diff --git a/zpu/build/CYC1000_zpu.qpf b/zpu/build/CYC1000_zpu.qpf
deleted file mode 100644
index b4d2262..0000000
--- a/zpu/build/CYC1000_zpu.qpf
+++ /dev/null
@@ -1,23 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-
-QUARTUS_VERSION = "5.0"
-DATE = "23:35:58 September 01, 2005"
-
-
-# Revisions
-
-PROJECT_REVISION = "CYC1000_zpu"
diff --git a/zpu/build/CYC1000_zpu.qsf b/zpu/build/CYC1000_zpu.qsf
deleted file mode 100644
index 9cdeaa3..0000000
--- a/zpu/build/CYC1000_zpu.qsf
+++ /dev/null
@@ -1,421 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2017 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other
-# applicable license agreement, including, without limitation,
-# that your use is for the sole purpose of programming logic
-# devices manufactured by Intel and sold by Intel or its
-# authorized distributors. Please refer to the applicable
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
-# Date created = 11:51:50 November 03, 2017
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-# cyc1000_nios_assignment_defaults.qdf
-# If this file doesn't exist, see file:
-# assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus Prime software
-# and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:51:50 NOVEMBER 03, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone 10 LP"
-set_global_assignment -name TOP_LEVEL_ENTITY CYC1000_zpu
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE 10CL025YU256C8G
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name ENABLE_OCT_DONE OFF
-set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "COMPILER CONFIGURED"
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-
-#============================================================
-# UART
-#============================================================
-set_location_assignment PIN_F13 -to UART_TX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
-set_location_assignment PIN_F15 -to UART_RX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
-set_location_assignment PIN_D15 -to UART_RX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
-set_location_assignment PIN_C15 -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-
-#============================================================
-# SD CARD
-#============================================================
-set_location_assignment PIN_F16 -to SDCARD_MISO[0]
-set_location_assignment PIN_D16 -to SDCARD_MOSI[0]
-set_location_assignment PIN_B16 -to SDCARD_CLK[0]
-set_location_assignment PIN_C16 -to SDCARD_CS[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
-
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_M2 -to CLOCK_12M
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_12M
-set_location_assignment PIN_E15 -to CLK_X
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK_X
-
-#============================================================
-# LED
-#============================================================
-set_location_assignment PIN_N3 -to LED[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
-set_location_assignment PIN_N5 -to LED[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
-set_location_assignment PIN_R4 -to LED[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
-set_location_assignment PIN_T2 -to LED[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
-set_location_assignment PIN_R3 -to LED[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
-set_location_assignment PIN_T3 -to LED[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
-set_location_assignment PIN_T4 -to LED[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
-set_location_assignment PIN_M6 -to LED[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
-
-#============================================================
-# SDRAM
-#============================================================
-# Data bus
-set_location_assignment PIN_B10 -to SDRAM_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
-set_location_assignment PIN_A10 -to SDRAM_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
-set_location_assignment PIN_B11 -to SDRAM_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
-set_location_assignment PIN_A11 -to SDRAM_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
-set_location_assignment PIN_A12 -to SDRAM_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
-set_location_assignment PIN_D9 -to SDRAM_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
-set_location_assignment PIN_B12 -to SDRAM_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
-set_location_assignment PIN_C9 -to SDRAM_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
-set_location_assignment PIN_D11 -to SDRAM_DQ[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
-set_location_assignment PIN_E11 -to SDRAM_DQ[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
-set_location_assignment PIN_A15 -to SDRAM_DQ[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
-set_location_assignment PIN_E9 -to SDRAM_DQ[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
-set_location_assignment PIN_D14 -to SDRAM_DQ[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
-set_location_assignment PIN_F9 -to SDRAM_DQ[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
-set_location_assignment PIN_C14 -to SDRAM_DQ[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
-set_location_assignment PIN_A14 -to SDRAM_DQ[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
-# Address Bus
-set_location_assignment PIN_A3 -to SDRAM_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0]
-set_location_assignment PIN_B5 -to SDRAM_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1]
-set_location_assignment PIN_B4 -to SDRAM_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2]
-set_location_assignment PIN_B3 -to SDRAM_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3]
-set_location_assignment PIN_C3 -to SDRAM_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4]
-set_location_assignment PIN_D3 -to SDRAM_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5]
-set_location_assignment PIN_E6 -to SDRAM_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6]
-set_location_assignment PIN_E7 -to SDRAM_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7]
-set_location_assignment PIN_D6 -to SDRAM_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8]
-set_location_assignment PIN_D8 -to SDRAM_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9]
-set_location_assignment PIN_A5 -to SDRAM_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10]
-set_location_assignment PIN_E8 -to SDRAM_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11]
-set_location_assignment PIN_A2 -to SDRAM_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12]
-set_location_assignment PIN_C6 -to SDRAM_ADDR[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[13]
-# Byte addressing
-set_location_assignment PIN_A4 -to SDRAM_BA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
-set_location_assignment PIN_B6 -to SDRAM_BA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
-set_location_assignment PIN_B13 -to SDRAM_DQM[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0]
-set_location_assignment PIN_D12 -to SDRAM_DQM[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1]
-# Chip control.
-set_location_assignment PIN_C8 -to SDRAM_CAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS
-set_location_assignment PIN_B7 -to SDRAM_RAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS
-set_location_assignment PIN_A7 -to SDRAM_WE
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE
-set_location_assignment PIN_A6 -to SDRAM_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS
-# Clock and enabling.
-set_location_assignment PIN_F8 -to SDRAM_CKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
-set_location_assignment PIN_B14 -to SDRAM_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
-
-#============================================================
-# FT2232H
-#============================================================
-# ADBUS
-set_location_assignment PIN_H3 -to ADBUS_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_0
-set_location_assignment PIN_H4 -to ADBUS_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_1
-set_location_assignment PIN_J4 -to ADBUS_2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_2
-set_location_assignment PIN_J5 -to ADBUS_3
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_3
-set_location_assignment PIN_M8 -to ADBUS_4
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_4
-set_location_assignment PIN_N8 -to ADBUS_7
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADBUS_7
-# BDBUS
-set_location_assignment PIN_R7 -to BDBUS[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[0]
-set_location_assignment PIN_T7 -to BDBUS[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[1]
-set_location_assignment PIN_R6 -to BDBUS[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[2]
-set_location_assignment PIN_T6 -to BDBUS[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[3]
-set_location_assignment PIN_R5 -to BDBUS[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[4]
-set_location_assignment PIN_T5 -to BDBUS[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BDBUS[5]
-
-#============================================================
-# Serial Configuration Memory
-#============================================================
-set_location_assignment PIN_H2 -to AS_DATA0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_DATA0
-set_location_assignment PIN_C1 -to AS_ASDO
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_ASDO
-set_location_assignment PIN_D2 -to AS_NCS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_NCS
-set_location_assignment PIN_H1 -to AS_DCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AS_DCLK
-
-#============================================================
-# PMOD IO Header PIO0 - PIO7
-#============================================================
-#set_location_assignment PIN_F13 -to PIO[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[1]
-#set_location_assignment PIN_F15 -to PIO[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[2]
-#set_location_assignment PIN_F16 -to PIO[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[3]
-#set_location_assignment PIN_D16 -to PIO[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[4]
-#set_location_assignment PIN_D15 -to PIO[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[5]
-#set_location_assignment PIN_C15 -to PIO[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[6]
-#set_location_assignment PIN_B16 -to PIO[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[7]
-#set_location_assignment PIN_C16 -to PIO[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PIO[8]
-
-#============================================================
-# GPIO14 - GPIO22 Header
-#============================================================
-set_location_assignment PIN_N2 -to GPIO[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14]
-set_location_assignment PIN_N1 -to GPIO[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15]
-set_location_assignment PIN_P2 -to GPIO[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16]
-set_location_assignment PIN_J1 -to GPIO[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17]
-set_location_assignment PIN_J2 -to GPIO[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18]
-set_location_assignment PIN_K2 -to GPIO[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19]
-set_location_assignment PIN_L2 -to GPIO[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20]
-set_location_assignment PIN_P1 -to GPIO[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21]
-set_location_assignment PIN_R1 -to GPIO[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22]
-
-#============================================================
-# GPIO8 - GPIO13 Header
-#============================================================
-set_location_assignment PIN_N16 -to GPIO[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8]
-set_location_assignment PIN_L15 -to GPIO[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9]
-set_location_assignment PIN_L16 -to GPIO[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10]
-set_location_assignment PIN_K15 -to GPIO[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11]
-set_location_assignment PIN_K16 -to GPIO[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12]
-set_location_assignment PIN_J14 -to GPIO[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13]
-set_location_assignment PIN_K1 -to D11_R
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D11_R
-set_location_assignment PIN_L1 -to D12_R
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to D12_R
-
-#============================================================
-# GPIO0 - GPIO7 Header
-#============================================================
-set_location_assignment PIN_T12 -to AIN
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AIN
-set_location_assignment PIN_P11 -to AREF
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AREF
-set_location_assignment PIN_R12 -to GPIO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0]
-set_location_assignment PIN_T13 -to GPIO[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1]
-set_location_assignment PIN_R13 -to GPIO[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2]
-set_location_assignment PIN_T14 -to GPIO[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3]
-set_location_assignment PIN_P14 -to GPIO[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4]
-set_location_assignment PIN_R14 -to GPIO[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5]
-set_location_assignment PIN_T15 -to GPIO[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6]
-set_location_assignment PIN_R11 -to GPIO[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7]
-
-#============================================================
-# Buttons
-#============================================================
-set_location_assignment PIN_N6 -to USER_BTN
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USER_BTN
-
-#============================================================
-# 3-Axis Accelerometer
-#============================================================
-set_location_assignment PIN_D1 -to SEN_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_CS
-set_location_assignment PIN_B1 -to SEN_INT1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_INT1
-set_location_assignment PIN_C2 -to SEN_INT2
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_INT2
-set_location_assignment PIN_G2 -to SEN_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SDI
-set_location_assignment PIN_G1 -to SEN_SDO
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SDO
-set_location_assignment PIN_F3 -to SEN_SPC
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SEN_SPC
-
-#============================================================
-# Modules and Files
-#============================================================
-#
-set_global_assignment -name VHDL_FILE ../CYC1000_zpu_Toplevel.vhd
-set_global_assignment -name QIP_FILE Clock_12to100.qip
-set_global_assignment -name SDC_FILE CYC1000_zpu_constraints.sdc
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
-#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
-set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/zpu/build/CYC1000_zpu_Toplevel.vhd b/zpu/build/CYC1000_zpu_Toplevel.vhd
deleted file mode 100644
index 5b600c4..0000000
--- a/zpu/build/CYC1000_zpu_Toplevel.vhd
+++ /dev/null
@@ -1,176 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.zpu_soc_pkg.all;
-
-entity CYC1000_zpu is
- port (
- -- Clock
- CLOCK_12M : in std_logic;
- -- LED
- LED : out std_logic_vector(7 downto 0);
- -- Debounced keys
--- KEY : in std_logic_vector(1 downto 0);
- -- DIP switches
--- SW : in std_logic_vector(3 downto 0);
- USER_BTN : in std_logic;
-
- -- TDI : in std_logic;
- -- TCK : in std_logic;
- -- TCS : in std_logic;
- -- TDO : out std_logic;
- -- I2C_SDAT : inout std_logic;
- -- I2C_SCLK : out std_logic;
- -- GPIO_0 : inout std_logic_vector(33 downto 0);
- -- GPIO_1 : inout std_logic_vector(33 downto 0);
-
- -- SD Card 1
- SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
-
- UART_RX_0 : in std_logic;
- UART_TX_0 : out std_logic;
- UART_RX_1 : in std_logic;
- UART_TX_1 : out std_logic;
-
- -- SDRAM signals
- SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
- SDRAM_CKE : out std_logic; -- clock enable.
- SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
- SDRAM_ADDR : out std_logic_vector(11 downto 0); -- 13 bit multiplexed address bus
- SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
- SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
- SDRAM_CS : out std_logic; -- a single chip select
- SDRAM_WE : out std_logic; -- write enable
- SDRAM_RAS : out std_logic; -- row address select
- SDRAM_CAS : out std_logic -- columns address select
- );
-END entity;
-
-architecture rtl of CYC1000_zpu is
-
- signal reset : std_logic;
- signal sysclk : std_logic;
- signal memclk : std_logic;
- signal pll_locked : std_logic;
-
- --signal ps2m_clk_in : std_logic;
- --signal ps2m_clk_out : std_logic;
- --signal ps2m_dat_in : std_logic;
- --signal ps2m_dat_out : std_logic;
-
- --signal ps2k_clk_in : std_logic;
- --signal ps2k_clk_out : std_logic;
- --signal ps2k_dat_in : std_logic;
- --signal ps2k_dat_out : std_logic;
-
- --alias PS2_MDAT : std_logic is GPIO_1(19);
- --alias PS2_MCLK : std_logic is GPIO_1(18);
-
-begin
-
---I2C_SDAT <= 'Z';
---GPIO_0(33 downto 2) <= (others => 'Z');
---GPIO_1 <= (others => 'Z');
---LED <= "101010" & reset & UART_RX_0;
-LED <= "00000000";
-
-mypll : entity work.Clock_12to100
-port map
-(
- inclk0 => CLOCK_12M,
- c0 => sysclk,
- c1 => memclk,
- locked => pll_locked
-);
-
---reset<=(not SW(0) xor KEY(0)) and pll_locked;
-reset<=(not USER_BTN) and pll_locked;
-
-myVirtualToplevel : entity work.zpu_soc
-generic map
-(
- SYSCLK_FREQUENCY => SYSCLK_CYC1000_FREQ
-)
-port map
-(
- SYSCLK => sysclk,
- MEMCLK => memclk,
- RESET_IN => reset,
-
- -- RS232
- UART_RX_0 => UART_RX_0,
- UART_TX_0 => UART_TX_0,
- UART_RX_1 => UART_RX_1,
- UART_TX_1 => UART_TX_1,
-
- -- SPI signals
- SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
- SPI_MOSI => open,
- SPI_CLK => open,
- SPI_CS => open,
-
- -- SD Card (SPI) signals
- SDCARD_MISO => SDCARD_MISO,
- SDCARD_MOSI => SDCARD_MOSI,
- SDCARD_CLK => SDCARD_CLK,
- SDCARD_CS => SDCARD_CS,
-
- -- PS/2 signals
- PS2K_CLK_IN => '1',
- PS2K_DAT_IN => '1',
- PS2K_CLK_OUT => open,
- PS2K_DAT_OUT => open,
- PS2M_CLK_IN => '1',
- PS2M_DAT_IN => '1',
- PS2M_CLK_OUT => open,
- PS2M_DAT_OUT => open,
-
- -- I²C signals
- I2C_SCL_IO => open,
- I2C_SDA_IO => open,
-
- -- IOCTL Bus --
- IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
- IOCTL_UPLOAD => open, -- Uploading from FPGA.
- IOCTL_CLK => open, -- I/O Clock.
- IOCTL_WR => open, -- Write Enable to FPGA.
- IOCTL_RD => open, -- Read Enable from FPGA.
- IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
- IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
- IOCTL_ADDR => open, -- Address in FPGA to write into.
- IOCTL_DOUT => open, -- Data to be written into FPGA.
- IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
-
- -- SDRAM signals
- SDRAM_CLK => SDRAM_CLK, -- sdram is accessed at 128MHz
- SDRAM_CKE => SDRAM_CKE, -- clock enable.
- SDRAM_DQ => SDRAM_DQ, -- 16 bit bidirectional data bus
- SDRAM_ADDR => SDRAM_ADDR, -- 13 bit multiplexed address bus
- SDRAM_DQM => SDRAM_DQM, -- two byte masks
- SDRAM_BA => SDRAM_BA, -- two banks
- SDRAM_CS_n => SDRAM_CS, -- a single chip select
- SDRAM_WE_n => SDRAM_WE, -- write enable
- SDRAM_RAS_n => SDRAM_RAS, -- row address select
- SDRAM_CAS_n => SDRAM_CAS, -- columns address select
- SDRAM_READY => open -- sd ready.
-
- -- DDR2 DRAM - doesnt exist on the QMV.
- --DDR2_ADDR => open, -- 14 bit multiplexed address bus
- --DDR2_DQ => open, -- 64 bit bidirectional data bus
- --DDR2_DQS => open, -- 8 bit bidirectional data bus
- --DDR2_DQM => open, -- eight byte masks
- --DDR2_ODT => open, -- 14 bit multiplexed address bus
- --DDR2_BA => open, -- 8 banks
- --DDR2_CS => open, -- 2 chip selects.
- --DDR2_WE => open, -- write enable
- --DDR2_RAS => open, -- row address select
- --DDR2_CAS => open, -- columns address select
- --DDR2_CKE => open, -- 2 clock enable.
- --DDR2_CLK => open -- 2 clocks.
-);
-
-
-end architecture;
diff --git a/zpu/build/CYC1000_zpu_constraints.sdc b/zpu/build/CYC1000_zpu_constraints.sdc
deleted file mode 100644
index 8d178e5..0000000
--- a/zpu/build/CYC1000_zpu_constraints.sdc
+++ /dev/null
@@ -1,135 +0,0 @@
-## Generated SDC file "E115_zpu.out.sdc"
-
-## Copyright (C) 2017 Intel Corporation. All rights reserved.
-## Your use of Intel Corporation's design tools, logic functions
-## and other software and tools, and its AMPP partner logic
-## functions, and any output files from any of the foregoing
-## (including device programming or simulation files), and any
-## associated documentation or information are expressly subject
-## to the terms and conditions of the Intel Program License
-## Subscription Agreement, the Intel Quartus Prime License Agreement,
-## the Intel FPGA IP License Agreement, or other applicable license
-## agreement, including, without limitation, that your use is for
-## the sole purpose of programming logic devices manufactured by
-## Intel and sold by Intel or its authorized distributors. Please
-## refer to the applicable agreement for further details.
-
-
-## VENDOR "Altera"
-## PROGRAM "Quartus Prime"
-## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
-
-## DATE "Sat Jun 22 23:32:00 2019"
-
-##
-## DEVICE "EP4CE115F23I7"
-##
-
-
-#**************************************************************
-# Time Information
-#**************************************************************
-
-set_time_format -unit ns -decimal_places 3
-
-
-
-#**************************************************************
-# Create Clock
-#**************************************************************
-
-create_clock -name {clk_12} -period 83.333 -waveform { 0.000 0.500 } [get_ports {CLOCK_12M}]
-
-
-#**************************************************************
-# Create Generated Clock
-#**************************************************************
-
-create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 25 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk0}]
-#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_12M}] -duty_cycle 50.000 -multiply_by 50 -divide_by 3 -master_clock {clk_12} [get_nets {mypll|altpll_component|_clk1}]
-
-#**************************************************************
-# Set Clock Latency
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Uncertainty
-#**************************************************************
-
-derive_clock_uncertainty
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
-
-
-#**************************************************************
-# Set Input Delay
-#**************************************************************
-
-# Delays for async signals - not necessary, but might as well avoid
-# having unconstrained ports in the design
-#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
-#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
-
-
-#**************************************************************
-# Set Output Delay
-#**************************************************************
-
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}]
-
-
-#**************************************************************
-# Set Clock Groups
-#**************************************************************
-
-
-
-#**************************************************************
-# Set False Path
-#**************************************************************
-
-set_false_path -from [get_keepers {USER_BTN*}]
-#set_false_path -from [get_keepers {SW*}]
-#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}]
-
-
-#**************************************************************
-# Set Multicycle Path
-#**************************************************************
-
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
-
-#**************************************************************
-# Set Maximum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Minimum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Input Transition
-#**************************************************************
-
diff --git a/zpu/build/Clock_12to100.cmp b/zpu/build/Clock_12to100.cmp
deleted file mode 100644
index e521c90..0000000
--- a/zpu/build/Clock_12to100.cmp
+++ /dev/null
@@ -1,25 +0,0 @@
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-component Clock_12to100
- PORT
- (
- areset : IN STD_LOGIC := '0';
- inclk0 : IN STD_LOGIC := '0';
- c0 : OUT STD_LOGIC ;
- c1 : OUT STD_LOGIC ;
- locked : OUT STD_LOGIC
- );
-end component;
diff --git a/zpu/build/Clock_12to100.ppf b/zpu/build/Clock_12to100.ppf
deleted file mode 100644
index 67075b3..0000000
--- a/zpu/build/Clock_12to100.ppf
+++ /dev/null
@@ -1,12 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/zpu/build/Clock_12to100.qip b/zpu/build/Clock_12to100.qip
deleted file mode 100644
index a0e38e1..0000000
--- a/zpu/build/Clock_12to100.qip
+++ /dev/null
@@ -1,5 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "13.0"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_12to100.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_12to100.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_12to100.ppf"]
diff --git a/zpu/build/Clock_12to100.vhd b/zpu/build/Clock_12to100.vhd
deleted file mode 100644
index 4f71e80..0000000
--- a/zpu/build/Clock_12to100.vhd
+++ /dev/null
@@ -1,397 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll
-
--- ============================================================
--- File Name: Clock_12to100.vhd
--- Megafunction Name(s):
--- altpll
---
--- Simulation Library Files(s):
--- altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY Clock_12to100 IS
- PORT
- (
- areset : IN STD_LOGIC := '0';
- inclk0 : IN STD_LOGIC := '0';
- c0 : OUT STD_LOGIC ;
- c1 : OUT STD_LOGIC ;
- locked : OUT STD_LOGIC
- );
-END Clock_12to100;
-
-
-ARCHITECTURE SYN OF clock_12to100 IS
-
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
- SIGNAL sub_wire1 : STD_LOGIC ;
- SIGNAL sub_wire2 : STD_LOGIC ;
- SIGNAL sub_wire3 : STD_LOGIC ;
- SIGNAL sub_wire4 : STD_LOGIC ;
- SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
- SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
- SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
- COMPONENT altpll
- GENERIC (
- clk0_divide_by : NATURAL;
- clk0_duty_cycle : NATURAL;
- clk0_multiply_by : NATURAL;
- clk0_phase_shift : STRING;
- clk1_divide_by : NATURAL;
- clk1_duty_cycle : NATURAL;
- clk1_multiply_by : NATURAL;
- clk1_phase_shift : STRING;
- compensate_clock : STRING;
- gate_lock_signal : STRING;
- inclk0_input_frequency : NATURAL;
- intended_device_family : STRING;
- invalid_lock_multiplier : NATURAL;
- lpm_hint : STRING;
- lpm_type : STRING;
- operation_mode : STRING;
- port_activeclock : STRING;
- port_areset : STRING;
- port_clkbad0 : STRING;
- port_clkbad1 : STRING;
- port_clkloss : STRING;
- port_clkswitch : STRING;
- port_configupdate : STRING;
- port_fbin : STRING;
- port_inclk0 : STRING;
- port_inclk1 : STRING;
- port_locked : STRING;
- port_pfdena : STRING;
- port_phasecounterselect : STRING;
- port_phasedone : STRING;
- port_phasestep : STRING;
- port_phaseupdown : STRING;
- port_pllena : STRING;
- port_scanaclr : STRING;
- port_scanclk : STRING;
- port_scanclkena : STRING;
- port_scandata : STRING;
- port_scandataout : STRING;
- port_scandone : STRING;
- port_scanread : STRING;
- port_scanwrite : STRING;
- port_clk0 : STRING;
- port_clk1 : STRING;
- port_clk2 : STRING;
- port_clk3 : STRING;
- port_clk4 : STRING;
- port_clk5 : STRING;
- port_clkena0 : STRING;
- port_clkena1 : STRING;
- port_clkena2 : STRING;
- port_clkena3 : STRING;
- port_clkena4 : STRING;
- port_clkena5 : STRING;
- port_extclk0 : STRING;
- port_extclk1 : STRING;
- port_extclk2 : STRING;
- port_extclk3 : STRING;
- valid_lock_multiplier : NATURAL
- );
- PORT (
- areset : IN STD_LOGIC ;
- clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
- inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
- locked : OUT STD_LOGIC
- );
- END COMPONENT;
-
-BEGIN
- sub_wire6_bv(0 DOWNTO 0) <= "0";
- sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
- sub_wire3 <= sub_wire0(0);
- sub_wire1 <= sub_wire0(1);
- c1 <= sub_wire1;
- locked <= sub_wire2;
- c0 <= sub_wire3;
- sub_wire4 <= inclk0;
- sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
-
- altpll_component : altpll
- GENERIC MAP (
- clk0_divide_by => 3,
- clk0_duty_cycle => 50,
- clk0_multiply_by => 25,
- clk0_phase_shift => "0",
- clk1_divide_by => 3,
- clk1_duty_cycle => 50,
- clk1_multiply_by => 50,
- clk1_phase_shift => "0",
- compensate_clock => "CLK0",
- gate_lock_signal => "NO",
- inclk0_input_frequency => 83333,
- intended_device_family => "Cyclone II",
- invalid_lock_multiplier => 5,
- lpm_hint => "CBX_MODULE_PREFIX=Clock_12to100",
- lpm_type => "altpll",
- operation_mode => "NORMAL",
- port_activeclock => "PORT_UNUSED",
- port_areset => "PORT_USED",
- port_clkbad0 => "PORT_UNUSED",
- port_clkbad1 => "PORT_UNUSED",
- port_clkloss => "PORT_UNUSED",
- port_clkswitch => "PORT_UNUSED",
- port_configupdate => "PORT_UNUSED",
- port_fbin => "PORT_UNUSED",
- port_inclk0 => "PORT_USED",
- port_inclk1 => "PORT_UNUSED",
- port_locked => "PORT_USED",
- port_pfdena => "PORT_UNUSED",
- port_phasecounterselect => "PORT_UNUSED",
- port_phasedone => "PORT_UNUSED",
- port_phasestep => "PORT_UNUSED",
- port_phaseupdown => "PORT_UNUSED",
- port_pllena => "PORT_UNUSED",
- port_scanaclr => "PORT_UNUSED",
- port_scanclk => "PORT_UNUSED",
- port_scanclkena => "PORT_UNUSED",
- port_scandata => "PORT_UNUSED",
- port_scandataout => "PORT_UNUSED",
- port_scandone => "PORT_UNUSED",
- port_scanread => "PORT_UNUSED",
- port_scanwrite => "PORT_UNUSED",
- port_clk0 => "PORT_USED",
- port_clk1 => "PORT_USED",
- port_clk2 => "PORT_UNUSED",
- port_clk3 => "PORT_UNUSED",
- port_clk4 => "PORT_UNUSED",
- port_clk5 => "PORT_UNUSED",
- port_clkena0 => "PORT_UNUSED",
- port_clkena1 => "PORT_UNUSED",
- port_clkena2 => "PORT_UNUSED",
- port_clkena3 => "PORT_UNUSED",
- port_clkena4 => "PORT_UNUSED",
- port_clkena5 => "PORT_UNUSED",
- port_extclk0 => "PORT_UNUSED",
- port_extclk1 => "PORT_UNUSED",
- port_extclk2 => "PORT_UNUSED",
- port_extclk3 => "PORT_UNUSED",
- valid_lock_multiplier => 1
- )
- PORT MAP (
- areset => areset,
- inclk => sub_wire5,
- clk => sub_wire0,
- locked => sub_wire2
- );
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_12to100.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
--- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
--- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/zpu/build/Clock_25to100.cmp b/zpu/build/Clock_25to100.cmp
deleted file mode 100644
index 09224bc..0000000
--- a/zpu/build/Clock_25to100.cmp
+++ /dev/null
@@ -1,25 +0,0 @@
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-component Clock_25to100
- PORT
- (
- areset : IN STD_LOGIC := '0';
- inclk0 : IN STD_LOGIC := '0';
- c0 : OUT STD_LOGIC ;
- c1 : OUT STD_LOGIC ;
- locked : OUT STD_LOGIC
- );
-end component;
diff --git a/zpu/build/Clock_25to100.ppf b/zpu/build/Clock_25to100.ppf
deleted file mode 100644
index feedea5..0000000
--- a/zpu/build/Clock_25to100.ppf
+++ /dev/null
@@ -1,12 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/zpu/build/Clock_25to100.qip b/zpu/build/Clock_25to100.qip
deleted file mode 100644
index b000805..0000000
--- a/zpu/build/Clock_25to100.qip
+++ /dev/null
@@ -1,5 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "13.0"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_25to100.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_25to100.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_25to100.ppf"]
diff --git a/zpu/build/Clock_25to100.vhd b/zpu/build/Clock_25to100.vhd
deleted file mode 100644
index 57699d6..0000000
--- a/zpu/build/Clock_25to100.vhd
+++ /dev/null
@@ -1,397 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll
-
--- ============================================================
--- File Name: Clock_25to100.vhd
--- Megafunction Name(s):
--- altpll
---
--- Simulation Library Files(s):
--- altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY Clock_25to100 IS
- PORT
- (
- areset : IN STD_LOGIC := '0';
- inclk0 : IN STD_LOGIC := '0';
- c0 : OUT STD_LOGIC ;
- c1 : OUT STD_LOGIC ;
- locked : OUT STD_LOGIC
- );
-END Clock_25to100;
-
-
-ARCHITECTURE SYN OF clock_25to100 IS
-
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
- SIGNAL sub_wire1 : STD_LOGIC ;
- SIGNAL sub_wire2 : STD_LOGIC ;
- SIGNAL sub_wire3 : STD_LOGIC ;
- SIGNAL sub_wire4 : STD_LOGIC ;
- SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
- SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
- SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
- COMPONENT altpll
- GENERIC (
- clk0_divide_by : NATURAL;
- clk0_duty_cycle : NATURAL;
- clk0_multiply_by : NATURAL;
- clk0_phase_shift : STRING;
- clk1_divide_by : NATURAL;
- clk1_duty_cycle : NATURAL;
- clk1_multiply_by : NATURAL;
- clk1_phase_shift : STRING;
- compensate_clock : STRING;
- gate_lock_signal : STRING;
- inclk0_input_frequency : NATURAL;
- intended_device_family : STRING;
- invalid_lock_multiplier : NATURAL;
- lpm_hint : STRING;
- lpm_type : STRING;
- operation_mode : STRING;
- port_activeclock : STRING;
- port_areset : STRING;
- port_clkbad0 : STRING;
- port_clkbad1 : STRING;
- port_clkloss : STRING;
- port_clkswitch : STRING;
- port_configupdate : STRING;
- port_fbin : STRING;
- port_inclk0 : STRING;
- port_inclk1 : STRING;
- port_locked : STRING;
- port_pfdena : STRING;
- port_phasecounterselect : STRING;
- port_phasedone : STRING;
- port_phasestep : STRING;
- port_phaseupdown : STRING;
- port_pllena : STRING;
- port_scanaclr : STRING;
- port_scanclk : STRING;
- port_scanclkena : STRING;
- port_scandata : STRING;
- port_scandataout : STRING;
- port_scandone : STRING;
- port_scanread : STRING;
- port_scanwrite : STRING;
- port_clk0 : STRING;
- port_clk1 : STRING;
- port_clk2 : STRING;
- port_clk3 : STRING;
- port_clk4 : STRING;
- port_clk5 : STRING;
- port_clkena0 : STRING;
- port_clkena1 : STRING;
- port_clkena2 : STRING;
- port_clkena3 : STRING;
- port_clkena4 : STRING;
- port_clkena5 : STRING;
- port_extclk0 : STRING;
- port_extclk1 : STRING;
- port_extclk2 : STRING;
- port_extclk3 : STRING;
- valid_lock_multiplier : NATURAL
- );
- PORT (
- areset : IN STD_LOGIC ;
- clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
- inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
- locked : OUT STD_LOGIC
- );
- END COMPONENT;
-
-BEGIN
- sub_wire6_bv(0 DOWNTO 0) <= "0";
- sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
- sub_wire3 <= sub_wire0(0);
- sub_wire1 <= sub_wire0(1);
- c1 <= sub_wire1;
- locked <= sub_wire2;
- c0 <= sub_wire3;
- sub_wire4 <= inclk0;
- sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
-
- altpll_component : altpll
- GENERIC MAP (
- clk0_divide_by => 1,
- clk0_duty_cycle => 50,
- clk0_multiply_by => 4,
- clk0_phase_shift => "0",
- clk1_divide_by => 1,
- clk1_duty_cycle => 50,
- clk1_multiply_by => 8,
- clk1_phase_shift => "0",
- compensate_clock => "CLK0",
- gate_lock_signal => "NO",
- inclk0_input_frequency => 40000,
- intended_device_family => "Cyclone II",
- invalid_lock_multiplier => 5,
- lpm_hint => "CBX_MODULE_PREFIX=Clock_25to100",
- lpm_type => "altpll",
- operation_mode => "NORMAL",
- port_activeclock => "PORT_UNUSED",
- port_areset => "PORT_USED",
- port_clkbad0 => "PORT_UNUSED",
- port_clkbad1 => "PORT_UNUSED",
- port_clkloss => "PORT_UNUSED",
- port_clkswitch => "PORT_UNUSED",
- port_configupdate => "PORT_UNUSED",
- port_fbin => "PORT_UNUSED",
- port_inclk0 => "PORT_USED",
- port_inclk1 => "PORT_UNUSED",
- port_locked => "PORT_USED",
- port_pfdena => "PORT_UNUSED",
- port_phasecounterselect => "PORT_UNUSED",
- port_phasedone => "PORT_UNUSED",
- port_phasestep => "PORT_UNUSED",
- port_phaseupdown => "PORT_UNUSED",
- port_pllena => "PORT_UNUSED",
- port_scanaclr => "PORT_UNUSED",
- port_scanclk => "PORT_UNUSED",
- port_scanclkena => "PORT_UNUSED",
- port_scandata => "PORT_UNUSED",
- port_scandataout => "PORT_UNUSED",
- port_scandone => "PORT_UNUSED",
- port_scanread => "PORT_UNUSED",
- port_scanwrite => "PORT_UNUSED",
- port_clk0 => "PORT_USED",
- port_clk1 => "PORT_USED",
- port_clk2 => "PORT_UNUSED",
- port_clk3 => "PORT_UNUSED",
- port_clk4 => "PORT_UNUSED",
- port_clk5 => "PORT_UNUSED",
- port_clkena0 => "PORT_UNUSED",
- port_clkena1 => "PORT_UNUSED",
- port_clkena2 => "PORT_UNUSED",
- port_clkena3 => "PORT_UNUSED",
- port_clkena4 => "PORT_UNUSED",
- port_clkena5 => "PORT_UNUSED",
- port_extclk0 => "PORT_UNUSED",
- port_extclk1 => "PORT_UNUSED",
- port_extclk2 => "PORT_UNUSED",
- port_extclk3 => "PORT_UNUSED",
- valid_lock_multiplier => 1
- )
- PORT MAP (
- areset => areset,
- inclk => sub_wire5,
- clk => sub_wire0,
- locked => sub_wire2
- );
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_25to100.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
--- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
--- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/zpu/build/Clock_50to100.cmp b/zpu/build/Clock_50to100.cmp
deleted file mode 100644
index 59524f7..0000000
--- a/zpu/build/Clock_50to100.cmp
+++ /dev/null
@@ -1,25 +0,0 @@
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-component Clock_50to100
- PORT
- (
- areset : IN STD_LOGIC := '0';
- inclk0 : IN STD_LOGIC := '0';
- c0 : OUT STD_LOGIC ;
- c1 : OUT STD_LOGIC ;
- locked : OUT STD_LOGIC
- );
-end component;
diff --git a/zpu/build/Clock_50to100.cnx b/zpu/build/Clock_50to100.cnx
deleted file mode 100644
index ff7e2b0..0000000
--- a/zpu/build/Clock_50to100.cnx
+++ /dev/null
@@ -1,209 +0,0 @@
-VERSION: WM1.0
-MODULE: altpll
-PRIVATE: ACTIVECLK_CHECK STRING "0"
-PRIVATE: BANDWIDTH STRING "1.000"
-PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-PRIVATE: BANDWIDTH_PRESET STRING "Low"
-PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-PRIVATE: CLKLOSS_CHECK STRING "0"
-PRIVATE: CLKSWITCH_CHECK STRING "1"
-PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-PRIVATE: CUR_FBIN_CLK STRING "c0"
-PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-PRIVATE: DIV_FACTOR0 NUMERIC "1"
-PRIVATE: DIV_FACTOR1 NUMERIC "1"
-PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-PRIVATE: LONG_SCAN_RADIO STRING "1"
-PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-PRIVATE: MIRROR_CLK0 STRING "0"
-PRIVATE: MIRROR_CLK1 STRING "0"
-PRIVATE: MULT_FACTOR0 NUMERIC "1"
-PRIVATE: MULT_FACTOR1 NUMERIC "1"
-PRIVATE: NORMAL_MODE_RADIO STRING "1"
-PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
-PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-PRIVATE: PLL_ARESET_CHECK STRING "1"
-PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-PRIVATE: PLL_ENA_CHECK STRING "0"
-PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-PRIVATE: PLL_PFDENA_CHECK STRING "0"
-PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif"
-PRIVATE: SACN_INPUTS_CHECK STRING "0"
-PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-PRIVATE: SHORT_SCAN_RADIO STRING "0"
-PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-PRIVATE: SPREAD_FREQ STRING "50.000"
-PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-PRIVATE: SPREAD_PERCENT STRING "0.500"
-PRIVATE: SPREAD_USE STRING "0"
-PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-PRIVATE: STICKY_CLK0 STRING "1"
-PRIVATE: STICKY_CLK1 STRING "1"
-PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-PRIVATE: USE_CLK0 STRING "1"
-PRIVATE: USE_CLK1 STRING "1"
-PRIVATE: USE_CLKENA0 STRING "0"
-PRIVATE: USE_CLKENA1 STRING "0"
-PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-PRIVATE: ZERO_DELAY_RADIO STRING "0"
-LIBRARY: altera_mf altera_mf.altera_mf_components.all
-CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
-CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
-CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
-CONSTANT: LPM_TYPE STRING "altpll"
-CONSTANT: OPERATION_MODE STRING "NORMAL"
-CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-CONSTANT: PORT_ARESET STRING "PORT_USED"
-CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-CONSTANT: PORT_LOCKED STRING "PORT_USED"
-CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-CONSTANT: PORT_clk0 STRING "PORT_USED"
-CONSTANT: PORT_clk1 STRING "PORT_USED"
-CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
-USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
-GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
-GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
-GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
-GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
-GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
-LIB_FILE: altera_mf
-
-LICENSE_ID: "DEVICE_FAMILY_Cyclone 10 LP" 10915102B3011615119A
-LICENSE_ID: "DEVICE_FAMILY_Cyclone IV E" 10915102A3011615119A
-LICENSE_ID: "DEVICE_FAMILY_Cyclone V" 10915102T3011615119M
-LICENSE_ID: "DEVICE_FAMILY_MAX V" 10915102H3011615119A
-LICENSE_ID: "DEVICE_FAMILY_Arria II GX" 10915102P3011615119S
-LICENSE_ID: "DEVICE_FAMILY_Cyclone IV GX" 10915102B3011615119A
-LICENSE_ID: "DEVICE_FAMILY_MAX II" 10915102N3011615119S
-LICENSE_ID: "DEVICE_FAMILY_MAX 10" 10915102N3011615119S
-LICENSE_ID: "FEATURE_STRATIXGX_DPA" 10915102V3011615119C
-LICENSE_ID: "FEATURE_STRATIXGX_BASIC" 10915102T3011615119M
-
-
-SUPPORTED_DEVICE_FAMILY: "Cyclone 10 LP"
-SUPPORTED_DEVICE_FAMILY: "Cyclone IV E"
-SUPPORTED_DEVICE_FAMILY: "Arria II GX"
-SUPPORTED_DEVICE_FAMILY: "Cyclone IV GX"
-SUPPORTED_DEVICE_FAMILY: "MAX 10"
-SUPPORTED_DEVICE_FAMILY: "Cyclone II"
-
-WIZARD_TITLE: "ALTPLL"
-QUARTUS_VERSION: "Version 17.0"
-QUARTUS_SVERSION: "17.0.2 Build 602 07/19/2017 SJ Lite Edition:07/19/2017"
-QUARTUS_BUILD_DATE: "07/19/2017"
-ALTERA_COPYRIGHT: "Copyright (C) 2017 Intel Corporation. All rights reserved."
-
-
-HELP_MENU_ITEM: FALSE "IUG$altpll Megafunction User Guide$http://www.altera.com/literature/ug/ug_altpll.pdf"
-HELP_MENU_ITEM: FALSE "IUG$General-Purpose PLLs in Stratix (GX) Devices$http://www.altera.com/literature/hb/stx/ch_1_vol_2.pdf"
-HELP_MENU_ITEM: FALSE "IUG$PLLs in Stratix II Devices$http://www.altera.com/literature/hb/stx2/stx2_sii52001.pdf"
-HELP_MENU_ITEM: FALSE "IUG$Clock Networks and PLLs in Stratix III Devices$http://www.altera.com/literature/hb/stx3/stx3_siii51006.pdf "
-HELP_MENU_ITEM: FALSE "IUG$PLLs in Cyclone II Devices$http://www.altera.com/literature/hb/cyc2/cyc2_cii51007.pdf"
diff --git a/zpu/build/Clock_50to100.cnxerr b/zpu/build/Clock_50to100.cnxerr
deleted file mode 100644
index 7b911a9..0000000
--- a/zpu/build/Clock_50to100.cnxerr
+++ /dev/null
@@ -1,7 +0,0 @@
-*******************************************
-** CNX File Error Log **
-*******************************************
-
-Line 0: WM1.0
- No valid wizard signature (generation mode ) found
-
diff --git a/zpu/build/Clock_50to100.ppf b/zpu/build/Clock_50to100.ppf
deleted file mode 100644
index ef75910..0000000
--- a/zpu/build/Clock_50to100.ppf
+++ /dev/null
@@ -1,12 +0,0 @@
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/zpu/build/Clock_50to100.qip b/zpu/build/Clock_50to100.qip
deleted file mode 100644
index 9ddc113..0000000
--- a/zpu/build/Clock_50to100.qip
+++ /dev/null
@@ -1,5 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "13.0"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "Clock_50to100.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_50to100.cmp"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "Clock_50to100.ppf"]
diff --git a/zpu/build/Clock_50to100.vhd b/zpu/build/Clock_50to100.vhd
deleted file mode 100644
index 70e444d..0000000
--- a/zpu/build/Clock_50to100.vhd
+++ /dev/null
@@ -1,399 +0,0 @@
--- megafunction wizard: %ALTPLL%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altpll
-
--- ============================================================
--- File Name: Clock_50to100.vhd
--- Megafunction Name(s):
--- altpll
---
--- Simulation Library Files(s):
--- altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions
---and other software and tools, and its AMPP partner logic
---functions, and any output files from any of the foregoing
---(including device programming or simulation files), and any
---associated documentation or information are expressly subject
---to the terms and conditions of the Altera Program License
---Subscription Agreement, Altera MegaCore Function License
---Agreement, or other applicable license agreement, including,
---without limitation, that your use is for the sole purpose of
---programming logic devices manufactured by Altera and sold by
---Altera or its authorized distributors. Please refer to the
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY Clock_50to100 IS
- PORT
- (
- areset : IN STD_LOGIC := '0';
- inclk0 : IN STD_LOGIC := '0';
- c0 : OUT STD_LOGIC ;
- c1 : OUT STD_LOGIC ;
- locked : OUT STD_LOGIC
- );
-END Clock_50to100;
-
-
-ARCHITECTURE SYN OF clock_50to100 IS
-
- SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
- SIGNAL sub_wire1 : STD_LOGIC ;
- SIGNAL sub_wire2 : STD_LOGIC ;
- SIGNAL sub_wire3 : STD_LOGIC ;
- SIGNAL sub_wire4 : STD_LOGIC ;
- SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
- SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
- SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-
-
- COMPONENT altpll
- GENERIC (
- bandwidth_type : STRING;
- clk0_divide_by : NATURAL;
- clk0_duty_cycle : NATURAL;
- clk0_multiply_by : NATURAL;
- clk0_phase_shift : STRING;
- clk1_divide_by : NATURAL;
- clk1_duty_cycle : NATURAL;
- clk1_multiply_by : NATURAL;
- clk1_phase_shift : STRING;
- compensate_clock : STRING;
- gate_lock_signal : STRING;
- inclk0_input_frequency : NATURAL;
- intended_device_family : STRING;
- invalid_lock_multiplier : NATURAL;
- lpm_hint : STRING;
- lpm_type : STRING;
- operation_mode : STRING;
- port_activeclock : STRING;
- port_areset : STRING;
- port_clkbad0 : STRING;
- port_clkbad1 : STRING;
- port_clkloss : STRING;
- port_clkswitch : STRING;
- port_configupdate : STRING;
- port_fbin : STRING;
- port_inclk0 : STRING;
- port_inclk1 : STRING;
- port_locked : STRING;
- port_pfdena : STRING;
- port_phasecounterselect : STRING;
- port_phasedone : STRING;
- port_phasestep : STRING;
- port_phaseupdown : STRING;
- port_pllena : STRING;
- port_scanaclr : STRING;
- port_scanclk : STRING;
- port_scanclkena : STRING;
- port_scandata : STRING;
- port_scandataout : STRING;
- port_scandone : STRING;
- port_scanread : STRING;
- port_scanwrite : STRING;
- port_clk0 : STRING;
- port_clk1 : STRING;
- port_clk2 : STRING;
- port_clk3 : STRING;
- port_clk4 : STRING;
- port_clk5 : STRING;
- port_clkena0 : STRING;
- port_clkena1 : STRING;
- port_clkena2 : STRING;
- port_clkena3 : STRING;
- port_clkena4 : STRING;
- port_clkena5 : STRING;
- port_extclk0 : STRING;
- port_extclk1 : STRING;
- port_extclk2 : STRING;
- port_extclk3 : STRING;
- valid_lock_multiplier : NATURAL
- );
- PORT (
- areset : IN STD_LOGIC ;
- clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
- inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
- locked : OUT STD_LOGIC
- );
- END COMPONENT;
-
-BEGIN
- sub_wire6_bv(0 DOWNTO 0) <= "0";
- sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
- sub_wire3 <= sub_wire0(0);
- sub_wire1 <= sub_wire0(1);
- c1 <= sub_wire1;
- locked <= sub_wire2;
- c0 <= sub_wire3;
- sub_wire4 <= inclk0;
- sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
-
- altpll_component : altpll
- GENERIC MAP (
- bandwidth_type => "AUTO",
- clk0_divide_by => 1,
- clk0_duty_cycle => 50,
- clk0_multiply_by => 2,
- clk0_phase_shift => "0",
- clk1_divide_by => 1,
- clk1_duty_cycle => 50,
- clk1_multiply_by => 2,
- clk1_phase_shift => "-2500 ps",
- compensate_clock => "CLK0",
- gate_lock_signal => "NO",
- inclk0_input_frequency => 20000,
- intended_device_family => "Cyclone V",
- invalid_lock_multiplier => 5,
- lpm_hint => "CBX_MODULE_PREFIX=Clock_50to100",
- lpm_type => "altpll",
- operation_mode => "NORMAL",
- port_activeclock => "PORT_UNUSED",
- port_areset => "PORT_USED",
- port_clkbad0 => "PORT_UNUSED",
- port_clkbad1 => "PORT_UNUSED",
- port_clkloss => "PORT_UNUSED",
- port_clkswitch => "PORT_UNUSED",
- port_configupdate => "PORT_UNUSED",
- port_fbin => "PORT_UNUSED",
- port_inclk0 => "PORT_USED",
- port_inclk1 => "PORT_UNUSED",
- port_locked => "PORT_USED",
- port_pfdena => "PORT_UNUSED",
- port_phasecounterselect => "PORT_UNUSED",
- port_phasedone => "PORT_UNUSED",
- port_phasestep => "PORT_UNUSED",
- port_phaseupdown => "PORT_UNUSED",
- port_pllena => "PORT_UNUSED",
- port_scanaclr => "PORT_UNUSED",
- port_scanclk => "PORT_UNUSED",
- port_scanclkena => "PORT_UNUSED",
- port_scandata => "PORT_UNUSED",
- port_scandataout => "PORT_UNUSED",
- port_scandone => "PORT_UNUSED",
- port_scanread => "PORT_UNUSED",
- port_scanwrite => "PORT_UNUSED",
- port_clk0 => "PORT_USED",
- port_clk1 => "PORT_USED",
- port_clk2 => "PORT_UNUSED",
- port_clk3 => "PORT_UNUSED",
- port_clk4 => "PORT_UNUSED",
- port_clk5 => "PORT_UNUSED",
- port_clkena0 => "PORT_UNUSED",
- port_clkena1 => "PORT_UNUSED",
- port_clkena2 => "PORT_UNUSED",
- port_clkena3 => "PORT_UNUSED",
- port_clkena4 => "PORT_UNUSED",
- port_clkena5 => "PORT_UNUSED",
- port_extclk0 => "PORT_UNUSED",
- port_extclk1 => "PORT_UNUSED",
- port_extclk2 => "PORT_UNUSED",
- port_extclk3 => "PORT_UNUSED",
- valid_lock_multiplier => 1
- )
- PORT MAP (
- areset => areset,
- inclk => sub_wire5,
- clk => sub_wire0,
- locked => sub_wire2
- );
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-2.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
--- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "Clock_50to100.mif"
--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-2000"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
--- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
--- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
--- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
--- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
--- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
--- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL Clock_50to100_inst.vhd FALSE
--- Retrieval info: LIB_FILE: altera_mf
--- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/zpu/build/DE0_nano_zpu.qpf b/zpu/build/DE0_nano_zpu.qpf
deleted file mode 100644
index 187422d..0000000
--- a/zpu/build/DE0_nano_zpu.qpf
+++ /dev/null
@@ -1,6 +0,0 @@
-DATE = "14:58:03 December 18, 2014"
-QUARTUS_VERSION = "14.0"
-
-# Revisions
-
-PROJECT_REVISION = "DE0_nano_zpu"
diff --git a/zpu/build/DE0_nano_zpu.qsf b/zpu/build/DE0_nano_zpu.qsf
deleted file mode 100644
index 6297314..0000000
--- a/zpu/build/DE0_nano_zpu.qsf
+++ /dev/null
@@ -1,476 +0,0 @@
-#============================================================
-# Build by Terasic System Builder
-#============================================================
-
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name DEVICE 5CSEMA4U23C6
-set_global_assignment -name TOP_LEVEL_ENTITY "DE0_nano_zpu"
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
-set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:58:03 DECEMBER 18,2014"
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
-
-
-#============================================================
-# ADC
-#============================================================
-set_location_assignment PIN_U9 -to ADC_CONVST
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST
-set_location_assignment PIN_V10 -to ADC_SCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK
-set_location_assignment PIN_AC4 -to ADC_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI
-set_location_assignment PIN_AD4 -to ADC_SDO
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO
-
-#============================================================
-# ARDUINO
-#============================================================
-set_location_assignment PIN_AG13 -to ARDUINO_IO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
-set_location_assignment PIN_AF13 -to ARDUINO_IO[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
-set_location_assignment PIN_AG10 -to ARDUINO_IO[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
-set_location_assignment PIN_AG9 -to ARDUINO_IO[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
-set_location_assignment PIN_U14 -to ARDUINO_IO[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
-set_location_assignment PIN_U13 -to ARDUINO_IO[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
-set_location_assignment PIN_AG8 -to ARDUINO_IO[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
-set_location_assignment PIN_AH8 -to ARDUINO_IO[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
-set_location_assignment PIN_AF17 -to ARDUINO_IO[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
-set_location_assignment PIN_AE15 -to ARDUINO_IO[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
-set_location_assignment PIN_AF15 -to ARDUINO_IO[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
-set_location_assignment PIN_AG16 -to ARDUINO_IO[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
-set_location_assignment PIN_AH11 -to ARDUINO_IO[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
-set_location_assignment PIN_AH12 -to ARDUINO_IO[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
-set_location_assignment PIN_AH9 -to ARDUINO_IO[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
-set_location_assignment PIN_AG11 -to ARDUINO_IO[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
-set_location_assignment PIN_AH7 -to ARDUINO_RESET_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
-
-#============================================================
-# CLOCK
-#============================================================
-#set_location_assignment PIN_V11 -to FPGA_CLK1_50
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
-set_location_assignment PIN_Y13 -to FPGA_CLK2_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
-set_location_assignment PIN_E11 -to FPGA_CLK3_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
-
-#set_location_assignment PIN_R8 -to CLOCK_50
-set_location_assignment PIN_V11 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# HPS
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2]
-set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3]
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N
-set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ
-set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C0_SDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
-
-#============================================================
-# KEY
-#============================================================
-set_location_assignment PIN_AH17 -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_location_assignment PIN_AH16 -to KEY[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-
-#============================================================
-# LED
-#============================================================
-set_location_assignment PIN_W15 -to LED[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
-set_location_assignment PIN_AA24 -to LED[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
-set_location_assignment PIN_V16 -to LED[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
-set_location_assignment PIN_V15 -to LED[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
-set_location_assignment PIN_AF26 -to LED[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
-set_location_assignment PIN_AE26 -to LED[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
-set_location_assignment PIN_Y16 -to LED[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
-set_location_assignment PIN_AA23 -to LED[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
-
-#============================================================
-# SW
-#============================================================
-set_location_assignment PIN_L10 -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_location_assignment PIN_L9 -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_location_assignment PIN_H6 -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_location_assignment PIN_H5 -to SW[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-
-#============================================================
-# GPIO_0, GPIO connect to GPIO Default
-#============================================================
-set_location_assignment PIN_V12 -to GPIO_0[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
-set_location_assignment PIN_AF7 -to GPIO_0[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
-set_location_assignment PIN_W12 -to GPIO_0[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
-set_location_assignment PIN_AF8 -to GPIO_0[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
-set_location_assignment PIN_Y8 -to GPIO_0[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
-set_location_assignment PIN_AB4 -to GPIO_0[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
-set_location_assignment PIN_W8 -to GPIO_0[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
-set_location_assignment PIN_Y4 -to GPIO_0[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
-set_location_assignment PIN_Y5 -to GPIO_0[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
-set_location_assignment PIN_U11 -to GPIO_0[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
-set_location_assignment PIN_T8 -to GPIO_0[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
-set_location_assignment PIN_T12 -to GPIO_0[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
-set_location_assignment PIN_AH5 -to GPIO_0[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
-set_location_assignment PIN_AH6 -to GPIO_0[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
-set_location_assignment PIN_AH4 -to GPIO_0[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
-set_location_assignment PIN_AG5 -to GPIO_0[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
-set_location_assignment PIN_AH3 -to GPIO_0[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
-set_location_assignment PIN_AH2 -to GPIO_0[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
-set_location_assignment PIN_AF4 -to GPIO_0[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
-set_location_assignment PIN_AG6 -to GPIO_0[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
-set_location_assignment PIN_AF5 -to GPIO_0[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
-set_location_assignment PIN_AE4 -to GPIO_0[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
-set_location_assignment PIN_T13 -to GPIO_0[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
-set_location_assignment PIN_T11 -to GPIO_0[23]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
-set_location_assignment PIN_AE7 -to GPIO_0[24]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
-set_location_assignment PIN_AF6 -to GPIO_0[25]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
-set_location_assignment PIN_AF9 -to GPIO_0[26]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
-set_location_assignment PIN_AE8 -to GPIO_0[27]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
-set_location_assignment PIN_AD10 -to GPIO_0[28]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
-set_location_assignment PIN_AE9 -to GPIO_0[29]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
-set_location_assignment PIN_AD11 -to GPIO_0[30]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
-set_location_assignment PIN_AF10 -to GPIO_0[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
-#set_location_assignment PIN_AD12 -to GPIO_0[32]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
-#set_location_assignment PIN_AE11 -to GPIO_0[33]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
-#set_location_assignment PIN_AF11 -to GPIO_0[34]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34]
-#set_location_assignment PIN_AE12 -to GPIO_0[35]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35]
-
-#============================================================
-# GPIO_1, GPIO connect to GPIO Default
-#============================================================
-set_location_assignment PIN_Y15 -to GPIO_1[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
-set_location_assignment PIN_AG28 -to GPIO_1[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
-set_location_assignment PIN_AA15 -to GPIO_1[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
-set_location_assignment PIN_AH27 -to GPIO_1[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
-set_location_assignment PIN_AG26 -to GPIO_1[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
-set_location_assignment PIN_AH24 -to GPIO_1[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
-set_location_assignment PIN_AF23 -to GPIO_1[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
-set_location_assignment PIN_AE22 -to GPIO_1[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
-set_location_assignment PIN_AF21 -to GPIO_1[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
-set_location_assignment PIN_AG20 -to GPIO_1[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
-set_location_assignment PIN_AG19 -to GPIO_1[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
-set_location_assignment PIN_AF20 -to GPIO_1[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
-set_location_assignment PIN_AC23 -to GPIO_1[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
-set_location_assignment PIN_AG18 -to GPIO_1[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
-set_location_assignment PIN_AH26 -to GPIO_1[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
-set_location_assignment PIN_AA19 -to GPIO_1[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
-set_location_assignment PIN_AG24 -to GPIO_1[16]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
-set_location_assignment PIN_AF25 -to GPIO_1[17]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
-set_location_assignment PIN_AH23 -to GPIO_1[18]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
-set_location_assignment PIN_AG23 -to GPIO_1[19]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
-set_location_assignment PIN_AE19 -to GPIO_1[20]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
-set_location_assignment PIN_AF18 -to GPIO_1[21]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
-set_location_assignment PIN_AD19 -to GPIO_1[22]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
-set_location_assignment PIN_AE20 -to GPIO_1[23]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
-set_location_assignment PIN_AE24 -to GPIO_1[24]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
-set_location_assignment PIN_AD20 -to GPIO_1[25]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
-set_location_assignment PIN_AF22 -to GPIO_1[26]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
-set_location_assignment PIN_AH22 -to GPIO_1[27]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
-set_location_assignment PIN_AH19 -to GPIO_1[28]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
-set_location_assignment PIN_AH21 -to GPIO_1[29]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
-set_location_assignment PIN_AG21 -to GPIO_1[30]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
-set_location_assignment PIN_AH18 -to GPIO_1[31]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
-set_location_assignment PIN_AD23 -to GPIO_1[32]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
-set_location_assignment PIN_AE23 -to GPIO_1[33]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
-set_location_assignment PIN_AA18 -to GPIO_1[34]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34]
-set_location_assignment PIN_AC22 -to GPIO_1[35]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35]
-
-
-set_location_assignment PIN_AE12 -to UART_TX_0
-set_location_assignment PIN_AE11 -to UART_RX_0
-set_location_assignment PIN_AF11 -to UART_TX_1
-set_location_assignment PIN_AD12 -to UART_RX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-
-#============================================================
-# End of pin assignments by Terasic System Builder
-#============================================================
-
-
-
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-
-set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
-
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-
-
-set_global_assignment -name VHDL_FILE ../DE0_nano_zpu_Toplevel.vhd
-set_global_assignment -name QIP_FILE Clock_50to100.qip
-set_global_assignment -name SDC_FILE DE0_nano_zpu_constraints.sdc
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
-#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
-#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip
-set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/zpu/build/DE0_nano_zpu.sdc b/zpu/build/DE0_nano_zpu.sdc
deleted file mode 100644
index e9e1fe7..0000000
--- a/zpu/build/DE0_nano_zpu.sdc
+++ /dev/null
@@ -1,92 +0,0 @@
-#**************************************************************
-# This .sdc file is created by Terasic Tool.
-# Users are recommended to modify this file to match users logic.
-#**************************************************************
-
-#**************************************************************
-# Create Clock
-#**************************************************************
-create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
-create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
-create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
-
-# for enhancing USB BlasterII to be reliable, 25MHz
-create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
-set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
-set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
-set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
-
-#**************************************************************
-# Create Generated Clock
-#**************************************************************
-derive_pll_clocks
-
-
-
-#**************************************************************
-# Set Clock Latency
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Uncertainty
-#**************************************************************
-derive_clock_uncertainty
-
-
-
-#**************************************************************
-# Set Input Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Output Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Groups
-#**************************************************************
-
-
-
-#**************************************************************
-# Set False Path
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Multicycle Path
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Maximum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Minimum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Input Transition
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Load
-#**************************************************************
-
-
-
diff --git a/zpu/build/DE0_nano_zpu_Toplevel.vhd b/zpu/build/DE0_nano_zpu_Toplevel.vhd
deleted file mode 100644
index b127e17..0000000
--- a/zpu/build/DE0_nano_zpu_Toplevel.vhd
+++ /dev/null
@@ -1,176 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.zpu_soc_pkg.all;
-
-entity DE0_nano_zpu is
- port (
- -- Clock
- CLOCK_50 : in std_logic;
- -- LED
- LED : out std_logic_vector(7 downto 0);
- -- Debounced keys
- KEY : in std_logic_vector(1 downto 0);
- -- DIP switches
- SW : in std_logic_vector(3 downto 0);
-
- TDI : out std_logic;
- TCK : out std_logic;
- TCS : out std_logic;
- TDO : in std_logic;
- -- I2C_SDAT : inout std_logic;
- -- I2C_SCLK : out std_logic;
- -- GPIO_0 : inout std_logic_vector(33 downto 0);
- -- GPIO_1 : inout std_logic_vector(33 downto 0);
-
- -- SD Card 1
- SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
-
- -- UART Serial channels.
- UART_RX_0 : in std_logic;
- UART_TX_0 : out std_logic;
- UART_RX_1 : in std_logic;
- UART_TX_1 : out std_logic
-
--- SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
--- SDRAM_CKE : out std_logic; -- clock enable.
--- SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
--- SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
--- SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
--- SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
--- SDRAM_CS : out std_logic; -- a single chip select
--- SDRAM_WE : out std_logic; -- write enable
--- SDRAM_RAS : out std_logic; -- row address select
--- SDRAM_CAS : out std_logic -- columns address select
- );
-END entity;
-
-architecture rtl of DE0_nano_zpu is
-
- signal reset : std_logic;
- signal sysclk : std_logic;
- signal memclk : std_logic;
- signal pll_locked : std_logic;
-
- --signal ps2m_clk_in : std_logic;
- --signal ps2m_clk_out : std_logic;
- --signal ps2m_dat_in : std_logic;
- --signal ps2m_dat_out : std_logic;
-
- --signal ps2k_clk_in : std_logic;
- --signal ps2k_clk_out : std_logic;
- --signal ps2k_dat_in : std_logic;
- --signal ps2k_dat_out : std_logic;
-
- --alias PS2_MDAT : std_logic is GPIO_1(19);
- --alias PS2_MCLK : std_logic is GPIO_1(18);
-
-begin
-
---I2C_SDAT <= 'Z';
---GPIO_0(33 downto 2) <= (others => 'Z');
---GPIO_1 <= (others => 'Z');
---LED <= "101010" & reset & UART_RX_0;
-LED <= "00000000";
-
-mypll : entity work.Clock_50to100
-port map
-(
- inclk0 => CLOCK_50,
- c0 => sysclk,
- c1 => memclk,
- locked => pll_locked
-);
-
-reset<=(not SW(0) xor KEY(0)) and pll_locked;
-
-myVirtualToplevel : entity work.zpu_soc
-generic map
-(
- SYSCLK_FREQUENCY => SYSCLK_DE0_FREQ
-)
-port map
-(
- SYSCLK => sysclk,
- MEMCLK => memclk,
- RESET_IN => reset,
-
- -- RS232
- UART_RX_0 => UART_RX_0,
- UART_TX_0 => UART_TX_0,
- UART_RX_1 => UART_RX_1,
- UART_TX_1 => UART_TX_1,
-
- -- SPI signals
- SPI_MISO => TDO, -- Allow the SPI interface not to be plumbed in.
- SPI_MOSI => TDI,
- SPI_CLK => TCK,
- SPI_CS => TCS,
-
- -- SD Card (SPI) signals
- SDCARD_MISO => SDCARD_MISO,
- SDCARD_MOSI => SDCARD_MOSI,
- SDCARD_CLK => SDCARD_CLK,
- SDCARD_CS => SDCARD_CS,
-
-
- -- PS/2 signals
- PS2K_CLK_IN => '1',
- PS2K_DAT_IN => '1',
- PS2K_CLK_OUT => open,
- PS2K_DAT_OUT => open,
- PS2M_CLK_IN => '1',
- PS2M_DAT_IN => '1',
- PS2M_CLK_OUT => open,
- PS2M_DAT_OUT => open,
-
- -- I²C signals
- I2C_SCL_IO => open,
- I2C_SDA_IO => open,
-
-
- -- IOCTL Bus --
- IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
- IOCTL_UPLOAD => open, -- Uploading from FPGA.
- IOCTL_CLK => open, -- I/O Clock.
- IOCTL_WR => open, -- Write Enable to FPGA.
- IOCTL_RD => open, -- Read Enable from FPGA.
- IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
- IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
- IOCTL_ADDR => open, -- Address in FPGA to write into.
- IOCTL_DOUT => open, -- Data to be written into FPGA.
- IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
-
- -- SDRAM signals
- SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
- SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
- SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
- SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
- SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
- SDRAM_BA => open, --SDRAM_BA, -- two banks
- SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
- SDRAM_WE_n => open, --SDRAM_WE, -- write enable
- SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
- SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
- SDRAM_READY => open
-
- -- DDR2 DRAM - doesnt exist on the QMV.
- --DDR2_ADDR => open, -- 14 bit multiplexed address bus
- --DDR2_DQ => open, -- 64 bit bidirectional data bus
- --DDR2_DQS => open, -- 8 bit bidirectional data bus
- --DDR2_DQM => open, -- eight byte masks
- --DDR2_ODT => open, -- 14 bit multiplexed address bus
- --DDR2_BA => open, -- 8 banks
- --DDR2_CS => open, -- 2 chip selects.
- --DDR2_WE => open, -- write enable
- --DDR2_RAS => open, -- row address select
- --DDR2_CAS => open, -- columns address select
- --DDR2_CKE => open, -- 2 clock enable.
- --DDR2_CLK => open -- 2 clocks.
-);
-
-
-end architecture;
diff --git a/zpu/build/DE0_nano_zpu_constraints.sdc b/zpu/build/DE0_nano_zpu_constraints.sdc
deleted file mode 100644
index a46c71d..0000000
--- a/zpu/build/DE0_nano_zpu_constraints.sdc
+++ /dev/null
@@ -1,137 +0,0 @@
-## Generated SDC file "hello_led.out.sdc"
-
-## Copyright (C) 1991-2011 Altera Corporation
-## Your use of Altera Corporation's design tools, logic functions
-## and other software and tools, and its AMPP partner logic
-## functions, and any output files from any of the foregoing
-## (including device programming or simulation files), and any
-## associated documentation or information are expressly subject
-## to the terms and conditions of the Altera Program License
-## Subscription Agreement, Altera MegaCore Function License
-## Agreement, or other applicable license agreement, including,
-## without limitation, that your use is for the sole purpose of
-## programming logic devices manufactured by Altera and sold by
-## Altera or its authorized distributors. Please refer to the
-## applicable agreement for further details.
-
-
-## VENDOR "Altera"
-## PROGRAM "Quartus II"
-## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition"
-
-## DATE "Fri Jul 06 23:05:47 2012"
-
-##
-## DEVICE "EP3C25Q240C8"
-##
-
-
-#**************************************************************
-# Time Information
-#**************************************************************
-
-set_time_format -unit ns -decimal_places 3
-
-
-#**************************************************************
-# Create Clock
-#**************************************************************
-
-create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}]
-
-
-#**************************************************************
-# Create Generated Clock
-#**************************************************************
-
-create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -multiply_by 12 -divide_by 2 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]}]
-create_generated_clock -name {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 3 -master_clock {mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL|vcoph[0]} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}]
-
-#**************************************************************
-# Set Clock Latency
-#**************************************************************
-
-
-#**************************************************************
-# Set Clock Uncertainty
-#**************************************************************
-
-set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
-set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
-set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
-set_clock_uncertainty -rise_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
-set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
-set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -rise_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
-set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -setup 0.080
-set_clock_uncertainty -fall_from [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -fall_to [get_clocks {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}] -hold 0.060
-#derive_clock_uncertainty
-
-
-#**************************************************************
-# Set Input Delay
-#**************************************************************
-
-
-# Delays for async signals - not necessary, but might as well avoid
-# having unconstrained ports in the design
-#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
-#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
-
-#**************************************************************
-# Set Output Delay
-#**************************************************************
-
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}]
-
-
-#**************************************************************
-# Set Clock Groups
-#**************************************************************
-
-
-
-#**************************************************************
-# Set False Path
-#**************************************************************
-
-set_false_path -from [get_keepers {KEY*}]
-set_false_path -from [get_keepers {SW*}]
-#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}]
-
-
-#**************************************************************
-# Set Multicycle Path
-#**************************************************************
-
-#set_multicycle_path -setup -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 1
-#set_multicycle_path -hold -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 0
-
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
-
-#**************************************************************
-# Set Maximum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Minimum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Input Transition
-#**************************************************************
diff --git a/zpu/build/DE10_nano_zpu.qpf b/zpu/build/DE10_nano_zpu.qpf
deleted file mode 100644
index 957cc5f..0000000
--- a/zpu/build/DE10_nano_zpu.qpf
+++ /dev/null
@@ -1,32 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2016 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other
-# applicable license agreement, including, without limitation,
-# that your use is for the sole purpose of programming logic
-# devices manufactured by Intel and sold by Intel or its
-# authorized distributors. Please refer to the applicable
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
-# Date created = 15:48:30 August 02, 2017
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "16.1"
-DATE = "15:48:30 August 02, 2017"
-
-# Revisions
-
-PROJECT_REVISION = "DE10_nano_zpu"
-PROJECT_REVISION = "DE10_nano_zpu"
diff --git a/zpu/build/DE10_nano_zpu.qsf b/zpu/build/DE10_nano_zpu.qsf
deleted file mode 100644
index da45b46..0000000
--- a/zpu/build/DE10_nano_zpu.qsf
+++ /dev/null
@@ -1,498 +0,0 @@
-#============================================================
-# Build by Terasic System Builder
-#============================================================
-
-set_global_assignment -name DEVICE 5CSEBA6U23I7
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
-set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:00 FEBRUARY 21,2011"
-set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name GENERATE_RBF_FILE ON
-
-
-#============================================================
-# UART
-#============================================================
-set_location_assignment PIN_Y15 -to UART_TX_0
-set_location_assignment PIN_AA15 -to UART_RX_0
-set_location_assignment PIN_AG28 -to UART_TX_1
-set_location_assignment PIN_AG26 -to UART_RX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-
-#============================================================
-# SD CARD
-#============================================================
-set_location_assignment PIN_AF25 -to SDCARD_MISO[0]
-set_location_assignment PIN_AF27 -to SDCARD_MOSI[0]
-set_location_assignment PIN_AH26 -to SDCARD_CLK[0]
-set_location_assignment PIN_AF28 -to SDCARD_CS[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
-
-#============================================================
-# CLOCK
-#============================================================
-#set_location_assignment PIN_R8 -to CLOCK_50
-set_location_assignment PIN_V11 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# LED
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
-set_location_assignment PIN_W15 -to LED[0]
-set_location_assignment PIN_AA24 -to LED[1]
-set_location_assignment PIN_V16 -to LED[2]
-set_location_assignment PIN_V15 -to LED[3]
-set_location_assignment PIN_AF26 -to LED[4]
-set_location_assignment PIN_AE26 -to LED[5]
-set_location_assignment PIN_Y16 -to LED[6]
-set_location_assignment PIN_AA23 -to LED[7]
-
-#============================================================
-# KEY
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_location_assignment PIN_AH17 -to KEY[0]
-set_location_assignment PIN_AH16 -to KEY[1]
-
-#============================================================
-# SW
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_location_assignment PIN_Y24 -to SW[0]
-set_location_assignment PIN_W24 -to SW[1]
-set_location_assignment PIN_W21 -to SW[2]
-set_location_assignment PIN_W20 -to SW[3]
-
-#============================================================
-# SDIO
-#============================================================
-#set_location_assignment PIN_AF25 -to SDIO_DAT[0]
-#set_location_assignment PIN_AF23 -to SDIO_DAT[1]
-#set_location_assignment PIN_AD26 -to SDIO_DAT[2]
-#set_location_assignment PIN_AF28 -to SDIO_DAT[3]
-#set_location_assignment PIN_AF27 -to SDIO_CMD
-#set_location_assignment PIN_AH26 -to SDIO_CLK
-#set_location_assignment PIN_AH7 -to SDIO_CD
-#set_location_assignment PIN_AF25 -to TDO
-#set_location_assignment PIN_AF28 -to TCS
-#set_location_assignment PIN_AF27 -to TDI
-#set_location_assignment PIN_AH26 -to TCK
-
-#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_*
-
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDO
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TDI
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TCS
-#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TDO
-#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TCS
-#set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TDI
-
-#============================================================
-# SDRAM
-#============================================================
-#set_location_assignment PIN_M7 -to SDRAM_BA[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
-#set_location_assignment PIN_M6 -to SDRAM_BA[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
-#set_location_assignment PIN_R6 -to SDRAM_DQM[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0]
-#set_location_assignment PIN_T5 -to SDRAM_DQM[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1]
-#set_location_assignment PIN_L2 -to SDRAM_RAS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS_N
-#set_location_assignment PIN_L1 -to SDRAM_CAS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS_N
-#set_location_assignment PIN_L7 -to SDRAM_CKE
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
-#set_location_assignment PIN_R4 -to SDRAM_CLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
-#set_location_assignment PIN_C2 -to SDRAM_WE_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE_N
-#set_location_assignment PIN_P6 -to SDRAM_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS_N
-#set_location_assignment PIN_G2 -to SDRAM_DQ[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
-#set_location_assignment PIN_G1 -to SDRAM_DQ[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
-#set_location_assignment PIN_L8 -to SDRAM_DQ[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
-#set_location_assignment PIN_K5 -to SDRAM_DQ[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
-#set_location_assignment PIN_K2 -to SDRAM_DQ[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
-#set_location_assignment PIN_J2 -to SDRAM_DQ[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
-#set_location_assignment PIN_J1 -to SDRAM_DQ[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
-#set_location_assignment PIN_R7 -to SDRAM_DQ[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
-#set_location_assignment PIN_T4 -to SDRAM_DQ[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
-#set_location_assignment PIN_T2 -to SDRAM_DQ[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
-#set_location_assignment PIN_T3 -to SDRAM_DQ[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
-#set_location_assignment PIN_R3 -to SDRAM_DQ[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
-#set_location_assignment PIN_R5 -to SDRAM_DQ[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
-#set_location_assignment PIN_P3 -to SDRAM_DQ[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
-#set_location_assignment PIN_N3 -to SDRAM_DQ[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
-#set_location_assignment PIN_K1 -to SDRAM_DQ[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
-#set_location_assignment PIN_P2 -to SDRAM_ADDR[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0]
-#set_location_assignment PIN_N5 -to SDRAM_ADDR[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1]
-#set_location_assignment PIN_N6 -to SDRAM_ADDR[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2]
-#set_location_assignment PIN_M8 -to SDRAM_ADDR[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3]
-#set_location_assignment PIN_P8 -to SDRAM_ADDR[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4]
-#set_location_assignment PIN_T7 -to SDRAM_ADDR[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5]
-#set_location_assignment PIN_N8 -to SDRAM_ADDR[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6]
-#set_location_assignment PIN_T6 -to SDRAM_ADDR[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7]
-#set_location_assignment PIN_R1 -to SDRAM_ADDR[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8]
-#set_location_assignment PIN_P1 -to SDRAM_ADDR[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9]
-#set_location_assignment PIN_N2 -to SDRAM_ADDR[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10]
-#set_location_assignment PIN_N1 -to SDRAM_ADDR[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11]
-#set_location_assignment PIN_L4 -to SDRAM_ADDR[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12]
-
-#============================================================
-# EPCS
-#============================================================
-#set_location_assignment PIN_H2 -to EPCS_DATA0
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0
-#set_location_assignment PIN_H1 -to EPCS_DCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK
-#set_location_assignment PIN_D2 -to EPCS_NCSO
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO
-#set_location_assignment PIN_C1 -to EPCS_ASDO
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO
-
-#============================================================
-# Accelerometer and EEPROM
-#============================================================
-#set_location_assignment PIN_F2 -to I2C_SCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
-#set_location_assignment PIN_F1 -to I2C_SDAT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
-#set_location_assignment PIN_G5 -to G_SENSOR_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N
-#set_location_assignment PIN_M2 -to G_SENSOR_INT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT
-
-#============================================================
-# ADC
-#============================================================
-#set_location_assignment PIN_A10 -to ADC_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
-#set_location_assignment PIN_B10 -to ADC_SADDR
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR
-#set_location_assignment PIN_B14 -to ADC_SCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
-#set_location_assignment PIN_A9 -to ADC_SDAT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT
-
-#============================================================
-# 2x13 GPIO Header
-#============================================================
-#set_location_assignment PIN_A14 -to GPIO_2[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0]
-#set_location_assignment PIN_B16 -to GPIO_2[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1]
-#set_location_assignment PIN_C14 -to GPIO_2[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2]
-#set_location_assignment PIN_C16 -to GPIO_2[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3]
-#set_location_assignment PIN_C15 -to GPIO_2[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4]
-#set_location_assignment PIN_D16 -to GPIO_2[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5]
-#set_location_assignment PIN_D15 -to GPIO_2[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6]
-#set_location_assignment PIN_D14 -to GPIO_2[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7]
-#set_location_assignment PIN_F15 -to GPIO_2[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8]
-#set_location_assignment PIN_F16 -to GPIO_2[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9]
-#set_location_assignment PIN_F14 -to GPIO_2[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10]
-#set_location_assignment PIN_G16 -to GPIO_2[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11]
-#set_location_assignment PIN_G15 -to GPIO_2[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12]
-#set_location_assignment PIN_E15 -to GPIO_2_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0]
-#set_location_assignment PIN_E16 -to GPIO_2_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1]
-#set_location_assignment PIN_M16 -to GPIO_2_IN[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2]
-
-#============================================================
-# GPIO_0, GPIO_0 connect to GPIO Default
-#============================================================
-#set_location_assignment PIN_A8 -to GPIO_0_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0]
-#set_location_assignment PIN_D3 -to GPIO_0[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
-#set_location_assignment PIN_B8 -to GPIO_0_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1]
-#set_location_assignment PIN_C3 -to GPIO_0[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
-#set_location_assignment PIN_A2 -to GPIO_0[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
-#set_location_assignment PIN_A3 -to GPIO_0[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
-#set_location_assignment PIN_B3 -to GPIO_0[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
-#set_location_assignment PIN_B4 -to GPIO_0[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
-#set_location_assignment PIN_A4 -to GPIO_0[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
-#set_location_assignment PIN_B5 -to GPIO_0[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
-#set_location_assignment PIN_A5 -to GPIO_0[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
-#set_location_assignment PIN_D5 -to GPIO_0[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
-#set_location_assignment PIN_B6 -to GPIO_0[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
-#set_location_assignment PIN_A6 -to GPIO_0[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
-#set_location_assignment PIN_B7 -to GPIO_0[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
-#set_location_assignment PIN_D6 -to GPIO_0[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
-#set_location_assignment PIN_A7 -to GPIO_0[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
-#set_location_assignment PIN_C6 -to GPIO_0[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
-#set_location_assignment PIN_C8 -to GPIO_0[16]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
-#set_location_assignment PIN_E6 -to GPIO_0[17]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
-#set_location_assignment PIN_E7 -to GPIO_0[18]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
-#set_location_assignment PIN_D8 -to GPIO_0[19]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
-#set_location_assignment PIN_E8 -to GPIO_0[20]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
-#set_location_assignment PIN_F8 -to GPIO_0[21]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
-#set_location_assignment PIN_F9 -to GPIO_0[22]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
-#set_location_assignment PIN_E9 -to GPIO_0[23]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
-#set_location_assignment PIN_C9 -to GPIO_0[24]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
-#set_location_assignment PIN_D9 -to GPIO_0[25]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
-#set_location_assignment PIN_E11 -to GPIO_0[26]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
-#set_location_assignment PIN_E10 -to GPIO_0[27]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
-#set_location_assignment PIN_C11 -to GPIO_0[28]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
-#set_location_assignment PIN_B11 -to GPIO_0[29]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
-#set_location_assignment PIN_A12 -to GPIO_0[30]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
-#set_location_assignment PIN_D11 -to GPIO_0[31]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
-#set_location_assignment PIN_D12 -to GPIO_0[32]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
-#set_location_assignment PIN_B12 -to GPIO_0[33]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
-
-#============================================================
-# GPIO_1, GPIO_1 connect to GPIO Default
-#============================================================
-#set_location_assignment PIN_T9 -to GPIO_1_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0]
-#set_location_assignment PIN_F13 -to GPIO_1[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
-#set_location_assignment PIN_R9 -to GPIO_1_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1]
-#set_location_assignment PIN_T15 -to GPIO_1[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
-#set_location_assignment PIN_T14 -to GPIO_1[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
-#set_location_assignment PIN_T13 -to GPIO_1[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
-#set_location_assignment PIN_R13 -to GPIO_1[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
-#set_location_assignment PIN_T12 -to GPIO_1[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
-#set_location_assignment PIN_R12 -to GPIO_1[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
-#set_location_assignment PIN_T11 -to GPIO_1[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
-#set_location_assignment PIN_T10 -to GPIO_1[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
-#set_location_assignment PIN_R11 -to GPIO_1[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
-#set_location_assignment PIN_P11 -to GPIO_1[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
-#set_location_assignment PIN_R10 -to GPIO_1[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
-#set_location_assignment PIN_N12 -to GPIO_1[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
-#set_location_assignment PIN_P9 -to GPIO_1[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
-#set_location_assignment PIN_N9 -to GPIO_1[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
-#set_location_assignment PIN_N11 -to GPIO_1[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
-#set_location_assignment PIN_L16 -to GPIO_1[16]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
-#set_location_assignment PIN_K16 -to GPIO_1[17]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
-#set_location_assignment PIN_R16 -to GPIO_1[18]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
-#set_location_assignment PIN_L15 -to GPIO_1[19]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
-#set_location_assignment PIN_P15 -to GPIO_1[20]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
-#set_location_assignment PIN_P16 -to GPIO_1[21]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
-#set_location_assignment PIN_R14 -to GPIO_1[22]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
-#set_location_assignment PIN_N16 -to GPIO_1[23]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
-#set_location_assignment PIN_N15 -to GPIO_1[24]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
-#set_location_assignment PIN_P14 -to GPIO_1[25]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
-#set_location_assignment PIN_L14 -to GPIO_1[26]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
-#set_location_assignment PIN_N14 -to GPIO_1[27]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
-#set_location_assignment PIN_M10 -to GPIO_1[28]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
-#set_location_assignment PIN_L13 -to GPIO_1[29]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
-#set_location_assignment PIN_J16 -to GPIO_1[30]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
-#set_location_assignment PIN_K15 -to GPIO_1[31]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
-#set_location_assignment PIN_J13 -to GPIO_1[32]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
-#set_location_assignment PIN_J14 -to GPIO_1[33]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
-
-#============================================================
-# End of pin assignments by Terasic System Builder
-#============================================================
-
-
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[*]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQM[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N
-
-set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
-
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-
-
-set_global_assignment -name VHDL_FILE ../DE10_nano_zpu_Toplevel.vhd
-set_global_assignment -name QIP_FILE Clock_50to100.qip
-set_global_assignment -name SDC_FILE DE10_nano_zpu_constraints.sdc
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
-#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
-
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip
-set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/zpu/build/DE10_nano_zpu.qsf.1405 b/zpu/build/DE10_nano_zpu.qsf.1405
deleted file mode 100644
index 4faf2d3..0000000
--- a/zpu/build/DE10_nano_zpu.qsf.1405
+++ /dev/null
@@ -1,478 +0,0 @@
-#============================================================
-# Build by Terasic System Builder
-#============================================================
-
-set_global_assignment -name DEVICE 5CSEBA6U23I7
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
-set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:00 FEBRUARY 21,2011"
-set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name GENERATE_RBF_FILE ON
-
-
-set_location_assignment PIN_AA13 -to UART_TX_0
-set_location_assignment PIN_AA11 -to UART_RX_0
-set_location_assignment PIN_Y11 -to UART_TX_1
-set_location_assignment PIN_AA26 -to UART_RX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-
-#============================================================
-# CLOCK
-#============================================================
-#set_location_assignment PIN_R8 -to CLOCK_50
-set_location_assignment PIN_V11 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# LED
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
-set_location_assignment PIN_W15 -to LED[0]
-set_location_assignment PIN_AA24 -to LED[1]
-set_location_assignment PIN_V16 -to LED[2]
-set_location_assignment PIN_V15 -to LED[3]
-set_location_assignment PIN_AF26 -to LED[4]
-set_location_assignment PIN_AE26 -to LED[5]
-set_location_assignment PIN_Y16 -to LED[6]
-set_location_assignment PIN_AA23 -to LED[7]
-
-#============================================================
-# KEY
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_location_assignment PIN_AH17 -to KEY[0]
-set_location_assignment PIN_AH16 -to KEY[1]
-
-#============================================================
-# SW
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_location_assignment PIN_Y24 -to SW[0]
-set_location_assignment PIN_W24 -to SW[1]
-set_location_assignment PIN_W21 -to SW[2]
-set_location_assignment PIN_W20 -to SW[3]
-
-#============================================================
-# SDRAM
-#============================================================
-#set_location_assignment PIN_M7 -to DRAM_BA[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
-#set_location_assignment PIN_M6 -to DRAM_BA[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
-#set_location_assignment PIN_R6 -to DRAM_DQM[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
-#set_location_assignment PIN_T5 -to DRAM_DQM[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
-#set_location_assignment PIN_L2 -to DRAM_RAS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
-#set_location_assignment PIN_L1 -to DRAM_CAS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
-#set_location_assignment PIN_L7 -to DRAM_CKE
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
-#set_location_assignment PIN_R4 -to DRAM_CLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
-#set_location_assignment PIN_C2 -to DRAM_WE_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
-#set_location_assignment PIN_P6 -to DRAM_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
-#set_location_assignment PIN_G2 -to DRAM_DQ[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
-#set_location_assignment PIN_G1 -to DRAM_DQ[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
-#set_location_assignment PIN_L8 -to DRAM_DQ[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
-#set_location_assignment PIN_K5 -to DRAM_DQ[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
-#set_location_assignment PIN_K2 -to DRAM_DQ[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
-#set_location_assignment PIN_J2 -to DRAM_DQ[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
-#set_location_assignment PIN_J1 -to DRAM_DQ[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
-#set_location_assignment PIN_R7 -to DRAM_DQ[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
-#set_location_assignment PIN_T4 -to DRAM_DQ[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
-#set_location_assignment PIN_T2 -to DRAM_DQ[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
-#set_location_assignment PIN_T3 -to DRAM_DQ[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
-#set_location_assignment PIN_R3 -to DRAM_DQ[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
-#set_location_assignment PIN_R5 -to DRAM_DQ[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
-#set_location_assignment PIN_P3 -to DRAM_DQ[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
-#set_location_assignment PIN_N3 -to DRAM_DQ[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
-#set_location_assignment PIN_K1 -to DRAM_DQ[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
-#set_location_assignment PIN_P2 -to DRAM_ADDR[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
-#set_location_assignment PIN_N5 -to DRAM_ADDR[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
-#set_location_assignment PIN_N6 -to DRAM_ADDR[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
-#set_location_assignment PIN_M8 -to DRAM_ADDR[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
-#set_location_assignment PIN_P8 -to DRAM_ADDR[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
-#set_location_assignment PIN_T7 -to DRAM_ADDR[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
-#set_location_assignment PIN_N8 -to DRAM_ADDR[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
-#set_location_assignment PIN_T6 -to DRAM_ADDR[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
-#set_location_assignment PIN_R1 -to DRAM_ADDR[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
-#set_location_assignment PIN_P1 -to DRAM_ADDR[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
-#set_location_assignment PIN_N2 -to DRAM_ADDR[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
-#set_location_assignment PIN_N1 -to DRAM_ADDR[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
-#set_location_assignment PIN_L4 -to DRAM_ADDR[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
-
-#============================================================
-# EPCS
-#============================================================
-#set_location_assignment PIN_H2 -to EPCS_DATA0
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0
-#set_location_assignment PIN_H1 -to EPCS_DCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK
-#set_location_assignment PIN_D2 -to EPCS_NCSO
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO
-#set_location_assignment PIN_C1 -to EPCS_ASDO
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO
-
-#============================================================
-# Accelerometer and EEPROM
-#============================================================
-#set_location_assignment PIN_F2 -to I2C_SCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
-#set_location_assignment PIN_F1 -to I2C_SDAT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
-#set_location_assignment PIN_G5 -to G_SENSOR_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N
-#set_location_assignment PIN_M2 -to G_SENSOR_INT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT
-
-#============================================================
-# ADC
-#============================================================
-#set_location_assignment PIN_A10 -to ADC_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
-#set_location_assignment PIN_B10 -to ADC_SADDR
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR
-#set_location_assignment PIN_B14 -to ADC_SCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
-#set_location_assignment PIN_A9 -to ADC_SDAT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT
-
-#============================================================
-# 2x13 GPIO Header
-#============================================================
-#set_location_assignment PIN_A14 -to GPIO_2[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0]
-#set_location_assignment PIN_B16 -to GPIO_2[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1]
-#set_location_assignment PIN_C14 -to GPIO_2[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2]
-#set_location_assignment PIN_C16 -to GPIO_2[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3]
-#set_location_assignment PIN_C15 -to GPIO_2[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4]
-#set_location_assignment PIN_D16 -to GPIO_2[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5]
-#set_location_assignment PIN_D15 -to GPIO_2[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6]
-#set_location_assignment PIN_D14 -to GPIO_2[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7]
-#set_location_assignment PIN_F15 -to GPIO_2[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8]
-#set_location_assignment PIN_F16 -to GPIO_2[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9]
-#set_location_assignment PIN_F14 -to GPIO_2[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10]
-#set_location_assignment PIN_G16 -to GPIO_2[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11]
-#set_location_assignment PIN_G15 -to GPIO_2[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12]
-#set_location_assignment PIN_E15 -to GPIO_2_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0]
-#set_location_assignment PIN_E16 -to GPIO_2_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1]
-#set_location_assignment PIN_M16 -to GPIO_2_IN[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2]
-
-#============================================================
-# GPIO_0, GPIO_0 connect to GPIO Default
-#============================================================
-#set_location_assignment PIN_A8 -to GPIO_0_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0]
-#set_location_assignment PIN_D3 -to GPIO_0[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
-#set_location_assignment PIN_B8 -to GPIO_0_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1]
-#set_location_assignment PIN_C3 -to GPIO_0[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
-#set_location_assignment PIN_A2 -to GPIO_0[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
-#set_location_assignment PIN_A3 -to GPIO_0[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
-#set_location_assignment PIN_B3 -to GPIO_0[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
-#set_location_assignment PIN_B4 -to GPIO_0[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
-#set_location_assignment PIN_A4 -to GPIO_0[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
-#set_location_assignment PIN_B5 -to GPIO_0[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
-#set_location_assignment PIN_A5 -to GPIO_0[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
-#set_location_assignment PIN_D5 -to GPIO_0[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
-#set_location_assignment PIN_B6 -to GPIO_0[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
-#set_location_assignment PIN_A6 -to GPIO_0[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
-#set_location_assignment PIN_B7 -to GPIO_0[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
-#set_location_assignment PIN_D6 -to GPIO_0[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
-#set_location_assignment PIN_A7 -to GPIO_0[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
-#set_location_assignment PIN_C6 -to GPIO_0[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
-#set_location_assignment PIN_C8 -to GPIO_0[16]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
-#set_location_assignment PIN_E6 -to GPIO_0[17]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
-#set_location_assignment PIN_E7 -to GPIO_0[18]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
-#set_location_assignment PIN_D8 -to GPIO_0[19]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
-#set_location_assignment PIN_E8 -to GPIO_0[20]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
-#set_location_assignment PIN_F8 -to GPIO_0[21]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
-#set_location_assignment PIN_F9 -to GPIO_0[22]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
-#set_location_assignment PIN_E9 -to GPIO_0[23]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
-#set_location_assignment PIN_C9 -to GPIO_0[24]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
-#set_location_assignment PIN_D9 -to GPIO_0[25]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
-#set_location_assignment PIN_E11 -to GPIO_0[26]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
-#set_location_assignment PIN_E10 -to GPIO_0[27]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
-#set_location_assignment PIN_C11 -to GPIO_0[28]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
-#set_location_assignment PIN_B11 -to GPIO_0[29]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
-#set_location_assignment PIN_A12 -to GPIO_0[30]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
-#set_location_assignment PIN_D11 -to GPIO_0[31]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
-#set_location_assignment PIN_D12 -to GPIO_0[32]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
-#set_location_assignment PIN_B12 -to GPIO_0[33]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
-
-#============================================================
-# GPIO_1, GPIO_1 connect to GPIO Default
-#============================================================
-#set_location_assignment PIN_T9 -to GPIO_1_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0]
-#set_location_assignment PIN_F13 -to GPIO_1[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
-#set_location_assignment PIN_R9 -to GPIO_1_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1]
-#set_location_assignment PIN_T15 -to GPIO_1[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
-#set_location_assignment PIN_T14 -to GPIO_1[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
-#set_location_assignment PIN_T13 -to GPIO_1[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
-#set_location_assignment PIN_R13 -to GPIO_1[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
-#set_location_assignment PIN_T12 -to GPIO_1[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
-#set_location_assignment PIN_R12 -to GPIO_1[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
-#set_location_assignment PIN_T11 -to GPIO_1[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
-#set_location_assignment PIN_T10 -to GPIO_1[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
-#set_location_assignment PIN_R11 -to GPIO_1[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
-#set_location_assignment PIN_P11 -to GPIO_1[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
-#set_location_assignment PIN_R10 -to GPIO_1[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
-#set_location_assignment PIN_N12 -to GPIO_1[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
-#set_location_assignment PIN_P9 -to GPIO_1[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
-#set_location_assignment PIN_N9 -to GPIO_1[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
-#set_location_assignment PIN_N11 -to GPIO_1[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
-#set_location_assignment PIN_L16 -to GPIO_1[16]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
-#set_location_assignment PIN_K16 -to GPIO_1[17]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
-#set_location_assignment PIN_R16 -to GPIO_1[18]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
-#set_location_assignment PIN_L15 -to GPIO_1[19]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
-#set_location_assignment PIN_P15 -to GPIO_1[20]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
-#set_location_assignment PIN_P16 -to GPIO_1[21]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
-#set_location_assignment PIN_R14 -to GPIO_1[22]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
-#set_location_assignment PIN_N16 -to GPIO_1[23]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
-#set_location_assignment PIN_N15 -to GPIO_1[24]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
-#set_location_assignment PIN_P14 -to GPIO_1[25]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
-#set_location_assignment PIN_L14 -to GPIO_1[26]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
-#set_location_assignment PIN_N14 -to GPIO_1[27]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
-#set_location_assignment PIN_M10 -to GPIO_1[28]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
-#set_location_assignment PIN_L13 -to GPIO_1[29]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
-#set_location_assignment PIN_J16 -to GPIO_1[30]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
-#set_location_assignment PIN_K15 -to GPIO_1[31]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
-#set_location_assignment PIN_J13 -to GPIO_1[32]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
-#set_location_assignment PIN_J14 -to GPIO_1[33]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
-
-#============================================================
-# End of pin assignments by Terasic System Builder
-#============================================================
-
-
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[*]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQM[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N
-
-set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
-
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-
-
-set_global_assignment -name VHDL_FILE ../DE10_nano_zpu_Toplevel.vhd
-set_global_assignment -name QIP_FILE Clock_50to100.qip
-#set_global_assignment -name SDC_FILE DE10_nano_zpu_constraints.sdc
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
-#set_global_assignment -name VHDL_FILE ../cpu/zpu_flex_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
-#set_global_assignment -name VHDL_FILE ../cpu/zpu_small_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_cacheL2.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
-#set_global_assignment -name VHDL_FILE ../cpu/zpu_medium_pkg.vhd
-#set_global_assignment -name VHDL_FILE ../trace/trace.vhd
-#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
-set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_brgen.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_mv_filter.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_rx.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_tx.vhd
-set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd
-set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/simple_uart.vhd
-#set_global_assignment -name VHDL_FILE ../devices/fifo/fifo.vhd
-set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd
-set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd
-set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd
-set_global_assignment -name VHDL_FILE ../devices/ioctl/ioctl.vhd
-set_global_assignment -name VHDL_FILE ../devices/RAM/dualport_ram.vhd
-set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd
-#set_global_assignment -name VERILOG_FILE ../cpu/qdiv.v
-#set_global_assignment -name VHDL_FILE ../devices/Peripherals/simple_uart.vhd
-#set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM.vhd
-#set_global_assignment -name VHDL_FILE ../devices/RAM/DualPortRAM.vhd
-#set_global_assignment -name VERILOG_FILE ../devices/RAM/TwoWayCache.v
-#set_global_assignment -name VHDL_FILE ../devices/RAM/sdram_cached.vhd
-#set_global_assignment -name VHDL_FILE ../Toplevel_Config.vhd
-#set_global_assignment -name VHDL_FILE ../DMACache_config.vhd
-#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_master.vhd
-#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_dither.vhd
-#set_global_assignment -name VHDL_FILE ../devices/Video/vga_controller.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache_pkg.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/FIFO_Counter.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACacheRAM.vhd
-
-
-
-
-
-
-
-
-
-
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/zpu/build/DE10_nano_zpu.qsf.2406 b/zpu/build/DE10_nano_zpu.qsf.2406
deleted file mode 100644
index 7781cd3..0000000
--- a/zpu/build/DE10_nano_zpu.qsf.2406
+++ /dev/null
@@ -1,486 +0,0 @@
-#============================================================
-# Build by Terasic System Builder
-#============================================================
-
-set_global_assignment -name DEVICE 5CSEBA6U23I7
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name TOP_LEVEL_ENTITY DE10_nano_zpu
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.1
-set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:22:00 FEBRUARY 21,2011"
-set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
-set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
-set_global_assignment -name GENERATE_RBF_FILE ON
-
-
-#set_location_assignment PIN_AA13 -to UART_TX_0
-#set_location_assignment PIN_AA11 -to UART_RX_0
-#set_location_assignment PIN_Y11 -to UART_TX_1
-#set_location_assignment PIN_AA26 -to UART_RX_1
-set_location_assignment PIN_Y15 -to UART_TX_0
-set_location_assignment PIN_AA15 -to UART_RX_0
-set_location_assignment PIN_AG28 -to UART_TX_1
-set_location_assignment PIN_AG26 -to UART_RX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-
-#============================================================
-# CLOCK
-#============================================================
-#set_location_assignment PIN_R8 -to CLOCK_50
-set_location_assignment PIN_V11 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# LED
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
-set_location_assignment PIN_W15 -to LED[0]
-set_location_assignment PIN_AA24 -to LED[1]
-set_location_assignment PIN_V16 -to LED[2]
-set_location_assignment PIN_V15 -to LED[3]
-set_location_assignment PIN_AF26 -to LED[4]
-set_location_assignment PIN_AE26 -to LED[5]
-set_location_assignment PIN_Y16 -to LED[6]
-set_location_assignment PIN_AA23 -to LED[7]
-
-#============================================================
-# KEY
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
-set_location_assignment PIN_AH17 -to KEY[0]
-set_location_assignment PIN_AH16 -to KEY[1]
-
-#============================================================
-# SW
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
-set_location_assignment PIN_Y24 -to SW[0]
-set_location_assignment PIN_W24 -to SW[1]
-set_location_assignment PIN_W21 -to SW[2]
-set_location_assignment PIN_W20 -to SW[3]
-
-#============================================================
-# SDRAM
-#============================================================
-#set_location_assignment PIN_M7 -to DRAM_BA[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
-#set_location_assignment PIN_M6 -to DRAM_BA[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
-#set_location_assignment PIN_R6 -to DRAM_DQM[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
-#set_location_assignment PIN_T5 -to DRAM_DQM[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
-#set_location_assignment PIN_L2 -to DRAM_RAS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
-#set_location_assignment PIN_L1 -to DRAM_CAS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
-#set_location_assignment PIN_L7 -to DRAM_CKE
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
-#set_location_assignment PIN_R4 -to DRAM_CLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
-#set_location_assignment PIN_C2 -to DRAM_WE_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
-#set_location_assignment PIN_P6 -to DRAM_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
-#set_location_assignment PIN_G2 -to DRAM_DQ[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
-#set_location_assignment PIN_G1 -to DRAM_DQ[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
-#set_location_assignment PIN_L8 -to DRAM_DQ[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
-#set_location_assignment PIN_K5 -to DRAM_DQ[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
-#set_location_assignment PIN_K2 -to DRAM_DQ[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
-#set_location_assignment PIN_J2 -to DRAM_DQ[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
-#set_location_assignment PIN_J1 -to DRAM_DQ[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
-#set_location_assignment PIN_R7 -to DRAM_DQ[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
-#set_location_assignment PIN_T4 -to DRAM_DQ[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
-#set_location_assignment PIN_T2 -to DRAM_DQ[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
-#set_location_assignment PIN_T3 -to DRAM_DQ[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
-#set_location_assignment PIN_R3 -to DRAM_DQ[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
-#set_location_assignment PIN_R5 -to DRAM_DQ[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
-#set_location_assignment PIN_P3 -to DRAM_DQ[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
-#set_location_assignment PIN_N3 -to DRAM_DQ[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
-#set_location_assignment PIN_K1 -to DRAM_DQ[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
-#set_location_assignment PIN_P2 -to DRAM_ADDR[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
-#set_location_assignment PIN_N5 -to DRAM_ADDR[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
-#set_location_assignment PIN_N6 -to DRAM_ADDR[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
-#set_location_assignment PIN_M8 -to DRAM_ADDR[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
-#set_location_assignment PIN_P8 -to DRAM_ADDR[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
-#set_location_assignment PIN_T7 -to DRAM_ADDR[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
-#set_location_assignment PIN_N8 -to DRAM_ADDR[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
-#set_location_assignment PIN_T6 -to DRAM_ADDR[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
-#set_location_assignment PIN_R1 -to DRAM_ADDR[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
-#set_location_assignment PIN_P1 -to DRAM_ADDR[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
-#set_location_assignment PIN_N2 -to DRAM_ADDR[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
-#set_location_assignment PIN_N1 -to DRAM_ADDR[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
-#set_location_assignment PIN_L4 -to DRAM_ADDR[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
-
-#============================================================
-# EPCS
-#============================================================
-#set_location_assignment PIN_H2 -to EPCS_DATA0
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DATA0
-#set_location_assignment PIN_H1 -to EPCS_DCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_DCLK
-#set_location_assignment PIN_D2 -to EPCS_NCSO
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_NCSO
-#set_location_assignment PIN_C1 -to EPCS_ASDO
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EPCS_ASDO
-
-#============================================================
-# Accelerometer and EEPROM
-#============================================================
-#set_location_assignment PIN_F2 -to I2C_SCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK
-#set_location_assignment PIN_F1 -to I2C_SDAT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT
-#set_location_assignment PIN_G5 -to G_SENSOR_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_CS_N
-#set_location_assignment PIN_M2 -to G_SENSOR_INT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to G_SENSOR_INT
-
-#============================================================
-# ADC
-#============================================================
-#set_location_assignment PIN_A10 -to ADC_CS_N
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N
-#set_location_assignment PIN_B10 -to ADC_SADDR
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SADDR
-#set_location_assignment PIN_B14 -to ADC_SCLK
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK
-#set_location_assignment PIN_A9 -to ADC_SDAT
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDAT
-
-#============================================================
-# 2x13 GPIO Header
-#============================================================
-#set_location_assignment PIN_A14 -to GPIO_2[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[0]
-#set_location_assignment PIN_B16 -to GPIO_2[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[1]
-#set_location_assignment PIN_C14 -to GPIO_2[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[2]
-#set_location_assignment PIN_C16 -to GPIO_2[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[3]
-#set_location_assignment PIN_C15 -to GPIO_2[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[4]
-#set_location_assignment PIN_D16 -to GPIO_2[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[5]
-#set_location_assignment PIN_D15 -to GPIO_2[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[6]
-#set_location_assignment PIN_D14 -to GPIO_2[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[7]
-#set_location_assignment PIN_F15 -to GPIO_2[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[8]
-#set_location_assignment PIN_F16 -to GPIO_2[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[9]
-#set_location_assignment PIN_F14 -to GPIO_2[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[10]
-#set_location_assignment PIN_G16 -to GPIO_2[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[11]
-#set_location_assignment PIN_G15 -to GPIO_2[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2[12]
-#set_location_assignment PIN_E15 -to GPIO_2_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[0]
-#set_location_assignment PIN_E16 -to GPIO_2_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[1]
-#set_location_assignment PIN_M16 -to GPIO_2_IN[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_2_IN[2]
-
-#============================================================
-# GPIO_0, GPIO_0 connect to GPIO Default
-#============================================================
-#set_location_assignment PIN_A8 -to GPIO_0_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[0]
-#set_location_assignment PIN_D3 -to GPIO_0[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0]
-#set_location_assignment PIN_B8 -to GPIO_0_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0_IN[1]
-#set_location_assignment PIN_C3 -to GPIO_0[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1]
-#set_location_assignment PIN_A2 -to GPIO_0[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2]
-#set_location_assignment PIN_A3 -to GPIO_0[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3]
-#set_location_assignment PIN_B3 -to GPIO_0[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4]
-#set_location_assignment PIN_B4 -to GPIO_0[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5]
-#set_location_assignment PIN_A4 -to GPIO_0[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6]
-#set_location_assignment PIN_B5 -to GPIO_0[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7]
-#set_location_assignment PIN_A5 -to GPIO_0[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8]
-#set_location_assignment PIN_D5 -to GPIO_0[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9]
-#set_location_assignment PIN_B6 -to GPIO_0[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10]
-#set_location_assignment PIN_A6 -to GPIO_0[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11]
-#set_location_assignment PIN_B7 -to GPIO_0[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12]
-#set_location_assignment PIN_D6 -to GPIO_0[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13]
-#set_location_assignment PIN_A7 -to GPIO_0[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14]
-#set_location_assignment PIN_C6 -to GPIO_0[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15]
-#set_location_assignment PIN_C8 -to GPIO_0[16]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16]
-#set_location_assignment PIN_E6 -to GPIO_0[17]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17]
-#set_location_assignment PIN_E7 -to GPIO_0[18]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18]
-#set_location_assignment PIN_D8 -to GPIO_0[19]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19]
-#set_location_assignment PIN_E8 -to GPIO_0[20]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20]
-#set_location_assignment PIN_F8 -to GPIO_0[21]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21]
-#set_location_assignment PIN_F9 -to GPIO_0[22]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22]
-#set_location_assignment PIN_E9 -to GPIO_0[23]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23]
-#set_location_assignment PIN_C9 -to GPIO_0[24]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24]
-#set_location_assignment PIN_D9 -to GPIO_0[25]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25]
-#set_location_assignment PIN_E11 -to GPIO_0[26]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26]
-#set_location_assignment PIN_E10 -to GPIO_0[27]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27]
-#set_location_assignment PIN_C11 -to GPIO_0[28]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28]
-#set_location_assignment PIN_B11 -to GPIO_0[29]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
-#set_location_assignment PIN_A12 -to GPIO_0[30]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30]
-#set_location_assignment PIN_D11 -to GPIO_0[31]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31]
-#set_location_assignment PIN_D12 -to GPIO_0[32]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32]
-#set_location_assignment PIN_B12 -to GPIO_0[33]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33]
-
-#============================================================
-# GPIO_1, GPIO_1 connect to GPIO Default
-#============================================================
-#set_location_assignment PIN_T9 -to GPIO_1_IN[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[0]
-#set_location_assignment PIN_F13 -to GPIO_1[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0]
-#set_location_assignment PIN_R9 -to GPIO_1_IN[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1_IN[1]
-#set_location_assignment PIN_T15 -to GPIO_1[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1]
-#set_location_assignment PIN_T14 -to GPIO_1[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2]
-#set_location_assignment PIN_T13 -to GPIO_1[3]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3]
-#set_location_assignment PIN_R13 -to GPIO_1[4]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4]
-#set_location_assignment PIN_T12 -to GPIO_1[5]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5]
-#set_location_assignment PIN_R12 -to GPIO_1[6]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6]
-#set_location_assignment PIN_T11 -to GPIO_1[7]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7]
-#set_location_assignment PIN_T10 -to GPIO_1[8]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8]
-#set_location_assignment PIN_R11 -to GPIO_1[9]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9]
-#set_location_assignment PIN_P11 -to GPIO_1[10]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10]
-#set_location_assignment PIN_R10 -to GPIO_1[11]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11]
-#set_location_assignment PIN_N12 -to GPIO_1[12]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12]
-#set_location_assignment PIN_P9 -to GPIO_1[13]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13]
-#set_location_assignment PIN_N9 -to GPIO_1[14]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14]
-#set_location_assignment PIN_N11 -to GPIO_1[15]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15]
-#set_location_assignment PIN_L16 -to GPIO_1[16]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16]
-#set_location_assignment PIN_K16 -to GPIO_1[17]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17]
-#set_location_assignment PIN_R16 -to GPIO_1[18]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18]
-#set_location_assignment PIN_L15 -to GPIO_1[19]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19]
-#set_location_assignment PIN_P15 -to GPIO_1[20]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20]
-#set_location_assignment PIN_P16 -to GPIO_1[21]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21]
-#set_location_assignment PIN_R14 -to GPIO_1[22]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22]
-#set_location_assignment PIN_N16 -to GPIO_1[23]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23]
-#set_location_assignment PIN_N15 -to GPIO_1[24]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24]
-#set_location_assignment PIN_P14 -to GPIO_1[25]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25]
-#set_location_assignment PIN_L14 -to GPIO_1[26]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26]
-#set_location_assignment PIN_N14 -to GPIO_1[27]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27]
-#set_location_assignment PIN_M10 -to GPIO_1[28]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28]
-#set_location_assignment PIN_L13 -to GPIO_1[29]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29]
-#set_location_assignment PIN_J16 -to GPIO_1[30]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30]
-#set_location_assignment PIN_K15 -to GPIO_1[31]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31]
-#set_location_assignment PIN_J13 -to GPIO_1[32]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32]
-#set_location_assignment PIN_J14 -to GPIO_1[33]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33]
-
-#============================================================
-# End of pin assignments by Terasic System Builder
-#============================================================
-
-
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQ[*]
-set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_DQM[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_BA[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_ADDR[*]
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_CAS_N
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_RAS_N
-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_WE_N
-
-set_instance_assignment -name SLEW_RATE 2 -to DRAM_DQ*
-
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-
-
-set_global_assignment -name VHDL_FILE ../DE10_nano_zpu_Toplevel.vhd
-set_global_assignment -name QIP_FILE Clock_50to100.qip
-#set_global_assignment -name SDC_FILE DE10_nano_zpu_constraints.sdc
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
-#set_global_assignment -name VHDL_FILE ../cpu/zpu_flex_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
-#set_global_assignment -name VHDL_FILE ../cpu/zpu_small_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_cacheL2.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
-#set_global_assignment -name VHDL_FILE ../cpu/zpu_medium_pkg.vhd
-#set_global_assignment -name VHDL_FILE ../trace/trace.vhd
-#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
-set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_brgen.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_mv_filter.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_rx.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_tx.vhd
-set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd
-set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/simple_uart.vhd
-#set_global_assignment -name VHDL_FILE ../devices/fifo/fifo.vhd
-set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd
-set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd
-set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd
-set_global_assignment -name VHDL_FILE ../devices/ioctl/ioctl.vhd
-set_global_assignment -name VHDL_FILE ../devices/RAM/dualport_ram.vhd
-set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd
-#set_global_assignment -name VERILOG_FILE ../cpu/qdiv.v
-#set_global_assignment -name VHDL_FILE ../devices/Peripherals/simple_uart.vhd
-#set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM.vhd
-#set_global_assignment -name VHDL_FILE ../devices/RAM/DualPortRAM.vhd
-#set_global_assignment -name VERILOG_FILE ../devices/RAM/TwoWayCache.v
-#set_global_assignment -name VHDL_FILE ../devices/RAM/sdram_cached.vhd
-#set_global_assignment -name VHDL_FILE ../Toplevel_Config.vhd
-#set_global_assignment -name VHDL_FILE ../DMACache_config.vhd
-#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_master.vhd
-#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_dither.vhd
-#set_global_assignment -name VHDL_FILE ../devices/Video/vga_controller.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache_pkg.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/FIFO_Counter.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACacheRAM.vhd
-
-
-
-
-
-
-
-
-
-
-
-
-
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/zpu/build/DE10_nano_zpu_Toplevel.vhd b/zpu/build/DE10_nano_zpu_Toplevel.vhd
deleted file mode 100644
index 74febe2..0000000
--- a/zpu/build/DE10_nano_zpu_Toplevel.vhd
+++ /dev/null
@@ -1,174 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.zpu_soc_pkg.all;
-
-entity DE10_nano_zpu is
- port (
- -- Clock
- CLOCK_50 : in std_logic;
- -- LED
- LED : out std_logic_vector(7 downto 0);
- -- Debounced keys
- KEY : in std_logic_vector(1 downto 0);
- -- DIP switches
- SW : in std_logic_vector(3 downto 0);
-
- TDI : out std_logic;
- TCK : out std_logic;
- TCS : out std_logic;
- TDO : in std_logic;
- -- I2C_SDAT : inout std_logic;
- -- I2C_SCLK : out std_logic;
- -- GPIO_0 : inout std_logic_vector(33 downto 0);
- -- GPIO_1 : inout std_logic_vector(33 downto 0);
-
- -- SD Card 1
- SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
-
- -- UART Serial channels.
- UART_RX_0 : in std_logic;
- UART_TX_0 : out std_logic;
- UART_RX_1 : in std_logic;
- UART_TX_1 : out std_logic
-
--- SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
--- SDRAM_CKE : out std_logic; -- clock enable.
--- SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
--- SDRAM_ADDR : out std_logic_vector(12 downto 0); -- 13 bit multiplexed address bus
--- SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
--- SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
--- SDRAM_CS : out std_logic; -- a single chip select
--- SDRAM_WE : out std_logic; -- write enable
--- SDRAM_RAS : out std_logic; -- row address select
--- SDRAM_CAS : out std_logic -- columns address select
- );
-END entity;
-
-architecture rtl of DE10_nano_zpu is
-
- signal reset : std_logic;
- signal sysclk : std_logic;
- signal memclk : std_logic;
- signal pll_locked : std_logic;
-
- --signal ps2m_clk_in : std_logic;
- --signal ps2m_clk_out : std_logic;
- --signal ps2m_dat_in : std_logic;
- --signal ps2m_dat_out : std_logic;
-
- --signal ps2k_clk_in : std_logic;
- --signal ps2k_clk_out : std_logic;
- --signal ps2k_dat_in : std_logic;
- --signal ps2k_dat_out : std_logic;
-
- --alias PS2_MDAT : std_logic is GPIO_1(19);
- --alias PS2_MCLK : std_logic is GPIO_1(18);
-
-begin
-
---I2C_SDAT <= 'Z';
---GPIO_0(33 downto 2) <= (others => 'Z');
---GPIO_1 <= (others => 'Z');
---LED <= "101010" & reset & UART_RX_0;
-LED <= "00000000";
-
-mypll : entity work.Clock_50to100
-port map
-(
- inclk0 => CLOCK_50,
- c0 => sysclk,
- c1 => memclk,
- locked => pll_locked
-);
-
-reset<=(not SW(0) xor KEY(0)) and pll_locked;
-
-myVirtualToplevel : entity work.zpu_soc
-generic map
-(
- SYSCLK_FREQUENCY => SYSCLK_DE10_FREQ
-)
-port map
-(
- SYSCLK => sysclk,
- MEMCLK => memclk,
- RESET_IN => reset,
-
- -- RS232
- UART_RX_0 => UART_RX_0,
- UART_TX_0 => UART_TX_0,
- UART_RX_1 => UART_RX_1,
- UART_TX_1 => UART_TX_1,
-
- -- SPI signals
- SPI_MISO => TDO, -- Allow the SPI interface not to be plumbed in.
- SPI_MOSI => TDI,
- SPI_CLK => TCK,
- SPI_CS => TCS,
-
- -- SD Card (SPI) signals
- SDCARD_MISO => SDCARD_MISO,
- SDCARD_MOSI => SDCARD_MOSI,
- SDCARD_CLK => SDCARD_CLK,
- SDCARD_CS => SDCARD_CS,
-
- -- PS/2 signals
- PS2K_CLK_IN => '1',
- PS2K_DAT_IN => '1',
- PS2K_CLK_OUT => open,
- PS2K_DAT_OUT => open,
- PS2M_CLK_IN => '1',
- PS2M_DAT_IN => '1',
- PS2M_CLK_OUT => open,
- PS2M_DAT_OUT => open,
-
- -- I²C signals
- I2C_SCL_IO => open,
- I2C_SDA_IO => open,
-
- -- IOCTL Bus --
- IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
- IOCTL_UPLOAD => open, -- Uploading from FPGA.
- IOCTL_CLK => open, -- I/O Clock.
- IOCTL_WR => open, -- Write Enable to FPGA.
- IOCTL_RD => open, -- Read Enable from FPGA.
- IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
- IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
- IOCTL_ADDR => open, -- Address in FPGA to write into.
- IOCTL_DOUT => open, -- Data to be written into FPGA.
- IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
-
- -- SDRAM signals
- SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
- SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
- SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
- SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
- SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
- SDRAM_BA => open, --SDRAM_BA, -- two banks
- SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
- SDRAM_WE_n => open, --SDRAM_WE, -- write enable
- SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
- SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
- SDRAM_READY => open
-
- -- DDR2 DRAM - doesnt exist on the QMV.
- --DDR2_ADDR => open, -- 14 bit multiplexed address bus
- --DDR2_DQ => open, -- 64 bit bidirectional data bus
- --DDR2_DQS => open, -- 8 bit bidirectional data bus
- --DDR2_DQM => open, -- eight byte masks
- --DDR2_ODT => open, -- 14 bit multiplexed address bus
- --DDR2_BA => open, -- 8 banks
- --DDR2_CS => open, -- 2 chip selects.
- --DDR2_WE => open, -- write enable
- --DDR2_RAS => open, -- row address select
- --DDR2_CAS => open, -- columns address select
- --DDR2_CKE => open, -- 2 clock enable.
- --DDR2_CLK => open -- 2 clocks.
-);
-
-
-end architecture;
diff --git a/zpu/build/DE10_nano_zpu_constraints.sdc b/zpu/build/DE10_nano_zpu_constraints.sdc
deleted file mode 100644
index 3c7f513..0000000
--- a/zpu/build/DE10_nano_zpu_constraints.sdc
+++ /dev/null
@@ -1,154 +0,0 @@
-## Generated SDC file "hello_led.out.sdc"
-
-## Copyright (C) 1991-2011 Altera Corporation
-## Your use of Altera Corporation's design tools, logic functions
-## and other software and tools, and its AMPP partner logic
-## functions, and any output files from any of the foregoing
-## (including device programming or simulation files), and any
-## associated documentation or information are expressly subject
-## to the terms and conditions of the Altera Program License
-## Subscription Agreement, Altera MegaCore Function License
-## Agreement, or other applicable license agreement, including,
-## without limitation, that your use is for the sole purpose of
-## programming logic devices manufactured by Altera and sold by
-## Altera or its authorized distributors. Please refer to the
-## applicable agreement for further details.
-
-
-## VENDOR "Altera"
-## PROGRAM "Quartus II"
-## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition"
-
-## DATE "Fri Jul 06 23:05:47 2012"
-
-##
-## DEVICE "EP3C25Q240C8"
-##
-
-
-#**************************************************************
-# Time Information
-#**************************************************************
-
-set_time_format -unit ns -decimal_places 3
-
-
-#**************************************************************
-# Create Clock
-#**************************************************************
-
-create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}]
-
-
-#**************************************************************
-# Create Generated Clock
-#**************************************************************
-
-create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_50}] -duty_cycle 50.000 -multiply_by 2 -master_clock {clk_50} [get_nets {mypll|altpll_component|auto_generated|wire_generic_pll1_outclk}]
-#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_50}] -duty_cycle 50.000 -phase 0 -multiply_by 4 -master_clock {clk_50} [get_nets {mypll|altpll_component|auto_generated|wire_generic_pll2_outclk}]
-
-
-#**************************************************************
-# Set Clock Latency
-#**************************************************************
-
-
-#**************************************************************
-# Set Clock Uncertainty
-#**************************************************************
-
-#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080
-#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060
-#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080
-#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060
-#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080
-#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060
-#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080
-#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -setup 0.080
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -hold 0.060
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -setup 0.080
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -hold 0.060
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -setup 0.080
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] -hold 0.060
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -setup 0.080
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] -hold 0.060
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -setup 0.080
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] -hold 0.060
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -setup 0.080
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] -hold 0.060
-derive_clock_uncertainty
-
-
-#**************************************************************
-# Set Input Delay
-#**************************************************************
-
-
-# Delays for async signals - not necessary, but might as well avoid
-# having unconstrained ports in the design
-#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
-#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
-
-#**************************************************************
-# Set Output Delay
-#**************************************************************
-
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[0]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[1]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[2]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[3]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[4]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[5]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[6]}]
-#set_output_delay -add_delay -clock [get_clocks {sysclk}] 0.500 [get_ports {LED[7]}]
-
-
-#**************************************************************
-# Set Clock Groups
-#**************************************************************
-
-
-
-#**************************************************************
-# Set False Path
-#**************************************************************
-
-set_false_path -from [get_keepers {KEY*}]
-set_false_path -from [get_keepers {SW*}]
-#set_false_path -from [get_cells {myVirtualToplevel|RESET_n}]
-
-
-#**************************************************************
-# Set Multicycle Path
-#**************************************************************
-
-#set_multicycle_path -setup -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 1
-#set_multicycle_path -hold -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 0
-
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 2
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheFetchIdx[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|cacheL1[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -setup -start 1
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxNOS[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|TOS.word[*]}] -hold -start 0
-
-#**************************************************************
-# Set Maximum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Minimum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Input Transition
-#**************************************************************
diff --git a/zpu/build/E115_zpu.cdf b/zpu/build/E115_zpu.cdf
deleted file mode 100644
index 9d4404f..0000000
--- a/zpu/build/E115_zpu.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition */
-JedecChain;
- FileRevision(JESD32A);
- DefaultMfr(6E);
-
- P ActionCode(Cfg)
- Device PartName(EP4CE115F23) Path("/srv/dvlp/Projects/dev/github/zpu/build/") File("E115_zpu.sof") MfrSpec(OpMask(1));
-
-ChainEnd;
-
-AlteraBegin;
- ChainType(JTAG);
-AlteraEnd;
diff --git a/zpu/build/E115_zpu.qpf b/zpu/build/E115_zpu.qpf
deleted file mode 100644
index f857ebe..0000000
--- a/zpu/build/E115_zpu.qpf
+++ /dev/null
@@ -1,23 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-
-QUARTUS_VERSION = "5.0"
-DATE = "23:35:58 September 01, 2005"
-
-
-# Revisions
-
-PROJECT_REVISION = "E115_zpu"
diff --git a/zpu/build/E115_zpu.qsf b/zpu/build/E115_zpu.qsf
deleted file mode 100644
index dbdc243..0000000
--- a/zpu/build/E115_zpu.qsf
+++ /dev/null
@@ -1,302 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-# ledwater_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-# assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005"
-set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
-set_global_assignment -name CDF_FILE E115.cdf
-
-# Pin & Location Assignments
-# ==========================
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name TOP_LEVEL_ENTITY E115_zpu
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP4CE115F23I7
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-
-# Assembler Assignments
-# =====================
-
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-
-set_global_assignment -name ENABLE_SIGNALTAP ON
-set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-
-
-
-
-#============================================================
-# UART
-#============================================================
-set_location_assignment PIN_A7 -to UART_RX_0
-set_location_assignment PIN_B7 -to UART_TX_0
-set_location_assignment PIN_C6 -to UART_RX_1
-set_location_assignment PIN_D7 -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-
-#============================================================
-# SD CARD
-#============================================================
-set_location_assignment PIN_C8 -to SDCARD_MISO[0]
-set_location_assignment PIN_C7 -to SDCARD_MOSI[0]
-set_location_assignment PIN_B8 -to SDCARD_CLK[0]
-set_location_assignment PIN_A8 -to SDCARD_CS[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
-
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_AB11 -to CLOCK_25
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_25
-#set_location_assignment PIN_AB11 -to clk_25M
-
-#============================================================
-# LED
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
-set_location_assignment PIN_A5 -to LED[0]
-set_location_assignment PIN_B5 -to LED[1]
-set_location_assignment PIN_C4 -to LED[2]
-set_location_assignment PIN_C3 -to LED[3]
-
-#============================================================
-# DDR2 DRAM
-#============================================================
-#set_location_assignment PIN_AA20 -to DDR2_ADDR[13]
-#set_location_assignment PIN_V8 -to DDR2_ADDR[12]
-#set_location_assignment PIN_AB6 -to DDR2_ADDR[11]
-#set_location_assignment PIN_K22 -to DDR2_ADDR[10]
-#set_location_assignment PIN_W10 -to DDR2_ADDR[9]
-#set_location_assignment PIN_T19 -to DDR2_ADDR[8]
-#set_location_assignment PIN_Y14 -to DDR2_ADDR[7]
-#set_location_assignment PIN_W14 -to DDR2_ADDR[6]
-#set_location_assignment PIN_T20 -to DDR2_ADDR[5]
-#set_location_assignment PIN_Y15 -to DDR2_ADDR[4]
-#set_location_assignment PIN_L22 -to DDR2_ADDR[3]
-#set_location_assignment PIN_Y17 -to DDR2_ADDR[2]
-#set_location_assignment PIN_L21 -to DDR2_ADDR[1]
-#set_location_assignment PIN_AB10 -to DDR2_ADDR[0]
-#set_location_assignment PIN_Y6 -to DDR2_BA[2]
-#set_location_assignment PIN_AB17 -to DDR2_BA[1]
-#set_location_assignment PIN_K21 -to DDR2_BA[0]
-#set_location_assignment PIN_J18 -to DDR2_CAS
-#set_location_assignment PIN_Y4 -to DDR2_CKE[0]
-#set_location_assignment PIN_AB5 -to DDR2_CKE[1]
-#set_location_assignment PIN_AA19 -to DDR2_CS[0]
-#set_location_assignment PIN_E21 -to DDR2_CS[1]
-#
-#set_location_assignment PIN_F20 -to DDR2_DM[7]
-#set_location_assignment PIN_F22 -to DDR2_DM[6]
-#set_location_assignment PIN_P22 -to DDR2_DM[5]
-#set_location_assignment PIN_V22 -to DDR2_DM[4]
-#set_location_assignment PIN_W15 -to DDR2_DM[3]
-#set_location_assignment PIN_AA14 -to DDR2_DM[2]
-#set_location_assignment PIN_AA8 -to DDR2_DM[1]
-#set_location_assignment PIN_AA5 -to DDR2_DM[0]
-#
-#set_location_assignment PIN_B21 -to DDR2_DQ[63]
-#set_location_assignment PIN_B22 -to DDR2_DQ[62]
-#set_location_assignment PIN_C21 -to DDR2_DQ[61]
-#set_location_assignment PIN_C22 -to DDR2_DQ[60]
-#set_location_assignment PIN_D22 -to DDR2_DQ[59]
-#set_location_assignment PIN_F19 -to DDR2_DQ[58]
-#set_location_assignment PIN_F17 -to DDR2_DQ[57]
-#set_location_assignment PIN_G18 -to DDR2_DQ[56]
-#set_location_assignment PIN_E22 -to DDR2_DQ[55]
-#set_location_assignment PIN_F21 -to DDR2_DQ[54]
-#set_location_assignment PIN_H21 -to DDR2_DQ[53]
-#set_location_assignment PIN_H22 -to DDR2_DQ[52]
-#set_location_assignment PIN_H19 -to DDR2_DQ[51]
-#set_location_assignment PIN_H20 -to DDR2_DQ[50]
-#set_location_assignment PIN_K18 -to DDR2_DQ[49]
-#set_location_assignment PIN_J21 -to DDR2_DQ[48]
-#set_location_assignment PIN_M22 -to DDR2_DQ[47]
-#set_location_assignment PIN_M21 -to DDR2_DQ[46]
-#set_location_assignment PIN_R22 -to DDR2_DQ[45]
-#set_location_assignment PIN_R21 -to DDR2_DQ[44]
-#set_location_assignment PIN_M20 -to DDR2_DQ[43]
-#set_location_assignment PIN_N20 -to DDR2_DQ[42]
-#set_location_assignment PIN_P21 -to DDR2_DQ[41]
-#set_location_assignment PIN_R19 -to DDR2_DQ[40]
-#set_location_assignment PIN_U22 -to DDR2_DQ[39]
-#set_location_assignment PIN_U21 -to DDR2_DQ[38]
-#set_location_assignment PIN_V21 -to DDR2_DQ[37]
-#set_location_assignment PIN_W22 -to DDR2_DQ[36]
-#set_location_assignment PIN_R20 -to DDR2_DQ[35]
-#set_location_assignment PIN_U20 -to DDR2_DQ[34]
-#set_location_assignment PIN_Y22 -to DDR2_DQ[33]
-#set_location_assignment PIN_AA21 -to DDR2_DQ[32]
-#set_location_assignment PIN_AB20 -to DDR2_DQ[31]
-#set_location_assignment PIN_AB18 -to DDR2_DQ[30]
-#set_location_assignment PIN_AA16 -to DDR2_DQ[29]
-#set_location_assignment PIN_AB16 -to DDR2_DQ[28]
-#set_location_assignment PIN_W17 -to DDR2_DQ[27]
-#set_location_assignment PIN_V15 -to DDR2_DQ[26]
-#set_location_assignment PIN_T15 -to DDR2_DQ[25]
-#set_location_assignment PIN_V14 -to DDR2_DQ[24]
-#set_location_assignment PIN_AA15 -to DDR2_DQ[23]
-#set_location_assignment PIN_AB15 -to DDR2_DQ[22]
-#set_location_assignment PIN_AB14 -to DDR2_DQ[21]
-#set_location_assignment PIN_AA13 -to DDR2_DQ[20]
-#set_location_assignment PIN_W13 -to DDR2_DQ[19]
-#set_location_assignment PIN_U12 -to DDR2_DQ[18]
-#set_location_assignment PIN_AB13 -to DDR2_DQ[17]
-#set_location_assignment PIN_AA10 -to DDR2_DQ[16]
-#set_location_assignment PIN_AA9 -to DDR2_DQ[15]
-#set_location_assignment PIN_AB8 -to DDR2_DQ[14]
-#set_location_assignment PIN_AB7 -to DDR2_DQ[13]
-#set_location_assignment PIN_AA7 -to DDR2_DQ[12]
-#set_location_assignment PIN_V11 -to DDR2_DQ[11]
-#set_location_assignment PIN_Y10 -to DDR2_DQ[10]
-#set_location_assignment PIN_U10 -to DDR2_DQ[9]
-#set_location_assignment PIN_Y8 -to DDR2_DQ[8]
-#set_location_assignment PIN_W8 -to DDR2_DQ[7]
-#set_location_assignment PIN_V5 -to DDR2_DQ[6]
-#set_location_assignment PIN_AA4 -to DDR2_DQ[5]
-#set_location_assignment PIN_Y3 -to DDR2_DQ[4]
-#set_location_assignment PIN_U9 -to DDR2_DQ[3]
-#set_location_assignment PIN_W7 -to DDR2_DQ[2]
-#set_location_assignment PIN_Y7 -to DDR2_DQ[1]
-#set_location_assignment PIN_W6 -to DDR2_DQ[0]
-#
-#set_location_assignment PIN_C20 -to DDR2_DQS[7]
-#set_location_assignment PIN_J22 -to DDR2_DQS[6]
-#set_location_assignment PIN_N18 -to DDR2_DQS[5]
-#set_location_assignment PIN_W20 -to DDR2_DQS[4]
-#set_location_assignment PIN_V13 -to DDR2_DQS[3]
-#set_location_assignment PIN_Y13 -to DDR2_DQS[2]
-#set_location_assignment PIN_AB9 -to DDR2_DQS[1]
-#set_location_assignment PIN_V10 -to DDR2_DQS[0]
-#
-#set_location_assignment PIN_AB19 -to DDR2_ODT[0]
-#set_location_assignment PIN_D21 -to DDR2_ODT[1]
-#set_location_assignment PIN_AA17 -to DDR2_RAS
-#set_location_assignment PIN_J20 -to DDR2_WE
-
-#============================================================
-# Modules and Files
-#============================================================
-
-set_global_assignment -name VHDL_FILE ../E115_zpu_Toplevel.vhd
-set_global_assignment -name QIP_FILE Clock_25to100.qip
-set_global_assignment -name SDC_FILE E115_zpu_constraints.sdc
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
-#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
-set_global_assignment -name VHDL_FILE ../devices/WishBone/SRAM/sram.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
-set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-
-
-
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/zpu/build/E115_zpu.qsf.2406 b/zpu/build/E115_zpu.qsf.2406
deleted file mode 100644
index b10429c..0000000
--- a/zpu/build/E115_zpu.qsf.2406
+++ /dev/null
@@ -1,176 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-# ledwater_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-# assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005"
-set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
-#set_global_assignment -name VERILOG_FILE ledwater.v
-set_global_assignment -name CDF_FILE E115.cdf
-
-# Pin & Location Assignments
-# ==========================
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name TOP_LEVEL_ENTITY E115_zpu
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP4CE115F23I7
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-
-# Assembler Assignments
-# =====================
-
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-
-
-#============================================================
-# UART
-#============================================================
-set_location_assignment PIN_A7 -to UART_RX_0
-set_location_assignment PIN_B7 -to UART_TX_0
-set_location_assignment PIN_C6 -to UART_RX_1
-set_location_assignment PIN_D7 -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_AB11 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-#set_location_assignment PIN_AB11 -to clk_25M
-
-#============================================================
-# LED
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
-set_location_assignment PIN_A5 -to LED[0]
-set_location_assignment PIN_B5 -to LED[1]
-set_location_assignment PIN_C4 -to LED[2]
-set_location_assignment PIN_C3 -to LED[3]
-
-#============================================================
-# Modules and Files
-#============================================================
-
-set_global_assignment -name VHDL_FILE ../E115_zpu_Toplevel.vhd
-set_global_assignment -name QIP_FILE Clock_25to100.qip
-set_global_assignment -name SDC_FILE E115_zpu_constraints.sdc
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
-#set_global_assignment -name VHDL_FILE ../cpu/zpu_flex_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
-#set_global_assignment -name VHDL_FILE ../cpu/zpu_small_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
-#set_global_assignment -name VHDL_FILE ../cpu/zpu_medium_pkg.vhd
-#set_global_assignment -name VHDL_FILE ../trace/trace.vhd
-#set_global_assignment -name VHDL_FILE ../trace/txt_util.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
-set_global_assignment -name VHDL_FILE ../devices/RAM/dpram.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_brgen.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_mv_filter.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_rx.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/uart_tx.vhd
-set_global_assignment -name VHDL_FILE ../devices/uart/uart.vhd
-set_global_assignment -name VHDL_FILE ../devices/uart/uart_debug.vhd
-#set_global_assignment -name VHDL_FILE ../devices/uart/simple_uart.vhd
-#set_global_assignment -name VHDL_FILE ../devices/fifo/fifo.vhd
-set_global_assignment -name VHDL_FILE ../devices/intr/interrupt_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/spi/spi.vhd
-set_global_assignment -name VHDL_FILE ../devices/ps2/io_ps2_com.vhd
-set_global_assignment -name VHDL_FILE ../devices/timer/timer_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/BootROM.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_0.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_1.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_2.vhd
-set_global_assignment -name VHDL_FILE ../devices/BootROM/SysROM_3.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_0.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_1.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_2.vhd
-set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM_3.vhd
-set_global_assignment -name VHDL_FILE ../devices/ioctl/ioctl.vhd
-set_global_assignment -name VHDL_FILE ../devices/RAM/dualport_ram.vhd
-set_global_assignment -name VHDL_FILE ../../em/common/config_pkg.vhd
-#set_global_assignment -name VERILOG_FILE ../cpu/qdiv.v
-#set_global_assignment -name VHDL_FILE ../devices/Peripherals/simple_uart.vhd
-#set_global_assignment -name VHDL_FILE ../devices/SysRAM/SysRAM.vhd
-#set_global_assignment -name VHDL_FILE ../devices/RAM/DualPortRAM.vhd
-#set_global_assignment -name VERILOG_FILE ../devices/RAM/TwoWayCache.v
-#set_global_assignment -name VHDL_FILE ../devices/RAM/sdram_cached.vhd
-#set_global_assignment -name VHDL_FILE ../Toplevel_Config.vhd
-#set_global_assignment -name VHDL_FILE ../DMACache_config.vhd
-#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_master.vhd
-#set_global_assignment -name VHDL_FILE ../devices/Video/video_vga_dither.vhd
-#set_global_assignment -name VHDL_FILE ../devices/Video/vga_controller.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACache_pkg.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/FIFO_Counter.vhd
-#set_global_assignment -name VHDL_FILE ../devices/DMA/DMACacheRAM.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
-
-
-
-
-
-
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/zpu/build/E115_zpu_Toplevel.vhd b/zpu/build/E115_zpu_Toplevel.vhd
deleted file mode 100644
index 313885a..0000000
--- a/zpu/build/E115_zpu_Toplevel.vhd
+++ /dev/null
@@ -1,177 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.zpu_soc_pkg.all;
-
-entity E115_zpu is
- port (
- -- Clock
- CLOCK_25 : in std_logic;
- -- LED
- LED : out std_logic_vector(7 downto 0);
- -- Debounced keys
- KEY : in std_logic_vector(1 downto 0);
- -- DIP switches
- SW : in std_logic_vector(3 downto 0);
-
- -- TDI : in std_logic;
- -- TCK : in std_logic;
- -- TCS : in std_logic;
- -- TDO : out std_logic;
- -- I2C_SDAT : inout std_logic;
- -- I2C_SCLK : out std_logic;
- -- GPIO_0 : inout std_logic_vector(33 downto 0);
- -- GPIO_1 : inout std_logic_vector(33 downto 0);
-
- -- SD Card 1
- SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
-
- -- UART Serial channels.
- UART_RX_0 : in std_logic;
- UART_TX_0 : out std_logic;
- UART_RX_1 : in std_logic;
- UART_TX_1 : out std_logic
-
- -- DDR2 DRAM
- --DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus
- --DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus
- --DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus
- --DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks
- --DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus
- --DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks
- --DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects.
- --DDR2_WE : out std_logic; -- write enable
- --DDR2_RAS : out std_logic; -- row address select
- --DDR2_CAS : out std_logic; -- columns address select
- --DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable.
- --DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks.
- );
-END entity;
-
-architecture rtl of E115_zpu is
-
- signal reset : std_logic;
- signal sysclk : std_logic;
- signal memclk : std_logic;
- signal pll_locked : std_logic;
-
- --signal ps2m_clk_in : std_logic;
- --signal ps2m_clk_out : std_logic;
- --signal ps2m_dat_in : std_logic;
- --signal ps2m_dat_out : std_logic;
-
- --signal ps2k_clk_in : std_logic;
- --signal ps2k_clk_out : std_logic;
- --signal ps2k_dat_in : std_logic;
- --signal ps2k_dat_out : std_logic;
-
- --alias PS2_MDAT : std_logic is GPIO_1(19);
- --alias PS2_MCLK : std_logic is GPIO_1(18);
-
-begin
-
---I2C_SDAT <= 'Z';
---GPIO_0(33 downto 2) <= (others => 'Z');
---GPIO_1 <= (others => 'Z');
---LED <= "101010" & reset & UART_RX_0;
-LED <= "00000000";
-
-mypll : entity work.Clock_25to100
-port map
-(
- inclk0 => CLOCK_25,
- c0 => sysclk,
- c1 => memclk,
- locked => pll_locked
-);
-
-reset<=(not SW(0) xor KEY(0)) and pll_locked;
-
-myVirtualToplevel : entity work.zpu_soc
-generic map
-(
- SYSCLK_FREQUENCY => SYSCLK_E115_FREQ
-)
-port map
-(
- SYSCLK => sysclk,
- MEMCLK => memclk,
- RESET_IN => reset,
-
- -- RS232
- UART_RX_0 => UART_RX_0,
- UART_TX_0 => UART_TX_0,
- UART_RX_1 => UART_RX_1,
- UART_TX_1 => UART_TX_1,
-
- -- SPI signals
- SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
- SPI_MOSI => open,
- SPI_CLK => open,
- SPI_CS => open,
-
- -- SD Card (SPI) signals
- SDCARD_MISO => SDCARD_MISO,
- SDCARD_MOSI => SDCARD_MOSI,
- SDCARD_CLK => SDCARD_CLK,
- SDCARD_CS => SDCARD_CS,
-
- -- PS/2 signals
- PS2K_CLK_IN => '1',
- PS2K_DAT_IN => '1',
- PS2K_CLK_OUT => open,
- PS2K_DAT_OUT => open,
- PS2M_CLK_IN => '1',
- PS2M_DAT_IN => '1',
- PS2M_CLK_OUT => open,
- PS2M_DAT_OUT => open,
-
- -- I²C signals
- I2C_SCL_IO => open,
- I2C_SDA_IO => open,
-
- -- IOCTL Bus --
- IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
- IOCTL_UPLOAD => open, -- Uploading from FPGA.
- IOCTL_CLK => open, -- I/O Clock.
- IOCTL_WR => open, -- Write Enable to FPGA.
- IOCTL_RD => open, -- Read Enable from FPGA.
- IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
- IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
- IOCTL_ADDR => open, -- Address in FPGA to write into.
- IOCTL_DOUT => open, -- Data to be written into FPGA.
- IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
-
- -- SDRAM signals which do not exist on the E115
- SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
- SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
- SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
- SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
- SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
- SDRAM_BA => open, --SDRAM_BA, -- two banks
- SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
- SDRAM_WE_n => open, --SDRAM_WE, -- write enable
- SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
- SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
- SDRAM_READY => open -- sd ready.
-
- -- DDR2 DRAM
- --DDR2_ADDR => DDR2_ADDR, -- 14 bit multiplexed address bus
- --DDR2_DQ => DDR2_DQ, -- 64 bit bidirectional data bus
- --DDR2_DQS => DDR2_DQS, -- 8 bit bidirectional data bus
- --DDR2_DQM => DDR2_DQM, -- eight byte masks
- --DDR2_ODT => DDR2_ODT, -- 14 bit multiplexed address bus
- --DDR2_BA => DDR2_BA, -- 8 banks
- --DDR2_CS => DDR2_CS, -- 2 chip selects.
- --DDR2_WE => DDR2_WE, -- write enable
- --DDR2_RAS => DDR2_RAS, -- row address select
- --DDR2_CAS => DDR2_CAS, -- columns address select
- --DDR2_CKE => DDR2_CKE, -- 2 clock enable.
- --DDR2_CLK => DDR2_CLK -- 2 clocks.
-);
-
-
-end architecture;
diff --git a/zpu/build/E115_zpu_constraints.sdc b/zpu/build/E115_zpu_constraints.sdc
deleted file mode 100644
index f1a16ee..0000000
--- a/zpu/build/E115_zpu_constraints.sdc
+++ /dev/null
@@ -1,129 +0,0 @@
-## Generated SDC file "E115_zpu.out.sdc"
-
-## Copyright (C) 2017 Intel Corporation. All rights reserved.
-## Your use of Intel Corporation's design tools, logic functions
-## and other software and tools, and its AMPP partner logic
-## functions, and any output files from any of the foregoing
-## (including device programming or simulation files), and any
-## associated documentation or information are expressly subject
-## to the terms and conditions of the Intel Program License
-## Subscription Agreement, the Intel Quartus Prime License Agreement,
-## the Intel FPGA IP License Agreement, or other applicable license
-## agreement, including, without limitation, that your use is for
-## the sole purpose of programming logic devices manufactured by
-## Intel and sold by Intel or its authorized distributors. Please
-## refer to the applicable agreement for further details.
-
-
-## VENDOR "Altera"
-## PROGRAM "Quartus Prime"
-## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
-
-## DATE "Sat Jun 22 23:32:00 2019"
-
-##
-## DEVICE "EP4CE115F23I7"
-##
-
-
-#**************************************************************
-# Time Information
-#**************************************************************
-
-set_time_format -unit ns -decimal_places 3
-
-
-
-#**************************************************************
-# Create Clock
-#**************************************************************
-
-create_clock -name {clk_25} -period 40.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_25}]
-
-
-#**************************************************************
-# Create Generated Clock
-#**************************************************************
-
-create_generated_clock -name {SYSCLK} -source [get_ports {CLOCK_25}] -duty_cycle 50.000 -multiply_by 4 -divide_by 1 -master_clock {clk_25} [get_nets {mypll|altpll_component|_clk0}]
-#create_generated_clock -name {MEMCLK} -source [get_ports {CLOCK_25}] -duty_cycle 50.000 -multiply_by 8 -divide_by 1 -master_clock {clk_25} [get_nets {mypll|altpll_component|_clk1}]
-
-
-#**************************************************************
-# Set Clock Latency
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Uncertainty
-#**************************************************************
-
-#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
-#set_clock_uncertainty -rise_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
-#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
-#set_clock_uncertainty -fall_from [get_clocks {MEMCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
-#set_clock_uncertainty -rise_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {MEMCLK}] 0.020
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {MEMCLK}] 0.020
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -rise_to [get_clocks {SYSCLK}] 0.020
-#set_clock_uncertainty -fall_from [get_clocks {SYSCLK}] -fall_to [get_clocks {SYSCLK}] 0.020
-derive_clock_uncertainty
-
-
-#**************************************************************
-# Set Input Delay
-#**************************************************************
-
-# Delays for async signals - not necessary, but might as well avoid
-# having unconstrained ports in the design
-#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
-#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
-
-
-#**************************************************************
-# Set Output Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Groups
-#**************************************************************
-
-
-
-#**************************************************************
-# Set False Path
-#**************************************************************
-
-set_false_path -from [get_keepers {KEY*}]
-set_false_path -from [get_keepers {SW*}]
-
-
-#**************************************************************
-# Set Multicycle Path
-#**************************************************************
-
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0
-
-#**************************************************************
-# Set Maximum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Minimum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Input Transition
-#**************************************************************
-
diff --git a/zpu/build/Makefile b/zpu/build/Makefile
deleted file mode 100644
index 0293db1..0000000
--- a/zpu/build/Makefile
+++ /dev/null
@@ -1,303 +0,0 @@
-#########################################################################################################
-##
-## Name: Makefile
-## Created: June 2019
-## Author(s): Philip Smart
-## Description: ZPU Makefile
-## This script builds the ZPU test images and should be used as a basis for main
-## project builds.
-##
-## Credits:
-## Copyright: (c) 2019 Philip Smart
-##
-## History: June 2019 - Initial script written.
-##
-#########################################################################################################
-## This source file is free software: you can redistribute it and#or modify
-## it under the terms of the GNU General Public License as published
-## by the Free Software Foundation, either version 3 of the License, or
-## (at your option) any later version.
-##
-## This source file is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program. If not, see .
-#########################################################################################################
-
-DE10_IP = 192.168.10.1
-DE10_USER = root
-DE10_PWD = 1
-ROOT = ../
-
-# Build utilites
-QUARTUS_SH = quartus_sh
-QUARTUS_CPF = quartus_cpf
-TEE = tee
-ECHO = echo
-MV = mv
-GREP = grep
-RM = rm
-CC = CC $(CINCLUDES)
-AR = ar
-LD = ld
-
-# Build flags
-SH_FLAGS = --flow compile
-CPF_FLAGS = -c -o bitstream_compression=on
-MSG_FILTER = "Error\|success"
-# MSG_FILTER = "Info\|Warning\|Error\|success"
-# MSG_FILTER = "Info\|Warning\|Error\|success"
-# MSG_FILTER = "Info\|Warning\|Error\|success"
-
-SOC = $(ROOT)/zpu_soc.vhd $(ROOT)/zpu_soc_pkg.vhd
-ZPU_EVO = $(ROOT)/cpu/zpu_core_evo.vhd $(ROOT)/cpu/zpu_pkg.vhd
-
-.PHONY: all
-all: DE10_nano_SMALL DE10_nano_MEDIUM DE10_nano_FLEX DE10_nano_EVO DE10_nano_EVO_MINIMAL E115_SMALL E115_MEDIUM E115_FLEX E115_EVO E115_EVO_MINIMAL DE0_nano_SMALL DE0_nano_MEDIUM DE0_nano_FLEX DE0_nano_EVO DE0_nano_EVO_MINIMAL QMV_SMALL QMV_MEDIUM QMV_FLEX QMV_EVO QMV_EVO_MINIMAL CYC1000_SMALL CYC1000_MEDIUM CYC1000_FLEX CYC1000_EVO CYC1000_EVO_MINIMAL
-DE0_nano: DE0_nano_SMALL DE0_nano_MEDIUM DE0_nano_FLEX DE0_nano_EVO DE0_nano_EVO_MINIMAL
-DE10_nano: DE10_nano_SMALL DE10_nano_MEDIUM DE10_nano_FLEX DE10_nano_EVO DE10_nano_EVO_MINIMAL
-E115: E115_SMALL E115_MEDIUM E115_FLEX E115_EVO E115_EVO_MINIMAL
-QMV: QMV_SMALL QMV_MEDIUM QMV_FLEX QMV_EVO QMV_EVO_MINIMAL
-CYC1000: CYC1000_SMALL CYC1000_MEDIUM CYC1000_FLEX CYC1000_EVO CYC1000_EVO_MINIMAL
-SMALL: DE10_nano_SMALL E115_SMALL DE0_nano_SMALL QMV_SMALL CYC1000_SMALL
-MEDIUM: DE10_nano_MEDIUM E115_MEDIUM DE0_nano_MEDIUM QMV_MEDIUM CYC1000_MEDIUM
-FLEX: DE10_nano_FLEX E115_FLEX DE0_nano_FLEX QMV_FLEX CYC1000_FLEX
-EVO: DE10_nano_EVO E115_EVO DE0_nano_EVO QMV_EVO CYC1000_EVO
-EVO_MINIMAL: DE10_nano_EVO_MINIMAL E115_EVO_MINIMAL DE0_nano_EVO_MINIMAL QMV_EVO_MINIMAL CYC1000_EVO_MINIMAL
-
-DE10_nano_SMALL:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) DE10_nano_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-DE10_nano_MEDIUM:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) DE10_nano_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-DE10_nano_FLEX:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) DE10_nano_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-DE10_nano_EVO:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) DE10_nano_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-DE10_nano_EVO_MINIMAL:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) DE10_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) DE10_nano_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-DE0_nano_SMALL:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) DE0_nano_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-DE0_nano_MEDIUM:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) DE0_nano_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-DE0_nano_FLEX:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) DE0_nano_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-DE0_nano_EVO:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) DE0_nano_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-DE0_nano_EVO_MINIMAL:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) DE0_nano_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) DE0_nano_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-E115_SMALL:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) E115_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-E115_MEDIUM:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) E115_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-E115_FLEX:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) E115_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-E115_EVO:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) E115_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-E115_EVO_MINIMAL:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) E115_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) E115_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-QMV_SMALL:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) QMV_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-QMV_MEDIUM:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) QMV_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-QMV_FLEX:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) QMV_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-QMV_EVO:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) QMV_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-QMV_EVO_MINIMAL:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) QMV_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) QMV_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-CYC1000_SMALL:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_SMALL : integer := [01]/ZPU_SMALL : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) CYC1000_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-CYC1000_MEDIUM:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_MEDIUM : integer := [01]/ZPU_MEDIUM : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) CYC1000_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-CYC1000_FLEX:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_FLEX : integer := [01]/ZPU_FLEX : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) CYC1000_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-CYC1000_EVO:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO : integer := [01]/ZPU_EVO : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) CYC1000_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-CYC1000_EVO_MINIMAL:
- @cat $(ROOT)/zpu_soc_pkg.tmpl.vhd | sed 's/ZPU_EVO_MINIMAL : integer := [01]/ZPU_EVO_MINIMAL : integer := 1/g' \
- > $(ROOT)/zpu_soc_pkg.vhd
- @$(ECHO) "Compiling $@..."
- @$(QUARTUS_SH) $(SH_FLAGS) CYC1000_zpu.qpf 2> /dev/null | $(TEE) $@.log | $(GREP) -i $(MSG_FILTER)
- @$(MV) CYC1000_zpu.sof $@.sof
- @$(QUARTUS_CPF) $(CPF_FLAGS) $@.sof $@.rbf 2> /dev/null | $(TEE) -a $@.log | $(GREP) -i $(MSG_FILTER)
- @$(ECHO) "$@.sof and $@.rbf generated..."
-
-clean:
- @$(ECHO) "Removing all temporary files..."
- @$(RM) -fr c5_pin_model_dump.txt ./db ./simulation DE0_nano_zpu.asm.rpt DE0_nano_zpu.done DE0_nano_zpu.fit.rpt DE0_nano_zpu.fit.smsg DE0_nano_zpu.fit.summary DE0_nano_zpu.flow.rpt DE0_nano_zpu.jdi DE0_nano_zpu.map.rpt DE0_nano_zpu.map.smsg DE0_nano_zpu.map.summary DE0_nano_zpu.pin DE0_nano_zpu.rbf DE0_nano_zpu.sld DE0_nano_zpu.sof DE0_nano_zpu.sta.rpt DE0_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt DE0*.log DE0_nano*.rbf DE0_nano*.sof DE0_nano*.sta.smsg
- @$(RM) -fr c5_pin_model_dump.txt ./db DE10_nano_zpu.asm.rpt DE10_nano_zpu.done DE10_nano_zpu.fit.rpt DE10_nano_zpu.fit.smsg DE10_nano_zpu.fit.summary DE10_nano_zpu.flow.rpt DE10_nano_zpu.jdi DE10_nano_zpu.map.rpt DE10_nano_zpu.map.smsg DE10_nano_zpu.map.summary DE10_nano_zpu.pin DE10_nano_zpu.rbf DE10_nano_zpu.sld DE10_nano_zpu.sof DE10_nano_zpu.sta.rpt DE10_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt DE10*.log DE10_nano*.rbf DE10_nano*.sof DE10_nano*.sta.smsg
- @$(RM) -fr c5_pin_model_dump.txt ./db E115_zpu.asm.rpt E115_zpu.done E115_zpu.fit.rpt E115_zpu.fit.smsg E115_zpu.fit.summary E115_zpu.flow.rpt E115_zpu.jdi E115_zpu.map.rpt E115_zpu.map.smsg E115_zpu.map.summary E115_zpu.pin E115_zpu.rbf E115_zpu.sld E115_zpu.sof E115_zpu.sta.rpt E115_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt E115_zpu.pof E115*.log E115*.rbf E115*.sof E115*.sta.smsg
- @$(RM) -fr c5_pin_model_dump.txt ./db CYC1000_zpu.asm.rpt CYC1000_zpu.done CYC1000_zpu.fit.rpt CYC1000_zpu.fit.smsg CYC1000_zpu.fit.summary CYC1000_zpu.flow.rpt CYC1000_zpu.jdi CYC1000_zpu.map.rpt CYC1000_zpu.map.smsg CYC1000_zpu.map.summary CYC1000_zpu.pin CYC1000_zpu.rbf CYC1000_zpu.sld CYC1000_zpu.sof CYC1000_zpu.sta.rpt CYC1000_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt CYC1000_zpu.pof CYC1000*.log CYC1000*.rbf CYC1000*.sof CYC1000*.sta.smsg
- @$(RM) -fr c5_pin_model_dump.txt ./db QMV_zpu.asm.rpt QMV_zpu.done QMV_zpu.fit.rpt QMV_zpu.fit.smsg QMV_zpu.fit.summary QMV_zpu.flow.rpt QMV_zpu.jdi QMV_zpu.map.rpt QMV_zpu.map.smsg QMV_zpu.map.summary QMV_zpu.pin QMV_zpu.rbf QMV_zpu.sld QMV_zpu.sof QMV_zpu.sta.rpt QMV_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt QMV_zpu.pof QMV*.log QMV*.rbf QMV*.sof QMV*.sta.smsg
- @$(RM) -fr output_files
diff --git a/zpu/build/QMV_zpu.cdf b/zpu/build/QMV_zpu.cdf
deleted file mode 100644
index 81376e4..0000000
--- a/zpu/build/QMV_zpu.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition */
-JedecChain;
- FileRevision(JESD32A);
- DefaultMfr(6E);
-
- P ActionCode(Cfg)
- Device PartName(5CEFA2F23) Path("/srv/dvlp/Projects/dev/github/zpu/build/") File("QMV_zpu.sof") MfrSpec(OpMask(1));
-
-ChainEnd;
-
-AlteraBegin;
- ChainType(JTAG);
-AlteraEnd;
diff --git a/zpu/build/QMV_zpu.qpf b/zpu/build/QMV_zpu.qpf
deleted file mode 100644
index dcdf51c..0000000
--- a/zpu/build/QMV_zpu.qpf
+++ /dev/null
@@ -1,23 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-
-QUARTUS_VERSION = "5.0"
-DATE = "23:35:58 September 01, 2005"
-
-
-# Revisions
-
-PROJECT_REVISION = "QMV_zpu"
diff --git a/zpu/build/QMV_zpu.qsf b/zpu/build/QMV_zpu.qsf
deleted file mode 100644
index f28e3fa..0000000
--- a/zpu/build/QMV_zpu.qsf
+++ /dev/null
@@ -1,473 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-# ledwater_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-# assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2017"
-set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
-set_global_assignment -name CDF_FILE QMV.cdf
-
-# Pin & Location Assignments
-# ==========================
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone V"
-set_global_assignment -name TOP_LEVEL_ENTITY QMV_zpu
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE 5CEFA2F23C8
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-
-# Assembler Assignments
-# =====================
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-
-set_global_assignment -name ENABLE_SIGNALTAP ON
-set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name NUM_PARALLEL_PROCESSORS 8
-
-
-#============================================================
-# CLOCK2
-#============================================================
-
-#============================================================
-# CLOCK3
-#============================================================
-
-#============================================================
-# CLOCK4
-#============================================================
-
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_M9 -to CLOCK_50
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
-
-#============================================================
-# DRAM
-#============================================================
-set_location_assignment PIN_Y9 -to SDRAM_ADDR[12]
-set_location_assignment PIN_T9 -to SDRAM_ADDR[11]
-set_location_assignment PIN_R6 -to SDRAM_ADDR[10]
-set_location_assignment PIN_W8 -to SDRAM_ADDR[9]
-set_location_assignment PIN_T8 -to SDRAM_ADDR[8]
-set_location_assignment PIN_U8 -to SDRAM_ADDR[7]
-set_location_assignment PIN_V6 -to SDRAM_ADDR[6]
-set_location_assignment PIN_U7 -to SDRAM_ADDR[5]
-set_location_assignment PIN_U6 -to SDRAM_ADDR[4]
-set_location_assignment PIN_N6 -to SDRAM_ADDR[3]
-set_location_assignment PIN_N8 -to SDRAM_ADDR[2]
-set_location_assignment PIN_P7 -to SDRAM_ADDR[1]
-set_location_assignment PIN_P8 -to SDRAM_ADDR[0]
-set_location_assignment PIN_P9 -to SDRAM_BA[1]
-set_location_assignment PIN_T7 -to SDRAM_BA[0]
-set_location_assignment PIN_AA7 -to SDRAM_CAS
-set_location_assignment PIN_V9 -to SDRAM_CKE
-set_location_assignment PIN_AB11 -to SDRAM_CLK
-set_location_assignment PIN_AB5 -to SDRAM_CS
-set_location_assignment PIN_P12 -to SDRAM_DQ[15]
-set_location_assignment PIN_R12 -to SDRAM_DQ[14]
-set_location_assignment PIN_U12 -to SDRAM_DQ[13]
-set_location_assignment PIN_R11 -to SDRAM_DQ[12]
-set_location_assignment PIN_R10 -to SDRAM_DQ[11]
-set_location_assignment PIN_U11 -to SDRAM_DQ[10]
-set_location_assignment PIN_T10 -to SDRAM_DQ[9]
-set_location_assignment PIN_U10 -to SDRAM_DQ[8]
-set_location_assignment PIN_AA8 -to SDRAM_DQ[7]
-set_location_assignment PIN_AB8 -to SDRAM_DQ[6]
-set_location_assignment PIN_AA9 -to SDRAM_DQ[5]
-set_location_assignment PIN_Y10 -to SDRAM_DQ[4]
-set_location_assignment PIN_AB10 -to SDRAM_DQ[3]
-set_location_assignment PIN_AA10 -to SDRAM_DQ[2]
-set_location_assignment PIN_Y11 -to SDRAM_DQ[1]
-set_location_assignment PIN_AA12 -to SDRAM_DQ[0]
-set_location_assignment PIN_AB7 -to SDRAM_DQM[0]
-set_location_assignment PIN_AB6 -to SDRAM_RAS
-set_location_assignment PIN_V10 -to SDRAM_DQM[1]
-set_location_assignment PIN_W9 -to SDRAM_WE
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[6]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[7]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[8]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[9]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[10]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[11]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[12]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[13]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[14]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[15]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[0]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[1]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[2]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[3]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[4]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[5]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[6]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[7]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[8]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[9]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[10]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[11]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[12]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[13]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[14]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQ[15]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[9]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[10]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[11]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[12]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_ADDR[13]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[2]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[3]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[4]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[5]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[6]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[7]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[8]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[9]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[10]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[11]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[12]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_ADDR[13]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[0]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[1]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[2]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[3]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[4]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[5]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[6]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[7]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[8]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[9]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[10]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[11]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[12]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_ADDR[13]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[1]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQM[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQM[1]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_BA[0]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_BA[1]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQM[0]
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_DQM[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_RAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_WE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CS
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CAS
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_RAS
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_WE
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CS
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CKE
-set_instance_assignment -name SLEW_RATE 0 -to SDRAM_CLK
-
-#============================================================
-# GPIO
-#============================================================
-# U8 5 - 59, odd
-#
-# U8 6 - 58 Even
-set_location_assignment PIN_AA13 -to BANK_4A_AA13
-set_location_assignment PIN_AB15 -to BANK_4A_AB15
-set_location_assignment PIN_Y14 -to BANK_4A_Y14
-set_location_assignment PIN_AB17 -to BANK_4A_AB17
-set_location_assignment PIN_Y16 -to BANK_4A_Y16
-set_location_assignment PIN_AA17 -to BANK_4A_AA17
-set_location_assignment PIN_AA19 -to BANK_4A_AA19
-set_location_assignment PIN_Y19 -to BANK_4A_Y19
-set_location_assignment PIN_AB20 -to BANK_4A_AB20
-set_location_assignment PIN_AB22 -to BANK_4A_AB22
-set_location_assignment PIN_Y22 -to BANK_4A_Y22
-set_location_assignment PIN_W21 -to BANK_4A_W21
-set_location_assignment PIN_V21 -to BANK_4A_V21
-set_location_assignment PIN_W19 -to BANK_4A_W19
-set_location_assignment PIN_U20 -to BANK_4A_U20
-set_location_assignment PIN_T22 -to BANK_5A_T22
-set_location_assignment PIN_R21 -to BANK_5A_R21
-set_location_assignment PIN_T19 -to BANK_5A_T19
-set_location_assignment PIN_P17 -to BANK_5A_P17
-set_location_assignment PIN_N21 -to BANK_5B_N21
-set_location_assignment PIN_M20 -to BANK_5B_M20
-set_location_assignment PIN_N19 -to BANK_5B_N19
-set_location_assignment PIN_L19 -to BANK_5B_L19
-set_location_assignment PIN_L22 -to BANK_5B_L22
-set_location_assignment PIN_K17 -to BANK_5B_K17
-set_location_assignment PIN_K21 -to BANK_5B_K21
-set_location_assignment PIN_N16 -to BANK_5B_N16
-#
-# U7 5 - 59 odd
-#set_location_assignment PIN_AA14 -to BANK_4A_AA14
-#set_location_assignment PIN_AA15 -to BANK_4A_AA15
-#set_location_assignment PIN_Y15 -to BANK_4A_Y15
-#set_location_assignment PIN_AB18 -to BANK_4A_AB18
-set_location_assignment PIN_Y17 -to BANK_4A_Y17
-set_location_assignment PIN_AA18 -to BANK_4A_AA18
-set_location_assignment PIN_AA20 -to BANK_4A_AA20
-set_location_assignment PIN_Y20 -to BANK_4A_Y20
-set_location_assignment PIN_AB21 -to BANK_4A_AB21
-set_location_assignment PIN_AA22 -to BANK_4A_AA22
-set_location_assignment PIN_W22 -to BANK_4A_W22
-set_location_assignment PIN_Y21 -to BANK_4A_Y21
-set_location_assignment PIN_U22 -to BANK_4A_U22
-set_location_assignment PIN_V20 -to BANK_4A_V20
-set_location_assignment PIN_U21 -to BANK_4A_U21
-set_location_assignment PIN_R22 -to BANK_5A_R22
-set_location_assignment PIN_P22 -to BANK_5A_P22
-set_location_assignment PIN_T20 -to BANK_5A_T20
-set_location_assignment PIN_P16 -to BANK_5A_P16
-set_location_assignment PIN_N20 -to BANK_5B_N20
-set_location_assignment PIN_M21 -to BANK_5B_M21
-set_location_assignment PIN_M18 -to BANK_5B_M18
-set_location_assignment PIN_L18 -to BANK_5B_L18
-set_location_assignment PIN_M22 -to BANK_5B_M22
-set_location_assignment PIN_L17 -to BANK_5B_L17
-set_location_assignment PIN_K22 -to BANK_5B_K22
-set_location_assignment PIN_M16 -to BANK_5B_M16
-#
-# U7 6 - 60 even
-set_location_assignment PIN_AA1 -to BANK_2A_AA1
-set_location_assignment PIN_W2 -to BANK_2A_W2
-set_location_assignment PIN_U2 -to BANK_2A_U2
-set_location_assignment PIN_N2 -to BANK_2A_N2
-set_location_assignment PIN_L2 -to BANK_2A_L2
-set_location_assignment PIN_G2 -to BANK_2A_G2
-set_location_assignment PIN_D3 -to BANK_2A_D3
-set_location_assignment PIN_C2 -to BANK_2A_C2
-set_location_assignment PIN_H6 -to BANK_8A_H6
-set_location_assignment PIN_H8 -to BANK_8A_H8
-set_location_assignment PIN_E7 -to BANK_8A_E7
-set_location_assignment PIN_C6 -to BANK_8A_C6
-set_location_assignment PIN_D9 -to BANK_8A_D9
-set_location_assignment PIN_A5 -to BANK_8A_A5
-set_location_assignment PIN_B7 -to BANK_8A_B7
-set_location_assignment PIN_A8 -to BANK_8A_A8
-set_location_assignment PIN_A10 -to BANK_8A_A10
-set_location_assignment PIN_C9 -to BANK_8A_C9
-set_location_assignment PIN_F10 -to BANK_8A_F10
-set_location_assignment PIN_B11 -to BANK_7A_B11
-set_location_assignment PIN_A12 -to BANK_7A_A12
-set_location_assignment PIN_D12 -to BANK_7A_D12
-set_location_assignment PIN_C13 -to BANK_7A_C13
-set_location_assignment PIN_A13 -to BANK_7A_A13
-set_location_assignment PIN_A14 -to BANK_7A_A14
-set_location_assignment PIN_C15 -to BANK_7A_C15
-set_location_assignment PIN_B16 -to BANK_7A_B16
-
-#============================================================
-# KEY
-#============================================================
-set_location_assignment PIN_AB13 -to KEY
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY
-
-#============================================================
-# LEDR
-#============================================================
-set_location_assignment PIN_D17 -to LEDR
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR
-
-#============================================================
-# PS2
-#============================================================
-
-#============================================================
-# RESET
-#============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_N
-set_location_assignment PIN_V18 -to RESET_N
-
-##============================================================
-# SD CARD
-#============================================================
-set_location_assignment PIN_Y17 -to SDCARD_MISO[0]
-set_location_assignment PIN_AA18 -to SDCARD_MOSI[0]
-set_location_assignment PIN_AA20 -to SDCARD_CLK[0]
-set_location_assignment PIN_Y20 -to SDCARD_CS[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
-
-#============================================================
-# SW
-#============================================================
-
-##============================================================
-# UART
-#============================================================
-set_location_assignment PIN_AA14 -to UART_RX_0
-set_location_assignment PIN_AA15 -to UART_TX_0
-set_location_assignment PIN_Y15 -to UART_RX_1
-set_location_assignment PIN_AB18 -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-
-#============================================================
-# End of pin assignments by Terasic System Builder
-#============================================================
-
-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
-
-#============================================================
-# Modules and Files
-#============================================================
-
-set_global_assignment -name VHDL_FILE ../QMV_zpu_Toplevel.vhd
-set_global_assignment -name QIP_FILE Clock_50to100.qip
-set_global_assignment -name SDC_FILE QMV_zpu_constraints.sdc
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
-#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
-set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6.qip
-#set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/W9864G6_cached.qip
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
-set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/48LC16M16_cached.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6.qip
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/W9864G6_cached.qip
-set_global_assignment -name VHDL_FILE ../devices/WishBone/SRAM/sram.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
-set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-
-
-
-
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/zpu/build/QMV_zpu_Toplevel.vhd b/zpu/build/QMV_zpu_Toplevel.vhd
deleted file mode 100644
index 3464451..0000000
--- a/zpu/build/QMV_zpu_Toplevel.vhd
+++ /dev/null
@@ -1,175 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.zpu_soc_pkg.all;
-
-entity QMV_zpu is
- port (
- -- Clock
- CLOCK_50 : in std_logic;
- -- RED LED
- LEDR : out std_logic;
- -- Debounced keys
- KEY : in std_logic;
- -- DIP switches
- -- SW : in std_logic_vector(3 downto 0);
-
- -- TDI : in std_logic;
- -- TCK : in std_logic;
- -- TCS : in std_logic;
- -- TDO : out std_logic;
- -- I2C_SDAT : inout std_logic;
- -- I2C_SCLK : out std_logic;
- -- GPIO_0 : inout std_logic_vector(33 downto 0);
- -- GPIO_1 : inout std_logic_vector(33 downto 0);
-
- -- SD Card 1
- SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
-
- -- UART Serial channels.
- UART_RX_0 : in std_logic;
- UART_TX_0 : out std_logic;
- UART_RX_1 : in std_logic;
- UART_TX_1 : out std_logic;
-
- SDRAM_CLK : out std_logic; -- sdram is accessed at 128MHz
- SDRAM_CKE : out std_logic; -- clock enable.
- SDRAM_DQ : inout std_logic_vector(15 downto 0); -- 16 bit bidirectional data bus
- SDRAM_ADDR : out std_logic_vector(11 downto 0); -- 13 bit multiplexed address bus
- SDRAM_DQM : out std_logic_vector(1 downto 0); -- two byte masks
- SDRAM_BA : out std_logic_vector(1 downto 0); -- two banks
- SDRAM_CS : out std_logic; -- a single chip select
- SDRAM_WE : out std_logic; -- write enable
- SDRAM_RAS : out std_logic; -- row address select
- SDRAM_CAS : out std_logic -- columns address select
- );
-END entity;
-
-architecture rtl of QMV_zpu is
-
- signal reset : std_logic;
- signal sysclk : std_logic;
- signal memclk : std_logic;
- signal pll_locked : std_logic;
-
- --signal ps2m_clk_in : std_logic;
- --signal ps2m_clk_out : std_logic;
- --signal ps2m_dat_in : std_logic;
- --signal ps2m_dat_out : std_logic;
-
- --signal ps2k_clk_in : std_logic;
- --signal ps2k_clk_out : std_logic;
- --signal ps2k_dat_in : std_logic;
- --signal ps2k_dat_out : std_logic;
-
- --alias PS2_MDAT : std_logic is GPIO_1(19);
- --alias PS2_MCLK : std_logic is GPIO_1(18);
-
-begin
-
---I2C_SDAT <= 'Z';
---GPIO_0(33 downto 2) <= (others => 'Z');
---GPIO_1 <= (others => 'Z');
---LED <= "101010" & reset & UART_RX_0;
-LEDR <= '0';
-
-mypll : entity work.Clock_50to100
-port map
-(
- areset => not KEY,
- inclk0 => CLOCK_50,
- c0 => sysclk,
- c1 => memclk,
- locked => pll_locked
-);
-
-reset <= KEY and pll_locked;
-
-myVirtualToplevel : entity work.zpu_soc
-generic map
-(
- SYSCLK_FREQUENCY => SYSCLK_QMV_FREQ
-)
-port map
-(
- SYSCLK => sysclk,
- MEMCLK => memclk,
- RESET_IN => reset,
-
- -- RS232
- UART_RX_0 => UART_RX_0,
- UART_TX_0 => UART_TX_0,
- UART_RX_1 => UART_RX_1,
- UART_TX_1 => UART_TX_1,
-
- -- SPI signals
- SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
- SPI_MOSI => open,
- SPI_CLK => open,
- SPI_CS => open,
-
- -- SD Card (SPI) signals
- SDCARD_MISO => SDCARD_MISO,
- SDCARD_MOSI => SDCARD_MOSI,
- SDCARD_CLK => SDCARD_CLK,
- SDCARD_CS => SDCARD_CS,
-
- -- PS/2 signals
- PS2K_CLK_IN => '1',
- PS2K_DAT_IN => '1',
- PS2K_CLK_OUT => open,
- PS2K_DAT_OUT => open,
- PS2M_CLK_IN => '1',
- PS2M_DAT_IN => '1',
- PS2M_CLK_OUT => open,
- PS2M_DAT_OUT => open,
-
- -- I²C signals
- I2C_SCL_IO => open,
- I2C_SDA_IO => open,
-
- -- IOCTL Bus --
- IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
- IOCTL_UPLOAD => open, -- Uploading from FPGA.
- IOCTL_CLK => open, -- I/O Clock.
- IOCTL_WR => open, -- Write Enable to FPGA.
- IOCTL_RD => open, -- Read Enable from FPGA.
- IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
- IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
- IOCTL_ADDR => open, -- Address in FPGA to write into.
- IOCTL_DOUT => open, -- Data to be written into FPGA.
- IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
-
- -- SDRAM signals
- SDRAM_CLK => SDRAM_CLK, -- sdram is accessed at 128MHz
- SDRAM_CKE => SDRAM_CKE, -- clock enable.
- SDRAM_DQ => SDRAM_DQ, -- 16 bit bidirectional data bus
- SDRAM_ADDR => SDRAM_ADDR, -- 13 bit multiplexed address bus
- SDRAM_DQM => SDRAM_DQM, -- two byte masks
- SDRAM_BA => SDRAM_BA, -- two banks
- SDRAM_CS_n => SDRAM_CS, -- a single chip select
- SDRAM_WE_n => SDRAM_WE, -- write enable
- SDRAM_RAS_n => SDRAM_RAS, -- row address select
- SDRAM_CAS_n => SDRAM_CAS, -- columns address select
- SDRAM_READY => open -- sd ready.
-
- -- DDR2 DRAM - doesnt exist on the QMV.
- --DDR2_ADDR => open, -- 14 bit multiplexed address bus
- --DDR2_DQ => open, -- 64 bit bidirectional data bus
- --DDR2_DQS => open, -- 8 bit bidirectional data bus
- --DDR2_DQM => open, -- eight byte masks
- --DDR2_ODT => open, -- 14 bit multiplexed address bus
- --DDR2_BA => open, -- 8 banks
- --DDR2_CS => open, -- 2 chip selects.
- --DDR2_WE => open, -- write enable
- --DDR2_RAS => open, -- row address select
- --DDR2_CAS => open, -- columns address select
- --DDR2_CKE => open, -- 2 clock enable.
- --DDR2_CLK => open -- 2 clocks.
-);
-
-
-end architecture;
diff --git a/zpu/build/QMV_zpu_constraints.sdc b/zpu/build/QMV_zpu_constraints.sdc
deleted file mode 100644
index 7c53f12..0000000
--- a/zpu/build/QMV_zpu_constraints.sdc
+++ /dev/null
@@ -1,121 +0,0 @@
-## Generated SDC file "QMV_zpu.out.sdc"
-
-## Copyright (C) 2017 Intel Corporation. All rights reserved.
-## Your use of Intel Corporation's design tools, logic functions
-## and other software and tools, and its AMPP partner logic
-## functions, and any output files from any of the foregoing
-## (including device programming or simulation files), and any
-## associated documentation or information are expressly subject
-## to the terms and conditions of the Intel Program License
-## Subscription Agreement, the Intel Quartus Prime License Agreement,
-## the Intel FPGA IP License Agreement, or other applicable license
-## agreement, including, without limitation, that your use is for
-## the sole purpose of programming logic devices manufactured by
-## Intel and sold by Intel or its authorized distributors. Please
-## refer to the applicable agreement for further details.
-
-
-## VENDOR "Altera"
-## PROGRAM "Quartus Prime"
-## VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
-
-## DATE "Sat Jun 22 23:32:00 2019"
-
-##
-## DEVICE "5CEFA2F23C8"
-##
-
-
-#**************************************************************
-# Time Information
-#**************************************************************
-set_time_format -unit ns -decimal_places 3
-
-#**************************************************************
-# Create Clock
-#**************************************************************
-create_clock -name {clk_50} -period 20.000 -waveform { 0.000 0.500 } [get_ports {CLOCK_50}]
-
-#**************************************************************
-# Create Generated Clock
-#**************************************************************
-
-create_generated_clock -name {SYSCLK} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50.000 -multiply_by 2 -divide_by 1 -phase 000 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER|divclk}]
-create_generated_clock -name {MEMCLK} -source [get_pins {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50.000 -multiply_by 2 -divide_by 1 -offset -2500 -master_clock {clk_50} [get_pins {mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER|divclk}]
-
-#**************************************************************
-# Set Clock Latency
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Uncertainty
-#**************************************************************
-
-derive_clock_uncertainty
-#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -setup 0.080
-#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -hold 0.060
-#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -setup 0.080
-#set_clock_uncertainty -rise_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -hold 0.060
-#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -setup 0.080
-#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -rise_to [get_clocks {clk_50}] -hold 0.060
-#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -setup 0.080
-#set_clock_uncertainty -fall_from [get_clocks {clk_50}] -fall_to [get_clocks {clk_50}] -hold 0.060
-
-
-#**************************************************************
-# Set Input Delay
-#**************************************************************
-
-# Delays for async signals - not necessary, but might as well avoid
-# having unconstrained ports in the design
-#set_input_delay -clock sysclk -min 0.5 [get_ports {UART_RXD}]
-#set_input_delay -clock sysclk -max 0.5 [get_ports {UART_RXD}]
-
-
-#**************************************************************
-# Set Output Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Groups
-#**************************************************************
-
-
-
-#**************************************************************
-# Set False Path
-#**************************************************************
-
-set_false_path -from [get_keepers {KEY*}]
-#set_false_path -from [get_keepers {SW*}]
-
-
-#**************************************************************
-# Set Multicycle Path
-#**************************************************************
-
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -setup -start 1
-#set_multicycle_path -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] -hold -start 0
-#set_multicycle_path -setup -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 1
-#set_multicycle_path -hold -start -from [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|pc[*]}] -to [get_keepers {zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|mxFifo[*]}] 0
-
-#**************************************************************
-# Set Maximum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Minimum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Input Transition
-#**************************************************************
-
diff --git a/zpu/build/ReVerSE-U16.qpf b/zpu/build/ReVerSE-U16.qpf
deleted file mode 100644
index 03045fb..0000000
--- a/zpu/build/ReVerSE-U16.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2017 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel FPGA IP License Agreement, or other applicable license
-# agreement, including, without limitation, that your use is for
-# the sole purpose of programming logic devices manufactured by
-# Intel and sold by Intel or its authorized distributors. Please
-# refer to the applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
-# Date created = 00:31:03 November 27, 2019
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "17.1"
-DATE = "00:31:03 November 27, 2019"
-
-# Revisions
-
-PROJECT_REVISION = "ReVerSE-U16"
diff --git a/zpu/build/ReVerSE_U16.qpf b/zpu/build/ReVerSE_U16.qpf
deleted file mode 100644
index a2b2ab9..0000000
--- a/zpu/build/ReVerSE_U16.qpf
+++ /dev/null
@@ -1,23 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-
-QUARTUS_VERSION = "5.0"
-DATE = "23:35:58 September 01, 2005"
-
-
-# Revisions
-
-PROJECT_REVISION = "ReVerSE_U16"
diff --git a/zpu/build/ReVerSE_U16.qsf b/zpu/build/ReVerSE_U16.qsf
deleted file mode 100644
index 41e25c2..0000000
--- a/zpu/build/ReVerSE_U16.qsf
+++ /dev/null
@@ -1,211 +0,0 @@
-# Copyright (C) 1991-2005 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-# ledwater_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-# assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-# Project-Wide Assignments
-# ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:35:58 SEPTEMBER 01, 2005"
-set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition"
-#set_global_assignment -name VERILOG_FILE ledwater.v
-set_global_assignment -name CDF_FILE E115.cdf
-
-# Pin & Location Assignments
-# ==========================
-
-# Analysis & Synthesis Assignments
-# ================================
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name TOP_LEVEL_ENTITY ReVerSE_U16
-
-# Fitter Assignments
-# ==================
-set_global_assignment -name DEVICE EP4CE22E22C7
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
-
-# Assembler Assignments
-# =====================
-
-set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
-set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
-set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
-
-
-#============================================================
-# UART
-#============================================================
-set_location_assignment PIN_72 -to UART_RX_0
-set_location_assignment PIN_71 -to UART_TX_0
-#set_location_assignment PIN_C6 -to UART_RX_1
-#set_location_assignment PIN_D7 -to UART_TX_1
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_0
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_0
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TX_1
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RX_1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_0
-#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to UART_TX_1
-
-#============================================================
-# SD CARD
-#============================================================
-#set_location_assignment PIN_C8 -to SDCARD_MISO[0]
-#set_location_assignment PIN_C7 -to SDCARD_MOSI[0]
-#set_location_assignment PIN_B8 -to SDCARD_CLK[0]
-#set_location_assignment PIN_A8 -to SDCARD_CS[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MISO[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_MOSI[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CLK[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDCARD_CS[0]
-#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_MOSI[0]
-#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CLK[0]
-#set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDCARD_CS[0]
-
-#============================================================
-# CLOCK
-#============================================================
-set_location_assignment PIN_25 -to REVERSEU16_CLOCK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to REVERSEU16_CLOCK
-#set_location_assignment PIN_AB11 -to clk_25M
-
-#============================================================
-# LED
-#============================================================
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
-#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
-#set_location_assignment PIN_A5 -to LED[0]
-#set_location_assignment PIN_B5 -to LED[1]
-#set_location_assignment PIN_C4 -to LED[2]
-#set_location_assignment PIN_C3 -to LED[3]
-
-
-set_location_assignment PIN_32 -to reset_button
-set_location_assignment PIN_98 -to SDRAM_ADDR[0]
-set_location_assignment PIN_86 -to SDRAM_ADDR[1]
-set_location_assignment PIN_87 -to SDRAM_ADDR[2]
-set_location_assignment PIN_105 -to SDRAM_ADDR[3]
-set_location_assignment PIN_76 -to SDRAM_ADDR[4]
-set_location_assignment PIN_77 -to SDRAM_ADDR[5]
-set_location_assignment PIN_80 -to SDRAM_ADDR[6]
-set_location_assignment PIN_83 -to SDRAM_ADDR[7]
-set_location_assignment PIN_85 -to SDRAM_ADDR[8]
-set_location_assignment PIN_67 -to SDRAM_ADDR[9]
-set_location_assignment PIN_99 -to SDRAM_ADDR[10]
-set_location_assignment PIN_69 -to SDRAM_ADDR[11]
-set_location_assignment PIN_68 -to SDRAM_ADDR[12]
-set_location_assignment PIN_101 -to SDRAM_BA[0]
-set_location_assignment PIN_100 -to SDRAM_BA[1]
-set_location_assignment PIN_43 -to SDRAM_CLK
-set_location_assignment PIN_119 -to SDRAM_DQM[0]
-set_location_assignment PIN_66 -to SDRAM_DQM[1]
-set_location_assignment PIN_142 -to SDRAM_DQ[0]
-set_location_assignment PIN_141 -to SDRAM_DQ[1]
-set_location_assignment PIN_137 -to SDRAM_DQ[2]
-set_location_assignment PIN_136 -to SDRAM_DQ[3]
-set_location_assignment PIN_135 -to SDRAM_DQ[4]
-set_location_assignment PIN_125 -to SDRAM_DQ[5]
-set_location_assignment PIN_121 -to SDRAM_DQ[6]
-set_location_assignment PIN_120 -to SDRAM_DQ[7]
-set_location_assignment PIN_65 -to SDRAM_DQ[8]
-set_location_assignment PIN_64 -to SDRAM_DQ[9]
-set_location_assignment PIN_60 -to SDRAM_DQ[10]
-set_location_assignment PIN_46 -to SDRAM_DQ[11]
-set_location_assignment PIN_44 -to SDRAM_DQ[12]
-set_location_assignment PIN_59 -to SDRAM_DQ[13]
-set_location_assignment PIN_42 -to SDRAM_DQ[14]
-set_location_assignment PIN_58 -to SDRAM_DQ[15]
-set_location_assignment PIN_106 -to SDRAM_nCAS
-set_location_assignment PIN_103 -to SDRAM_nRAS
-set_location_assignment PIN_104 -to SDRAM_nWE
-
-#============================================================
-# Modules and Files
-#============================================================
-
-set_global_assignment -name VHDL_FILE ../ReVerSE_U16_Toplevel.vhd
-set_global_assignment -name QIP_FILE Clock_25to100.qip
-set_global_assignment -name SDC_FILE ReVerSE_U16_constraints.sdc
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_flex.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_pkg.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_small.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_medium.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_core_evo_L2.vhd
-set_global_assignment -name VHDL_FILE ../cpu/zpu_uart_debug.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc_pkg.vhd
-set_global_assignment -name VHDL_FILE ../zpu_soc.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/RAM/dpram.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/uart/uart.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/intr/interrupt_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/spi/spi.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/SDMMC/SDCard.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ps2/io_ps2_com.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/timer/timer_controller.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/BootROM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/DualPortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBootBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/BRAM/SinglePortBRAM.vhd
-set_global_assignment -name VHDL_FILE ../devices/sysbus/ioctl/ioctl.vhd
-#set_global_assignment -name VHDL_FILE ../devices/sysbus/TCPU/tcpu.vhd
-set_global_assignment -name QIP_FILE ../devices/sysbus/SDRAM/sdram.qip
-#set_global_assignment -name VHDL_FILE ../devices/sysbus/SDRAM/sdram.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_top.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_byte_ctrl.vhd
-set_global_assignment -name VHDL_FILE ../devices/WishBone/I2C/i2c_master_bit_ctrl.vhd
-#set_global_assignment -name QIP_FILE ../devices/WishBone/SDRAM/wbsdram.qip
-set_global_assignment -name VHDL_FILE ../devices/WishBone/SDRAM/wbsdram.vhd
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
-set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
-set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
-set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
-set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
-
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/zpu/build/ReVerSE_U16_Toplevel.vhd b/zpu/build/ReVerSE_U16_Toplevel.vhd
deleted file mode 100644
index ff186ac..0000000
--- a/zpu/build/ReVerSE_U16_Toplevel.vhd
+++ /dev/null
@@ -1,165 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.zpu_soc_pkg.all;
-
-entity ReVerSE_U16 is
- port (
- -- Clock
- REVERSEU16_CLOCK: in std_logic;
- --
- reset_button : in std_logic;
- -- LED
- --LED : out std_logic_vector(7 downto 0);
- -- Debounced keys
- --KEY : in std_logic_vector(1 downto 0);
- -- DIP switches
- --SW : in std_logic_vector(3 downto 0);
-
- -- TDI : in std_logic;
- -- TCK : in std_logic;
- -- TCS : in std_logic;
- -- TDO : out std_logic;
- -- I2C_SDAT : inout std_logic;
- -- I2C_SCLK : out std_logic;
- -- GPIO_0 : inout std_logic_vector(33 downto 0);
- -- GPIO_1 : inout std_logic_vector(33 downto 0);
-
- -- SD Card 1
- SDCARD_MISO : in std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_MOSI : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CLK : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
- SDCARD_CS : out std_logic_vector(SOC_SD_DEVICES-1 downto 0);
-
- -- UART Serial channels.
- UART_RX_0 : in std_logic;
- UART_TX_0 : out std_logic
- --UART_RX_1 : in std_logic;
- --UART_TX_1 : out std_logic
-
- -- DDR2 DRAM
- --DDR2_ADDR : out std_logic_vector(13 downto 0); -- 14 bit multiplexed address bus
- --DDR2_DQ : inout std_logic_vector(63 downto 0); -- 64 bit bidirectional data bus
- --DDR2_DQS : inout std_logic_vector(7 downto 0); -- 8 bit bidirectional data bus
- --DDR2_DQM : out std_logic_vector(17 downto 0); -- eight byte masks
- --DDR2_ODT : out std_logic_vector(1 downto 0); -- 14 bit multiplexed address bus
- --DDR2_BA : out std_logic_vector(2 downto 0); -- 8 banks
- --DDR2_CS : out std_logic_vector(1 downto 0); -- 2 chip selects.
- --DDR2_WE : out std_logic; -- write enable
- --DDR2_RAS : out std_logic; -- row address select
- --DDR2_CAS : out std_logic; -- columns address select
- --DDR2_CKE : out std_logic_vector(1 downto 0); -- 2 clock enable.
- --DDR2_CLK : out std_logic_vector(1 downto 0) -- 2 clocks.
- );
-END entity;
-
-architecture rtl of ReVerSE_U16 is
-
- signal reset : std_logic;
- signal sysclk : std_logic;
- signal memclk : std_logic;
- signal pll_locked : std_logic;
-
- --signal ps2m_clk_in : std_logic;
- --signal ps2m_clk_out : std_logic;
- --signal ps2m_dat_in : std_logic;
- --signal ps2m_dat_out : std_logic;
-
- --signal ps2k_clk_in : std_logic;
- --signal ps2k_clk_out : std_logic;
- --signal ps2k_dat_in : std_logic;
- --signal ps2k_dat_out : std_logic;
-
- --alias PS2_MDAT : std_logic is GPIO_1(19);
- --alias PS2_MCLK : std_logic is GPIO_1(18);
-
-begin
-
---I2C_SDAT <= 'Z';
---GPIO_0(33 downto 2) <= (others => 'Z');
---GPIO_1 <= (others => 'Z');
---LED <= "101010" & reset & UART_RX_0;
---LED <= "00000000";
-
-mypll : entity work.Clock_25to100
-port map
-(
- inclk0 => REVERSEU16_CLOCK,
- c0 => sysclk,
- c1 => memclk,
- locked => pll_locked
-);
-
-reset <= reset_button or pll_locked;
-
-myVirtualToplevel : entity work.zpu_soc
-generic map
-(
- SYSCLK_FREQUENCY => SYSCLK_E115_FREQ
-)
-port map
-(
- SYSCLK => sysclk,
- MEMCLK => memclk,
- RESET_IN => reset,
-
- -- RS232
- UART_RX_0 => UART_RX_0,
- UART_TX_0 => UART_TX_0,
- UART_RX_1 => '0',
- UART_TX_1 => open,
-
- -- SPI signals
- SPI_MISO => '1', -- Allow the SPI interface not to be plumbed in.
- SPI_MOSI => open,
- SPI_CLK => open,
- SPI_CS => open,
-
- -- SD Card (SPI) signals
- SDCARD_MISO => SDCARD_MISO,
- SDCARD_MOSI => SDCARD_MOSI,
- SDCARD_CLK => SDCARD_CLK,
- SDCARD_CS => SDCARD_CS,
-
- -- PS/2 signals
- PS2K_CLK_IN => '1',
- PS2K_DAT_IN => '1',
- PS2K_CLK_OUT => open,
- PS2K_DAT_OUT => open,
- PS2M_CLK_IN => '1',
- PS2M_DAT_IN => '1',
- PS2M_CLK_OUT => open,
- PS2M_DAT_OUT => open,
-
- -- I²C signals
- I2C_SCL_IO => open,
- I2C_SDA_IO => open,
-
- -- IOCTL Bus --
- IOCTL_DOWNLOAD => open, -- Downloading to FPGA.
- IOCTL_UPLOAD => open, -- Uploading from FPGA.
- IOCTL_CLK => open, -- I/O Clock.
- IOCTL_WR => open, -- Write Enable to FPGA.
- IOCTL_RD => open, -- Read Enable from FPGA.
- IOCTL_SENSE => '0', -- Sense to see if HPS accessing ioctl bus.
- IOCTL_SELECT => open, -- Enable IOP control over ioctl bus.
- IOCTL_ADDR => open, -- Address in FPGA to write into.
- IOCTL_DOUT => open, -- Data to be written into FPGA.
- IOCTL_DIN => (others => '0'), -- Data to be read into HPS.
-
- -- SDRAM signals which do not exist on the E115
- SDRAM_CLK => open, --SDRAM_CLK, -- sdram is accessed at 128MHz
- SDRAM_CKE => open, --SDRAM_CKE, -- clock enable.
- SDRAM_DQ => open, --SDRAM_DQ, -- 16 bit bidirectional data bus
- SDRAM_ADDR => open, --SDRAM_ADDR, -- 13 bit multiplexed address bus
- SDRAM_DQM => open, --SDRAM_DQM, -- two byte masks
- SDRAM_BA => open, --SDRAM_BA, -- two banks
- SDRAM_CS_n => open, --SDRAM_CS, -- a single chip select
- SDRAM_WE_n => open, --SDRAM_WE, -- write enable
- SDRAM_RAS_n => open, --SDRAM_RAS, -- row address select
- SDRAM_CAS_n => open, --SDRAM_CAS, -- columns address select
- SDRAM_READY => open -- sd ready.
-);
-
-
-end architecture;
diff --git a/zpu/build/clean.sh b/zpu/build/clean.sh
deleted file mode 100755
index 7010966..0000000
--- a/zpu/build/clean.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/bash
-
-rm -fr c5_pin_model_dump.txt ./db DE10_nano_zpu.asm.rpt DE10_nano_zpu.done DE10_nano_zpu.fit.rpt DE10_nano_zpu.fit.smsg DE10_nano_zpu.fit.summary DE10_nano_zpu.flow.rpt DE10_nano_zpu.jdi DE10_nano_zpu.map.rpt DE10_nano_zpu.map.smsg DE10_nano_zpu.map.summary DE10_nano_zpu.pin DE10_nano_zpu.rbf DE10_nano_zpu.sld DE10_nano_zpu.sof DE10_nano_zpu.sta.rpt DE10_nano_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt
-rm -fr c5_pin_model_dump.txt ./db E115_zpu.asm.rpt E115_zpu.done E115_zpu.fit.rpt E115_zpu.fit.smsg E115_zpu.fit.summary E115_zpu.flow.rpt E115_zpu.jdi E115_zpu.map.rpt E115_zpu.map.smsg E115_zpu.map.summary E115_zpu.pin E115_zpu.rbf E115_zpu.sld E115_zpu.sof E115_zpu.sta.rpt E115_zpu.sta.summary ./incremental_db qmegawiz_errors_log.txt E115_zpu.pof
diff --git a/zpu/build/ddd b/zpu/build/ddd
deleted file mode 100644
index e0f6620..0000000
--- a/zpu/build/ddd
+++ /dev/null
@@ -1,617 +0,0 @@
----------------------------------------------------------------------------------------------------------
---
--- Name: sdram.vhd
--- Created: September 2019
--- Original Author: Stephen J. Leary 2013-2014
--- VHDL Author: Philip Smart
--- Description: Original verilog module written by Stephen J. Leary 2013-2014 for the Archimedes
--- emulator with the MT48LC16M16 chip.
--- The verilog has been translated into VHDL and adapted for both the system bus and
--- the Wishbone bus undergoing extensive modifications to work with the ZPU EVO processor,
--- specifically parameterisation and burst tuning to enhance L2 Cache Fill performance.
--- Credits:
--- Copyright: Copyright (c) 2013-2014, Stephen J. Leary, All rights reserved.
--- VHDL translation, sysbus adaptation and enhancements (c) 2019 Philip Smart
---
---
--- History: September 2019 - Initial module translation to VHDL based on Stephen J. Leary's Verilog
--- source code.
--- November 2019 - Adapted for the system bus for use when no Wishbone interface is
--- instantiated in the ZPU Evo.
---
----------------------------------------------------------------------------------------------------------
--- This source file is free software: you can redistribute it and-or modify
--- it under the terms of the GNU General Public License as published
--- by the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This source file is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see .
----------------------------------------------------------------------------------------------------------
-library ieee;
-library pkgs;
-library work;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.zpu_soc_pkg.all;
-use work.zpu_pkg.all;
-
-entity SDRAM is
- generic (
- MAX_DATACACHE_BITS : integer := 4; -- Maximum size in addr bits of 32bit datacache for burst transactions.
- SDRAM_ROWS : integer := 4096; -- Number of Rows in the SDRAM.
- SDRAM_COLUMNS : integer := 256; -- Number of Columns in an SDRAM page (ie. 1 row).
- SDRAM_BANKS : integer := 4; -- Number of banks in the SDRAM.
- SDRAM_DATAWIDTH : integer := 16; -- Data width of SDRAM chip (ie. 16, 32).
- SDRAM_CLK_FREQ : integer := 100000000; -- Frequency of the SDRAM clock in Hertz.
- SDRAM_tRCD : integer := 2; -- tRCD - RAS to CAS minimum period (in ns), ie. 20ns -> 2 cycles@100MHz
- SDRAM_tRP : integer := 2; -- tRP - Precharge delay, min time for a precharge command to complete (in ns), ie. 15ns -> 2 cycles@100MHz
- SDRAM_tRFC : integer := 70; -- tRFC - Auto-refresh minimum time to complete (in ns), ie. 66ns
- SDRAM_tREF : integer := 64 -- tREF - period of time a complete refresh of all rows is made within (in ms).
- );
- port (
- -- SDRAM Interface
- SDRAM_CLK : in std_logic; -- SDRAM is accessed at given clock, frequency specified in RAM_CLK.
- SDRAM_RST : in std_logic; -- Reset the sdram controller.
- SDRAM_CKE : out std_logic; -- Clock enable.
- SDRAM_DQ : inout std_logic_vector(SDRAM_DATAWIDTH-1 downto 0); -- Bidirectional data bus
- SDRAM_ADDR : out std_logic_vector(log2ceil(SDRAM_ROWS) - 1 downto 0); -- Multiplexed address bus
- SDRAM_DQM : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of byte masks dependent on number of banks.
- SDRAM_BA : out std_logic_vector(log2ceil(SDRAM_BANKS) - 1 downto 0); -- Number of banks in SDRAM
- SDRAM_CS_n : out std_logic; -- Single chip select
- SDRAM_WE_n : out std_logic; -- Write enable
- SDRAM_RAS_n : out std_logic; -- Row address select
- SDRAM_CAS_n : out std_logic; -- Columns address select
- SDRAM_READY : out std_logic; -- SD ready.
-
- -- CPU Interface
- CLK : in std_logic; -- System master clock
- RESET : in std_logic; -- High active sync reset
- ADDR : in std_logic_vector(log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS) downto 0);
- DATA_IN : in std_logic_vector(WORD_32BIT_RANGE); -- Write data
- DATA_OUT : out std_logic_vector(WORD_32BIT_RANGE); -- Read data
- WRITE_BYTE : in std_logic; -- Write a single byte as specified in A1:A0
- WRITE_HWORD : in std_logic; -- Write a 16bit word as specified in A1
- CS : in std_logic; -- Chip Select.
- WREN : in std_logic; -- Write enable.
- RDEN : in std_logic; -- Read enable.
- BUSY : out std_logic -- Memory is busy, hold CPU.
- );
-end SDRAM;
-
-architecture Structure of SDRAM is
-
- -- Constants to define the structure of the SDRAM in bits for provisioning of signals.
- constant SDRAM_ROW_BITS : integer := log2ceil(SDRAM_ROWS);
- constant SDRAM_COLUMN_BITS : integer := log2ceil(SDRAM_COLUMNS);
- constant SDRAM_ARRAY_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS);
- constant SDRAM_BANK_BITS : integer := log2ceil(SDRAM_BANKS);
- constant SDRAM_ADDR_BITS : integer := log2ceil(SDRAM_ROWS * SDRAM_COLUMNS * SDRAM_BANKS);
-
- -- Command table for a standard SDRAM.
- --
- -- Name (Function) CKE CS# RAS# CAS# WE# DQM ADDR DQ
- -- COMMAND INHIBIT (NOP) H H X X X X X X
- -- NO OPERATION (NOP) H L H H H X X X
- -- ACTIVE (select bank and activate row) H L L H H X Bank/row X
- -- READ (select bank and column, and start READ burst) H L H L H L/H Bank/col X
- -- WRITE (select bank and column, and start WRITE burst) H L H L L L/H Bank/col Valid
- -- BURST TERMINATE H L H H L X X Active
- -- PRECHARGE (Deactivate row in bank or banks) H L L H L X Code X
- -- AUTO REFRESH or SELF REFRESH (enter self refresh mode) H L L L H X X X
- -- LOAD MODE REGISTER H L L L L X Op-code X
- -- Write enable/output enable H X X X X L X Active
- -- Write inhibit/output High-Z H X X X X H X High-Z
- -- Self Refresh Entry L L L L H X X X
- -- Self Refresh Exit (Device is idle) H H X X X X X X
- -- Self Refresh Exit (Device is in Self Refresh state) H L H H X X X X
- -- Clock suspend mode Entry L X X X X X X X
- -- Clock suspend mode Exit H X X X X X X X
- -- Power down mode Entry (Device is idle) L H X X X X X X
- -- Power down mode Entry (Device is Active) L L H H X X X X
- -- Power down mode Exit (Any state) H H X X X X X X
- -- Power down mode Exit (Device is powered down) H L H H X X X X
-
- constant CMD_INHIBIT : std_logic_vector(4 downto 0) := "11111";
- constant CMD_NOP : std_logic_vector(4 downto 0) := "10111";
- constant CMD_ACTIVE : std_logic_vector(4 downto 0) := "10011";
- constant CMD_READ : std_logic_vector(4 downto 0) := "10101";
- constant CMD_WRITE : std_logic_vector(4 downto 0) := "10100";
- constant CMD_BURST_TERMINATE : std_logic_vector(4 downto 0) := "10110";
- constant CMD_PRECHARGE : std_logic_vector(4 downto 0) := "10010";
- constant CMD_AUTO_REFRESH : std_logic_vector(4 downto 0) := "10001";
- constant CMD_LOAD_MODE : std_logic_vector(4 downto 0) := "10000";
- constant CMD_SELF_REFRESH_START : std_logic_vector(4 downto 0) := "00001";
- constant CMD_SELF_REFRESH_END : std_logic_vector(4 downto 0) := "10110";
- constant CMD_CLOCK_SUSPEND : std_logic_vector(4 downto 0) := "00000";
- constant CMD_CLOCK_RESTORE : std_logic_vector(4 downto 0) := "10000";
- constant CMD_POWER_DOWN : std_logic_vector(4 downto 0) := "01000";
- constant CMD_POWER_RESTORE : std_logic_vector(4 downto 0) := "01100";
-
- -- Load Mode Register setting for a standard SDRAM.
- --
- -- xx:10 = Reserved :
- -- 9 = Write Burst Mode : 0 = Programmed Burst Length, 1 = Single Location Access
- -- 8:7 = Operating Mode : 00 = Standard Operation, all other values reserved.
- -- 6:4 = CAS Latency : 010 = 2, 011 = 3, all other values reserved.
- -- 3 = Burst Type : 0 = Sequential, 1 = Interleaved.
- -- 2:0 = Burst Length : When 000 = 1, 001 = 2, 010 = 4, 011 = 8, all others reserved except 111 when BT = 0 sets full page access.
- -- | A12-A10 | A9 A8-A7 | A6 A5 A4 | A3Â A2 A1 A0 |
- -- | reserved| wr burst |reserved| CAS Ltncy|addr mode| burst len|
- constant WRITE_BURST_MODE : std_logic := '1';
- constant OP_MODE : std_logic_vector(1 downto 0) := "00";
- constant CAS_LATENCY : std_logic_vector(2 downto 0) := "011";
- constant BURST_TYPE : std_logic := '0';
- constant BURST_LENGTH : std_logic_vector(2 downto 0) := "000";
- constant MODE : std_logic_vector(SDRAM_ROW_BITS-1 downto 0) := std_logic_vector(to_unsigned(to_integer(unsigned("00" & WRITE_BURST_MODE & OP_MODE & CAS_LATENCY & BURST_TYPE & BURST_LENGTH)), SDRAM_ROW_BITS));
-
- -- FSM Cycle States governed in units of time, the state changes location according to the configurable parameters to ensure correct actuation at the correct time.
- --
- constant CYCLE_PRECHARGE : integer := 0; -- 0
- constant CYCLE_RAS_START : integer := tRP; -- 3
- constant CYCLE_RAS_NEXT : integer := CYCLE_RAS_START + 1; -- 4
- constant CYCLE_CAS0 : integer := CYCLE_RAS_START + tRCD; -- 3 + tRCD
- constant CYCLE_CAS1 : integer := CYCLE_CAS0 + 1; -- 4 + tRCD
- constant CYCLE_READ0 : integer := CYCLE_CAS0 + to_integer(unsigned(CAS_LATENCY)) + 1; -- 3 + tRCD + CAS_LATENCY
- constant CYCLE_READ1 : integer := CYCLE_READ0 + 1; -- 4 + tRCD + CAS_LATENCY
- constant CYCLE_END : integer := CYCLE_READ1 + 1; -- 9 + tRCD + CAS_LATENCY
- constant CYCLE_RFSH_START : integer := tRP; -- tRP
- constant CYCLE_RFSH_END : integer := CYCLE_RFSH_START + ((tRFC/SDRAM_CLK_FREQ) * 10000000) + tRP + 1; -- tRP (start) + tRFC (min autorefresh time) + tRP (end) in clock ticks.
-
- -- Period in clock cycles between SDRAM refresh cycles. This equates to tREF / SDRAM_ROWS to evenly divide the time, then subtract the length of the refresh period as this is
- -- the time it takes when a refresh starts to completion.
- constant REFRESH_PERIOD : integer := (((tREF * SDRAM_CLK_FREQ ) / SDRAM_ROWS) - (tRFC * 1000)) / 1000;
-
- type BankArray is array(natural range 0 to 3) of std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
-
- -- Cache for holding burst reads to allow for differing speeds of WishBone Master.
- type DataCacheArray is array(natural range 0 to ((2**(MAX_DATACACHE_BITS))-1)) of std_logic_vector(WORD_32BIT_RANGE);
- signal readCache : DataCacheArray;
- attribute ramstyle : string;
- attribute ramstyle of readCache : signal is "logic";
- signal cacheReadAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0);
- signal cacheWriteAddr : unsigned(MAX_DATACACHE_BITS-1 downto 0);
-
- -- SDRAM domain signals.
- signal sdCycle : integer range 0 to 31;
- signal sdDone : std_logic;
- signal sdCmd : std_logic_vector(4 downto 0);
- signal sdRefreshCount : unsigned(11 downto 0);
- signal sdAutoRefresh : std_logic;
- signal sdResetTimer : unsigned(7 downto 0);
- signal sdMuxAddr : std_logic_vector(SDRAM_ROW_BITS-1 downto 0); -- 12+ bit multiplexed address bus
- signal sdDoneLast : std_logic;
- signal sdInResetCounter : unsigned(7 downto 0);
- signal isReady : std_logic;
- signal sdDataOut : std_logic_vector(SDRAM_DATAWIDTH-1 downto 0);
- signal sdDataIn : std_logic_vector(SDRAM_DATAWIDTH-1 downto 0);
- signal sdActiveRow : BankArray;
- signal sdActiveBank : std_logic_vector(1 downto 0);
- signal cpuBank : natural range 0 to 3;
- signal cpuRow : std_logic_vector(SDRAM_ROW_BITS-1 downto 0);
- signal cpuCol : std_logic_vector(SDRAM_COLUMN_BITS-1 downto 0);
- signal sdDQM : std_logic_vector(1 downto 0);
-
- -- CPU domain signals.
- signal cpuBusy : std_logic;
- signal cpuDQM : std_logic_vector(3 downto 0);
- signal cpuDataOut : std_logic_vector(WORD_32BIT_RANGE);
- signal cpuDataIn : std_logic_vector(WORD_32BIT_RANGE);
- signal cpuIsWriting : std_logic;
-
- signal cpuReq : std_logic;
- signal cpuLastEN : std_logic;
- signal sdReqLast : std_logic;
- signal sdAck : std_logic;
- signal cpuDoneAck : std_logic;
-
- type ramArray is array(natural range 0 to SDRAM_COLUMNS) of std_logic_vector(WORD_32BIT_RANGE);
- type ramCtrl is array(0 downto 0) of std_logic_vector(SDRAM_ADDR_BITS downto 0);
-
- shared variable READRAM : ramArray :=
- (
- others => X"00000000"
- );
-
- shared variable WRITERAM : ramArray :=
- (
- others => X"00000000"
- );
- shared variable WRITECTRL : ramCtrl :=
- (
- others => (others => '0')
- );
- shared variable READCTRL : ramCtrl :=
- (
- others => (others => '0')
- );
-
- signal cpuReadFifoBlockAddr : std_logic_vector(SDRAM_ADDR_BITS-1 downto SDRAM_COLUMNS);
- signal sdReadFifoBlockAddr : std_logic_vector(SDRAM_ADDR_BITS-1 downto SDRAM_COLUMNS);
- signal fifoSdWREN : std_logic;
- signal fifoCpuWREN : std_logic;
-
-
-begin
-
- -- Tri-state control of the SDRAM data bus.
--- process(cpuIsWriting, SDRAM_DQ, sdDataOut)
--- begin
--- if (cpuIsWriting = '1') then
--- SDRAM_DQ <= sdDataOut;
--- sdDataIn <= SDRAM_DQ;
--- else
--- SDRAM_DQ <= (others => 'Z');
--- sdDataIn <= SDRAM_DQ;
--- end if;
--- end process;
-
- -- SDRAM Side of dual port RAM.
- -- For Read: sdDataOut <= FIFO(sdFifoAddr)
- -- For WriteL FIFO(sdFifoAddr) <= sdDataIn
--- process(SDRAM_CLK)
--- begin
--- if rising_edge(SDRAM_CLK) then
--- if fifoSdWREN = '1' then
--- FIFO(to_integer(unsigned(sdWriteColumnAddr(SDRAM_COLUMNS-1 downto 0)))) := sdDataIn;
--- sdDataOut(WORD_32BIT_RANGE) <= sdDataIn;
--- else
--- sdDataOut(WORD_32BIT_RANGE) <= FIFO(to_integer(unsigned(sdReadColumnAddr(SDRAM_COLUMN-1 downto 0))));
--- end if;
--- end if;
--- end process;
-
- -- Main FSM for SDRAM control and refresh.
- process(ALL)
- begin
- if (cpuIsWriting = '1') then
- SDRAM_DQ <= sdDataOut;
- else
- SDRAM_DQ <= (others => 'Z');
- end if;
- sdDataIn <= SDRAM_DQ;
-
- if (SDRAM_RST = '1') then
- sdResetTimer <= (others => '0'); -- 0 upto 127
- sdInResetCounter <= (others => '1'); -- 255 downto 0
- sdMuxAddr <= (others => '0');
- sdAutoRefresh <= '0';
- sdRefreshCount <= (others => '0');
- sdActiveBank <= (others => '0');
- sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
- isReady <= '0';
- sdCmd <= CMD_AUTO_REFRESH;
- SDRAM_DQM <= (others => '1');
- sdCycle <= 0;
- sdDone <= '0';
- cacheWriteAddr <= (others => '0');
- sdAck <= '0';
- sdReqLast <= '0';
-
- elsif rising_edge(SDRAM_CLK) then
-
- -- If no specific command given the default is NOP.
- sdCmd <= CMD_NOP;
-
- -- Initialisation on power up or reset. The SDRAM must be given at least 200uS to initialise and a fixed setup pattern applied.
- if (isReady = '0') then
- sdResetTimer <= sdResetTimer + 1;
-
- -- 1uS timer.
- if (sdResetTimer = SDRAM_CLK_FREQ/1000000) then
- sdResetTimer <= (others => '0');
- sdInResetCounter <= sdInResetCounter - 1;
- end if;
-
- -- Every 1uS check for the next init action.
- if (sdResetTimer = 0) then
-
- -- 200uS wait, no action as the SDRAM starts up.
- -- ie. 255 downto 55
-
- -- Precharge all banks
- if(sdInResetCounter = 55) then
- sdCmd <= CMD_PRECHARGE;
- SDRAM_ADDR(10) <= '1';
- end if;
-
- -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
- -- the other.
- if(sdInResetCounter >= 40 and sdInResetCounter <= 48) then
- sdCmd <= CMD_AUTO_REFRESH;
- end if;
-
- -- Load the Mode register with our parameters.
- if(sdInResetCounter = 39) then
- sdCmd <= CMD_LOAD_MODE;
- SDRAM_ADDR <= MODE;
- end if;
-
- -- 8 auto refresh commands as specified in datasheet. The RFS time is 60nS, so using a 1uS timer, issue one after
- -- the other.
- if(sdInResetCounter >= 30 and sdInResetCounter <= 38) then
- sdCmd <= CMD_AUTO_REFRESH;
- end if;
-
- -- SDRAM ready.
- if(sdInResetCounter = 20) then
- isReady <= '1';
- end if;
- end if;
-
- else
-
- -- Counter to the next auto-refresh in sdram clock ticks.
- sdRefreshCount <= sdRefreshCount + 1;
-
- -- Store the CPU request signal state to detect a change.
- sdReqLast <= cpuReq;
-
- -- If the CPU makes an SDRAM request and we arent already processing, acknowledge it.
- -- This mechanism is used to reduce the possibility of metastability issues due to differing clocks.
- if ((sdReqLast = '0' and cpuReq = '1') and sdAck = '0') then
- sdAck <= '1';
- end if;
-
- -- If the CPU completes its request because it detects the SDRAM ACK, remove the ACK signal as it is no longer needed.
- if ((sdReqLast = '1' and cpuReq = '0') and sdAck = '1') then
- sdAck <= '0';
- end if;
-
- -- If the SDRAM has completed its transaction and the CPU has acknowledged it, remove the signals.
- if (sdDone = '1' and cpuDoneAck = '1') then
- sdDone <= '0';
- end if;
-
- -- Auto refresh. On timeout it kicks in so that ROWS auto refreshes are
- -- issued in a tRFC period. Other bus operations are stalled during this period.
- if (sdRefreshCount > REFRESH_PERIOD and sdCycle = 0) then
- sdAutoRefresh <= '1';
- sdRefreshCount <= (others => '0');
- sdCmd <= CMD_PRECHARGE;
- SDRAM_ADDR(10) <= '1';
- sdActiveBank <= (others => '0');
- sdActiveRow <= ((others => '0'), (others => '0'), (others => '0'), (others => '0'));
-
- -- In auto refresh period.
- elsif (sdAutoRefresh = '1') then
-
- -- while the cycle is active count.
- sdCycle <= sdCycle + 1;
- case (sdCycle) is
- when CYCLE_RFSH_START =>
- sdCmd <= CMD_AUTO_REFRESH;
-
- when CYCLE_RFSH_END =>
- -- reset the count.
- sdAutoRefresh <= '0';
- sdCycle <= 0;
-
- when others =>
- end case;
-
- -- If we are not acknowledging a CPU request (and signals to stabilize and latch), run the FSM to refresh or service a request.
- elsif sdAck = '0' then
--- if sdAck = '0' then
-
- if ((cpuBusy = '1' and sdCycle = 0) or sdCycle /= 0) then -- or (sdCycle = 0 and CS = '1')) then
-
- -- while the cycle is active count.
- sdCycle <= sdCycle + 1;
- case (sdCycle) is
-
- when CYCLE_PRECHARGE =>
- -- If the bank is not open then no need to precharge, move onto RAS.
- if (sdActiveBank(cpuBank) = '0') then
- sdCycle <= CYCLE_RAS_START;
-
- -- If the requested row is already active, go to CAS for immediate access to this row.
- elsif (sdActiveRow(cpuBank) = cpuRow) then
- sdCycle <= CYCLE_CAS0;
-
- -- Otherwise we close out the open bank by issuing a PRECHARGE.
- else
- sdCmd <= CMD_PRECHARGE;
- SDRAM_ADDR(10) <= '0';
- SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length));
- sdActiveBank(cpuBank) <= '0'; -- Store flag to indicate which bank is being made active.
- end if;
-
- -- Open the requested row.
- when CYCLE_RAS_START =>
- sdCmd <= CMD_ACTIVE;
- SDRAM_ADDR <= cpuRow; -- Addr presented to SDRAM as row address.
- SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Addr presented to SDRAM as bank select.
- sdActiveRow(cpuBank) <= cpuRow; -- Store number of row being made active
- sdActiveBank(cpuBank) <= '1'; -- Store flag to indicate which bank is being made active.
-
- when CYCLE_RAS_NEXT =>
- SDRAM_DQM <= "11"; -- Set DQ to tri--state.
-
- -- this is the first CAS cycle
- when CYCLE_CAS0 =>
- -- Process on a 32bit boundary, this core is originally intended for a a 16bit chip so we need 2 accesses for a 32bit alignment, for a 32bit chip, remove CAS1 (TODO: Auto enable logic based on datawidth).
- SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '0')), SDRAM_ROW_BITS)); -- CAS address = Address accessing first 16bit location within the 32bit external alignment with no auto precharge
- -- SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Ensure bank is the correct one opened.
-
- SDRAM_DQM <= not cpuDQM(3 downto 2);
- sdDataOut <= cpuDataIn((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH); -- Assign corresponding data to the SDRAM databus.
- -- If writing, setup for a write with preset mask.
- if (cpuIsWriting = '1') then
- sdCmd <= CMD_WRITE;
- else
- -- Setup for a read.
- sdCmd <= CMD_READ;
- SDRAM_DQM <= "00"; -- For reads dont mask the data output.
- end if;
-
- when CYCLE_CAS1 =>
- SDRAM_ADDR <= std_logic_vector(to_unsigned(to_integer(unsigned(cpuCol(SDRAM_COLUMN_BITS-1 downto 1) & '1')), SDRAM_ROW_BITS)); -- CAS address = Next address accessing second 16bit location within the 32bit external alignment with no auto precharge
- -- SDRAM_BA <= std_logic_vector(to_unsigned(cpuBank, SDRAM_BA'length)); -- Ensure bank is the correct one opened.
-
- SDRAM_DQM <= not cpuDQM(1 downto 0);
- sdDataOut <= cpuDataIn(SDRAM_DATAWIDTH-1 downto 0);
- -- If writing, setup for a write with preset mask.
- if (cpuIsWriting = '1') then
- sdCmd <= CMD_WRITE;
- -- sdDone <= '1'; --not sdDone;
- sdCycle <= CYCLE_END;
- else
- -- Setup for a read, change to write if flag set.
- sdCmd <= CMD_READ;
- SDRAM_DQM <= "00"; -- For reads dont mask the data output.
- end if;
-
- -- Data is available CAS Latency clocks after the read request.
- when CYCLE_READ0 =>
- -- If writing, then we are complete, exit else read the first word.
- if (cpuIsWriting = '1') then
- sdCycle <= CYCLE_END;
- else
- cpuDataOut((SDRAM_DATAWIDTH*2)-1 downto SDRAM_DATAWIDTH) <= sdDataIn;
- end if;
-
- when CYCLE_READ1 =>
- -- If writing, then we are complete, exit else read the first word.
- if (cpuIsWriting = '1') then
- sdCycle <= CYCLE_END;
- else
- cpuDataOut(SDRAM_DATAWIDTH-1 downto 0) <= sdDataIn;
- end if;
-
- when CYCLE_END =>
- sdDone <= '1'; --not sdDone;
- sdCycle <= 0;
-
- -- Other states are wait states, waiting for the correct time slot for SDRAM access.
- when others =>
- end case;
- else
- sdCycle <= 0;
- end if;
- end if;
- end if;
- end if;
- end process;
-
- -- CPU Side of dual port RAM.
- -- For Read: cpuDataOut <= FIFO(cpuFifoAddr)
- -- For Write: FIFO(cpuFifoAddr) <= cpuDataIn
--- process(CLK)
--- begin
--- if rising_edge(CLK) then
--- if fifoCpuWREN = '1' then
--- FIFO(to_integer(unsigned(cpuWriteColumnAddr(SDRAM_COLUMNS-1 downto 0)))) := cpuDataIn;
--- cpuDataOut(WORD_32BIT_RANGE) <= cpuDataIn;
--- else
--- cpuDataOut(WORD_32BIT_RANGE) <= FIFO(to_integer(unsigned(cpuReadColumnAddr(SDRAM_COLUMN-1 downto 0))));
--- end if;
--- end if;
--- end process;
-
- -- CPU/BUS side logic. When the CPU initiates a transaction, capture the signals and the captured values are used within the SDRAM domain. This is to prevent
- -- any changes CPU side or differing signal lengths due to CPU architecture or clock being propogated into the SDRAM domain. The CPU only needs to know
- -- when the transation is complete and data read.
- --
- process(ALL)
- begin
- if (RESET = '1') then
- sdDoneLast <= '0';
- cpuBusy <= '0';
- cpuBank <= 0;
- cpuRow <= (others => '0');
- cpuCol <= (others => '0');
- cpuDQM <= (others => '1');
- cpuDoneAck <= '0';
- cpuReq <= '0';
- cpuLastEN <= '0';
-
- -- If the SDRAM isnt ready, we can only wait.
- elsif isReady = '0' then
-
- elsif rising_edge(CLK) then
-
- -- Preserve current enable state to detect activation.
- cpuLastEN <= RDEN or WREN;
-
- -- Detect a Chip Select state change signalling access.
- if cpuLastEN = '0' and (RDEN = '1' or WREN = '1') then
- cpuBusy <= '1';
- cpuIsWriting <= WREN;
- cpuBank <= to_integer(unsigned(ADDR(SDRAM_ADDR_BITS downto SDRAM_ARRAY_BITS+1)));
- cpuRow <= std_logic_vector(to_unsigned(to_integer(unsigned(ADDR(SDRAM_ARRAY_BITS downto SDRAM_COLUMN_BITS+1))), SDRAM_ROW_BITS));
- cpuCol <= ADDR(SDRAM_COLUMN_BITS downto 2) & '0';
- cpuReq <= '1';
-
- -- Preset the write selects according to the CPU signals. Let Quartus optimize as easier to read seeing all mask values.
- if(WRITE_BYTE = '1') then
- case ADDR(1 downto 0) is
- when "00" => cpuDQM <= "1000";
- cpuDataIn <= DATA_IN(7 downto 0) & X"000000";
- when "01" => cpuDQM <= "0100";
- cpuDataIn <= X"00" & DATA_IN(7 downto 0) & X"0000";
- when "10" => cpuDQM <= "0010";
- cpuDataIn <= X"0000" & DATA_IN(7 downto 0) & X"00";
- when "11" => cpuDQM <= "0001";
- cpuDataIn <= X"000000" & DATA_IN(7 downto 0);
- when others =>
- end case;
-
- elsif(WRITE_HWORD = '1') then
-
- case ADDR(1) is
- when '0' => cpuDQM <= "1100";
- cpuDataIn <= DATA_IN(15 downto 0) & X"0000";
- when '1' => cpuDQM <= "0011";
- cpuDataIn <= X"0000" & DATA_IN(15 downto 0);
- end case;
-
- else
- -- Reads are always 32bit wide and if no part word signal is asserted, writes are 32bit.
- cpuDataIn <= DATA_IN(31 downto 0);
- cpuDQM <= "1111";
- end if;
- end if;
-
- if cpuReq = '1' and sdAck = '1' then
- cpuReq <= '0';
- end if;
-
- -- Note SDRAM activity via a previous/last signal.
- sdDoneLast <= sdDone;
-
- -- If there has been a change in the SDRAM done activity reset the signals as initiated transaction is complete.
- if (sdDoneLast = '0' and sdDone = '1') then
- cpuDoneAck <= '1';
- end if;
-
- if (sdDoneLast = '1' and sdDone = '0' and cpuDoneAck = '1') then
- cpuDoneAck <= '0';
- cpuBusy <= '0';
- end if;
-
- end if;
- end process;
-
- -- Assign stored data to the CPU bus to be read.
- DATA_OUT <= cpuDataOut;
-
- -- drive control signals according to current command
- SDRAM_CKE <= sdCmd(4);
- SDRAM_CS_n <= sdCmd(3);
- SDRAM_RAS_n <= sdCmd(2);
- SDRAM_CAS_n <= sdCmd(1);
- SDRAM_WE_n <= sdCmd(0);
--- SDRAM_DQM <= sdDQM;
- -- SDRAM_ADDR <= sdMuxAddr;
-
- -- System bus control signals.
- BUSY <= '1' when (cpuLastEN = '0' and (RDEN = '1' or WREN = '1')) else cpuBusy;
- SDRAM_READY <= isReady;
-
-end Structure;
diff --git a/zpu/build/simulation/modelsim/QMV_zpu.sft b/zpu/build/simulation/modelsim/QMV_zpu.sft
deleted file mode 100644
index 0c5034b..0000000
--- a/zpu/build/simulation/modelsim/QMV_zpu.sft
+++ /dev/null
@@ -1 +0,0 @@
-set tool_name "ModelSim-Altera (VHDL)"
diff --git a/zpu/build/simulation/modelsim/QMV_zpu.vho b/zpu/build/simulation/modelsim/QMV_zpu.vho
deleted file mode 100644
index 18bc2d7..0000000
--- a/zpu/build/simulation/modelsim/QMV_zpu.vho
+++ /dev/null
@@ -1,465015 +0,0 @@
--- Copyright (C) 2017 Intel Corporation. All rights reserved.
--- Your use of Intel Corporation's design tools, logic functions
--- and other software and tools, and its AMPP partner logic
--- functions, and any output files from any of the foregoing
--- (including device programming or simulation files), and any
--- associated documentation or information are expressly subject
--- to the terms and conditions of the Intel Program License
--- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel FPGA IP License Agreement, or other applicable license
--- agreement, including, without limitation, that your use is for
--- the sole purpose of programming logic devices manufactured by
--- Intel and sold by Intel or its authorized distributors. Please
--- refer to the applicable agreement for further details.
-
--- VENDOR "Altera"
--- PROGRAM "Quartus Prime"
--- VERSION "Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition"
-
--- DATE "03/05/2020 08:44:57"
-
---
--- Device: Altera 5CEFA2F23C8 Package FBGA484
---
-
---
--- This VHDL file should be used for ModelSim-Altera (VHDL) only
---
-
-LIBRARY ALTERA;
-LIBRARY ALTERA_LNSIM;
-LIBRARY CYCLONEV;
-LIBRARY IEEE;
-USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
-USE ALTERA_LNSIM.ALTERA_LNSIM_COMPONENTS.ALL;
-USE CYCLONEV.CYCLONEV_COMPONENTS.ALL;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY QMV_zpu IS
- PORT (
- CLOCK_50 : IN std_logic;
- LEDR : OUT std_logic;
- KEY : IN std_logic;
- SDCARD_MISO : IN std_logic_vector(0 DOWNTO 0);
- SDCARD_MOSI : OUT std_logic_vector(0 DOWNTO 0);
- SDCARD_CLK : OUT std_logic_vector(0 DOWNTO 0);
- SDCARD_CS : OUT std_logic_vector(0 DOWNTO 0);
- UART_RX_0 : IN std_logic;
- UART_TX_0 : OUT std_logic;
- UART_RX_1 : IN std_logic;
- UART_TX_1 : OUT std_logic;
- SDRAM_CLK : OUT std_logic;
- SDRAM_CKE : OUT std_logic;
- SDRAM_DQ : INOUT std_logic_vector(15 DOWNTO 0);
- SDRAM_ADDR : OUT std_logic_vector(11 DOWNTO 0);
- SDRAM_DQM : OUT std_logic_vector(1 DOWNTO 0);
- SDRAM_BA : OUT std_logic_vector(1 DOWNTO 0);
- SDRAM_CS : OUT std_logic;
- SDRAM_WE : OUT std_logic;
- SDRAM_RAS : OUT std_logic;
- SDRAM_CAS : OUT std_logic
- );
-END QMV_zpu;
-
--- Design Ports Information
--- UART_TX_1 => Location: PIN_AB18, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_CLK => Location: PIN_AB11, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- UART_TX_0 => Location: PIN_AA15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDCARD_MOSI[0] => Location: PIN_AA18, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDCARD_CLK[0] => Location: PIN_AA20, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDCARD_CS[0] => Location: PIN_Y20, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[0] => Location: PIN_P8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[1] => Location: PIN_P7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[2] => Location: PIN_N8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[3] => Location: PIN_N6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[4] => Location: PIN_U6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[5] => Location: PIN_U7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[6] => Location: PIN_V6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[7] => Location: PIN_U8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[8] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[9] => Location: PIN_W8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[10] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_ADDR[11] => Location: PIN_T9, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQM[0] => Location: PIN_AB7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQM[1] => Location: PIN_V10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_BA[0] => Location: PIN_T7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_BA[1] => Location: PIN_P9, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_WE => Location: PIN_W9, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_RAS => Location: PIN_AB6, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_CAS => Location: PIN_AA7, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- LEDR => Location: PIN_D17, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_CKE => Location: PIN_V9, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_CS => Location: PIN_AB5, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[12] => Location: PIN_R11, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[13] => Location: PIN_U12, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[14] => Location: PIN_R12, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[15] => Location: PIN_P12, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[0] => Location: PIN_AA12, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[1] => Location: PIN_Y11, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[2] => Location: PIN_AA10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[3] => Location: PIN_AB10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[4] => Location: PIN_Y10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[5] => Location: PIN_AA9, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[6] => Location: PIN_AB8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[7] => Location: PIN_AA8, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[8] => Location: PIN_U10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[9] => Location: PIN_T10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[10] => Location: PIN_U11, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- SDRAM_DQ[11] => Location: PIN_R10, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA
--- CLOCK_50 => Location: PIN_M9, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- KEY => Location: PIN_AB13, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- SDCARD_MISO[0] => Location: PIN_Y17, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- UART_RX_0 => Location: PIN_AA14, I/O Standard: 3.3-V LVTTL, Current Strength: Default
--- UART_RX_1 => Location: PIN_Y15, I/O Standard: 3.3-V LVTTL, Current Strength: Default
-
-
-ARCHITECTURE structure OF QMV_zpu IS
-SIGNAL gnd : std_logic := '0';
-SIGNAL vcc : std_logic := '1';
-SIGNAL unknown : std_logic := 'X';
-SIGNAL devoe : std_logic := '1';
-SIGNAL devclrn : std_logic := '1';
-SIGNAL devpor : std_logic := '1';
-SIGNAL ww_devoe : std_logic;
-SIGNAL ww_devclrn : std_logic;
-SIGNAL ww_devpor : std_logic;
-SIGNAL ww_CLOCK_50 : std_logic;
-SIGNAL ww_LEDR : std_logic;
-SIGNAL ww_KEY : std_logic;
-SIGNAL ww_SDCARD_MISO : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SDCARD_MOSI : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SDCARD_CLK : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_SDCARD_CS : std_logic_vector(0 DOWNTO 0);
-SIGNAL ww_UART_RX_0 : std_logic;
-SIGNAL ww_UART_TX_0 : std_logic;
-SIGNAL ww_UART_RX_1 : std_logic;
-SIGNAL ww_UART_TX_1 : std_logic;
-SIGNAL ww_SDRAM_CLK : std_logic;
-SIGNAL ww_SDRAM_CKE : std_logic;
-SIGNAL ww_SDRAM_ADDR : std_logic_vector(11 DOWNTO 0);
-SIGNAL ww_SDRAM_DQM : std_logic_vector(1 DOWNTO 0);
-SIGNAL ww_SDRAM_BA : std_logic_vector(1 DOWNTO 0);
-SIGNAL ww_SDRAM_CS : std_logic;
-SIGNAL ww_SDRAM_WE : std_logic;
-SIGNAL ww_SDRAM_RAS : std_logic;
-SIGNAL ww_SDRAM_CAS : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(39 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(39 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ : std_logic_vector(12 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ACLR_bus\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_CLK_bus\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ENA_bus\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AX_bus\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AY_bus\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_ACLR_bus\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_CLK_bus\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_ENA_bus\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_AX_bus\ : std_logic_vector(13 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_AY_bus\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_BX_bus\ : std_logic_vector(13 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_BY_bus\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(39 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(39 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ : std_logic_vector(39 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\ : std_logic_vector(39 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_CLKIN_bus\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_MHI_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_SHIFTEN_bus\ : std_logic_vector(8 DOWNTO 0);
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER_VCO0PH_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER_VCO0PH_bus\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~40\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~41\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~44\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~45\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~48\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~49\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~52\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~53\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~56\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~57\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~60\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~61\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~63\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~64\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~65\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~67\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~68\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~69\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~71\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~387\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~388\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~389\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~390\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~391\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~392\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~393\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~394\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~395\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~396\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~397\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~398\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~399\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~400\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~401\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~402\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~403\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~404\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~405\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~406\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~407\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~408\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~409\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~410\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~411\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~412\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~413\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~414\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~415\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~416\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~417\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~418\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~419\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~420\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~421\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~422\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~423\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~424\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~425\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~426\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~427\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~428\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~429\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~430\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~431\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~432\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~433\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~434\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~435\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~436\ : std_logic;
-SIGNAL \CLOCK_50~input_o\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_EXTSWITCHBUF\ : std_logic;
-SIGNAL \KEY~input_o\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_CLKOUT\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI2\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI3\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI4\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI5\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI6\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI7\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_UP\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI1\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTENM\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI0\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|fb_clkin\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_CNTNEN\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTEN0\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_TCLK\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH0\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH1\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH2\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH3\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH4\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH5\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH6\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH7\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIGSHIFTEN2\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\ : std_logic;
-SIGNAL \UART_RX_1~input_o\ : std_logic;
-SIGNAL \UART_RX_0~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~3_combout\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|wire_generic_pll1_locked\ : std_logic;
-SIGNAL \reset~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~42\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~46\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal11~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~50\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER_RX~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~54\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~58\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~62\ : std_logic;
-SIGNAL \myVirtualToplevel|Add1~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal11~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[0]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~62_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[1]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[3]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[4]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[5]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[6]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[8]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~58\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[9]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~54\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[10]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~42\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[11]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[12]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~50\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[13]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal12~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~46\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[14]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add2~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_COUNTER[15]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_n~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_n~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RESET_n~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM990\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_OTERM3311\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~104_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~105_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_OTERM3260\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_OTERM3263\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_OTERM3287\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_OTERM3284\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_OTERM3272\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_OTERM3269\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_OTERM3266\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~100_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~99_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divStart~1_combout\ : std_logic;
-SIGNAL \~GND~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_OTERM3299\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_OTERM3296\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_OTERM3290\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_OTERM3323\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_OTERM3308\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_OTERM3305\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_OTERM1905\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_OTERM1903\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_OTERM1901\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_OTERM1899\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_OTERM1897\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_OTERM1895\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_OTERM1893\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_OTERM1891\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_OTERM1889\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_OTERM1887\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_OTERM1885\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_OTERM1883\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_OTERM1881\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_OTERM1879\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_OTERM1877\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_OTERM1871\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_OTERM1867\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_OTERM1865\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_OTERM1863\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_OTERM1947\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_OTERM1945\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_OTERM1943\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_OTERM1939\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_OTERM1937\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_OTERM1935\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_OTERM1933\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_OTERM1931\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_OTERM1929\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_OTERM1927\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_OTERM1925\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_OTERM1923\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_OTERM1921\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_OTERM1919\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_OTERM1917\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_OTERM1915\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_OTERM1913\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_OTERM1911\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_OTERM1909\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~11\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_OTERM1907\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_OTERM2626\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_OTERM2629\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_OTERM2632\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_OTERM2635\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_OTERM2638\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_OTERM2641\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_OTERM2644\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_OTERM2647\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_OTERM2650\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_OTERM2653\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_OTERM2656\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_OTERM2659\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_OTERM2662\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_OTERM2668\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_OTERM2671\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_OTERM2674\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_OTERM2677\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~95\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_OTERM2680\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~83\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add8~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~67\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add0~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370_BDD12371\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_OTERM2683\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470_BDD12471\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690_BDD12691\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_OTERM1875\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_OTERM1873\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706_BDD12707\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489_BDD8490\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_BDD8960\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_DATA_WRITE[7]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ : std_logic;
-SIGNAL \SDCARD_MISO[0]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector15~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector14~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector14~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector15~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_RESET_TIMER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_RESET_TIMER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_RESET_TIMER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_RESET_TIMER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add0~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_RESET_TIMER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal8~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector15~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector18~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector15~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector15~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector15~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_RD[0]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~38\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~26\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~6\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM782\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644_BDD12645\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_OTERM3342\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux74~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ : std_logic;
-SIGNAL \SDRAM_DQ[0]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_OTERM3178\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_OTERM3050\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_OTERM2986\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_OTERM3114\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_OTERM2794\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_OTERM2858\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_OTERM2730\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_OTERM2922\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_OTERM2926\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_OTERM2734\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_OTERM2862\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_OTERM2798\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_OTERM3118\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_OTERM3182\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_OTERM2990\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_OTERM3054\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][15]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux68~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1409\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM41\ : std_logic;
-SIGNAL \SDRAM_DQ[7]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ : std_logic;
-SIGNAL \SDRAM_DQ[13]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \SDRAM_DQ[2]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM922\ : std_logic;
-SIGNAL \SDRAM_DQ[10]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM23\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1177\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM553\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM551\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux75~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624_BDD12625\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628_BDD12629\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM5\ : std_logic;
-SIGNAL \SDRAM_DQ[1]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_ENABLE_FIFO~0_combout\ : std_logic;
-SIGNAL \SDRAM_DQ[5]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157_BDD9158\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_BDD9162\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159_BDD9160\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1533\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437_BDD8438\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435_BDD8436\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1543\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1385\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1567\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1259\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1427\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803_BDD8804\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1283\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791_BDD8792\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1477\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_OTERM3048\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_OTERM3176\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_OTERM3112\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_OTERM2984\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_OTERM2920\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_OTERM2792\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_OTERM2728\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_OTERM2856\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux72~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ : std_logic;
-SIGNAL \SDRAM_DQ[3]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM35\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_OTERM3329\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_OTERM2980\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_OTERM3172\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_OTERM3044\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_OTERM3108\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_OTERM2852\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_OTERM2724\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_OTERM2916\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_OTERM2788\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux70~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|INT_ENABLE[16]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Mux0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_TICK_HALT~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_TICK_HALT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add3~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal13~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~13_sumout\ : std_logic;
-SIGNAL \SDRAM_DQ[6]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM45\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal4~0_RESYN12606_BDD12607\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1_CS~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_ENABLE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_ENABLE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_RESET~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_RESET~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RXD_SYNC2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RXD_SYNC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Selector4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Selector5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Selector6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Selector7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Selector8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Selector9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Selector10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Selector11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Selector12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.bits~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.bits~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.start~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.start~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.idle~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.idle~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_OTERM2722\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_OTERM2850\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_OTERM2786\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_OTERM2914\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_OTERM2978\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_OTERM3042\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_OTERM3106\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_OTERM3170\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_OTERM3174\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_OTERM3110\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_OTERM2982\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_OTERM3046\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_OTERM2726\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_OTERM2790\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_OTERM2918\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_OTERM2854\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~54\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~34\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~38\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~42\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~46\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~58\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~62\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add1~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.stop~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.stop~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_STATE.stop~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_INTR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_ENABLE_FIFO~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA_READY~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA_READY~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA_READY~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|process_3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal2~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add3~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add2~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal3~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add4~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal2~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal3~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_BUFFER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~24_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~17_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[6]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_ENABLE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_RESET~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_RESET~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RXD_SYNC2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RXD_SYNC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Selector6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~54\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~34\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~38\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~42\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~46\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~58\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~62\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add1~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Selector7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Selector8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Selector9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Selector10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Selector11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Selector12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_STATE.stop~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_STATE.stop~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_STATE.idle~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_STATE.idle~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_STATE.start~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_STATE.start~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_STATE.bits~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_STATE.bits~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Selector4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Selector5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_INTR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add4~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal2~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal2~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA_READY~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA_READY~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA_READY~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|process_3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add3~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add2~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal3~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal3~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~24_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~17_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[6]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[0]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal36~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTR0_CS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal36~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~94\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~90\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~86\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~82\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~78\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~74\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~110\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~106\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~70\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~66\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~46\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~42\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~62\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~58\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~54\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~102\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~50\ : std_logic;
-SIGNAL \myVirtualToplevel|Add18~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal35~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal35~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal35~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal35~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal35~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal35~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal35~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal35~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~42\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~46\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add19~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~70\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~66\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~62\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal34~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~58\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~54\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~50\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~46\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~42\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add16~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal34~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal34~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal34~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal34~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~125_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~126\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~90\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~86\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~82\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~50\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~54\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~90\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~94\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~86\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~82\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~50\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~54\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~70\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~74\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~78\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~58\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~62\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~66\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~42\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~46\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1615\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|LessThan0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[1]~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_OTERM3217\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux81~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125_BDD9126\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[0]~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~20_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[2]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add5~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add7~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~66\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~70\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~62\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~58\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal33~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~46\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~50\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~54\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~42\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal33~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal33~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal33~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~70\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~66\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~62\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal32~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~58\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~54\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~50\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~46\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~42\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add14~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal32~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal32~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal32~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal32~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add15~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~73_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[5]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[0]_OTERM1629\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~42\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[1]_OTERM1627\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|process_1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|process_1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add9~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|process_1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|process_1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|process_1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|process_1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~46\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[2]_OTERM1755\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~42_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~37\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~32\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~20_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[2]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM31\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_OTERM3214\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_OTERM3211\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_OTERM3223\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_OTERM3208\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_OTERM3205\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_OTERM3202\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1313\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1319\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1323\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1325\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1355\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1343\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1341\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1347\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1349\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1335\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1337\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM603\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM599\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM595\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM597\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[30]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1074\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[17]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[17]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[17]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_RESET~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_RESET~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_ENABLE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_OVERRUN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_ENABLE_FIFO~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal5~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add7~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal5~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal5~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal5~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER[16]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~62\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~50\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~54\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_OTERM2774\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_OTERM2902\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_OTERM2838\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_OTERM2710\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_OTERM3158\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_OTERM3030\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_OTERM2966\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_OTERM3094\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~38\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_OTERM3028\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_OTERM2964\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_OTERM3156\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_OTERM3092\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_OTERM2836\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_OTERM2708\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_OTERM2772\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_OTERM2900\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~34\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM918\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux92~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux268~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux268~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[3]_OTERM1757\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[4]_OTERM1773\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[4]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[4]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~22_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[4]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~26_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_INTR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_INTR~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add5~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_INTR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_INTR~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_INTR~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_INTR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_INTR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~26_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_INTR~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_INTR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add5~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_INTR~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_INTR~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_INTR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~22_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[4]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[4]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739_BDD8740\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~58\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~46\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~42\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~30\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~26\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~38\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~22\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~62\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~18\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~34\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~14\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~10\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~6\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~2\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~54\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add0~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescaled_tick~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER_REG_REQ~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|process_0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER_REG_REQ~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~86\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~98\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~102\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~70\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~74\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~78\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~90\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~94\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~113_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~114\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~10\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~14\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~34\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~82\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~106\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~110\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~42\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~46\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~66\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~117_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~118\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~121_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~122\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~125_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~126\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~26\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM914\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[22]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_ENABLE_FIFO~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_RESET~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_RESET~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_ENABLE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_OVERRUN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add6~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add7~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal5~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal5~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~38\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~50\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~54\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux83~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux86~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~18_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[0]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_EMPTY_V~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_EMPTY_V~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~18_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[0]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~89_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~91_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~36_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~93_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[26]~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[24]~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~70\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~74\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~78\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~58\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~62\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~66\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~42\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~46\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~121_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_OTERM3036\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_OTERM3164\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_OTERM2972\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_OTERM3100\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_OTERM2716\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_OTERM2844\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_OTERM2908\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_OTERM2780\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[24]~87_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux87~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][24]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM15\ : std_logic;
-SIGNAL \SDRAM_DQ[8]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~122\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~110\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~113_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~114\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~117_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993_BDD8994\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_OTERM1841\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_OTERM1839\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_OTERM3160\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_OTERM3096\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_OTERM2968\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_OTERM3032\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_OTERM2712\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_OTERM2840\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_OTERM2904\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_OTERM2776\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_OTERM2704\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_OTERM2896\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_OTERM2832\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_OTERM2768\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_OTERM3088\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_OTERM3024\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_OTERM3152\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_OTERM2960\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux88~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][23]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[22]_OTERM1263\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~35_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[23]_OTERM1307\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[23]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_OTERM1829\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_OTERM1827\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678_BDD12679\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670_BDD12671\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778_BDD12779\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669_BDD8670\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~117_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677_BDD8678\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466_BDD13467\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_BDD9276\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~137_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~142_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025_BDD9026\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027_BDD9028\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029_BDD9030\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8685_BDD8686\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8683_BDD8684\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]_OTERM1709\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~91\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]_OTERM1711\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~95\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[2]_OTERM1713\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~87\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[3]_OTERM1715\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~83\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[4]_OTERM1717\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[5]_OTERM1719\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]_OTERM1721\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~71\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]_OTERM1723\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~75\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[8]_OTERM1725\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~79\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]_OTERM1727\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[10]_OTERM1729\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~63\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[11]_OTERM1731\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~67\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[12]_OTERM1737\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~35\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[13]_OTERM1631\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~39\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[14]_OTERM1733\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[15]_OTERM1735\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]_OTERM1753\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[17]_OTERM1743\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~23\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]_OTERM1741\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~27\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[19]_OTERM1739\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~31\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[20]_OTERM1747\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~15\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]_OTERM1751\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[22]_OTERM1749\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~11\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[23]_OTERM1745\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~19\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~125_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[24]_OTERM1693\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~126\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~127\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~121_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[25]_OTERM1695\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~122\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~123\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[26]_OTERM1697\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~110\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~111\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~117_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[27]_OTERM1699\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~118\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~119\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~113_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[28]_OTERM1701\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~114\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~115\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[29]_OTERM1703\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~102\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~103\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]_OTERM1705\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM792\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM788\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM197\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM169\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM199\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM171\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM201\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM173\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM203\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM175\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM205\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM177\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM207\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM179\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM209\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM181\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM183\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM211\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM185\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM213\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM215\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM187\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM217\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM189\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM219\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM191\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~359\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~363\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~351\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~343\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~347\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~355\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~720\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~716\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~712\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~708\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~724\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~728\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~147_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277_BDD9278\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][28]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[28]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM91\ : std_logic;
-SIGNAL \SDRAM_DQ[12]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM93\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~79_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[28]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~366_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector298~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[27]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[3]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]_OTERM2950\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[28]_OTERM3078\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[28]_OTERM3014\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[28]_OTERM3142\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[28]_OTERM2886\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[28]_OTERM2694\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[28]_OTERM2822\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[28]_OTERM2758\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector297~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[28]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[4]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM768\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[29]_OTERM3140\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[29]_OTERM2948\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[29]_OTERM3012\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[29]_OTERM3076\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[29]_OTERM2820\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[29]_OTERM2692\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[29]_OTERM2756\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[29]_OTERM2884\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector296~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM770\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[5]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[30]_OTERM3074\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[30]_OTERM3138\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[30]_OTERM2946\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[30]_OTERM3010\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[30]_OTERM2818\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[30]_OTERM2754\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[30]_OTERM2882\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[30]_OTERM2690\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector295~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[30]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[6]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[31]_OTERM3086\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[31]_OTERM3150\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[31]_OTERM3022\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[31]_OTERM2958\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[31]_OTERM2702\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[31]_OTERM2766\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[31]_OTERM2830\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[31]_OTERM2894\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector294~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM766\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM764\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[7]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~367_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~371_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~370_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~369_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~368_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]_OTERM1823\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]_OTERM1825\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~387_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~386_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~384_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~385_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~380_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~381_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_RESYN8957_BDD8958\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8749_BDD8750\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM800\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[20]_OTERM1213\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745_BDD8746\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337_BDD9338\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594_BDD12595\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592_BDD12593\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335_BDD9336\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_BDD9334\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_BDD8966\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~383_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967_BDD8968\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~242_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~243_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~235_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~234_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~239_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~230_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~231_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~238_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]_OTERM1843\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]_OTERM1845\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~223_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~222_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~218_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~219_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~227_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~244_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~228_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~224_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~240_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~237_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~233_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~221_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~217_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~241_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~225_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~245_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~229_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~232_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~220_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~236_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~216_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~91\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~95\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~87\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~83\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~71\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~75\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~79\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~63\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~67\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~35\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~39\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[16]_OTERM1239\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~287_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~278_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~279_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~286_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~291_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~298_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~299_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~290_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]_OTERM1849\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~283_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]_OTERM1847\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~282_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~295_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~303_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~294_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~302_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~280_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~276_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~292_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~281_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~293_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~289_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~305_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~301_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~285_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~300_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~304_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~288_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~284_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1183\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1181\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1185\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~47_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~319_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~311_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~327_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~335_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~310_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~326_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~318_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~435_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~334_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~323_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~331_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~315_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~307_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~322_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~314_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~330_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~306_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~316_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~312_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~313_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~317_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~320_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~325_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~321_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~308_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]_OTERM1833\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]_OTERM1831\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~329_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~332_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~333_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~328_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8709_BDD8710\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8705_BDD8706\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111_BDD9112\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_BDD8708\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711_BDD8712\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8979_BDD8980\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345_BDD9346\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349_BDD9350\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~39_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347_BDD9348\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_BDD8984\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_RESYN9251_BDD9252\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1187\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1189\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[12]_OTERM1241\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8977_BDD8978\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975_BDD8976\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~418_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~411_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~419_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~410_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~396_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~405_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~397_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~404_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~413_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~421_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~412_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~420_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~402_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~403_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]_OTERM1821\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]_OTERM1819\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~406_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~408_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~424_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~422_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~399_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~415_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~417_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~401_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~423_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~407_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~409_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~425_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~398_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~414_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~416_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~400_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770_BDD12771\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~66_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1231\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1229\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_OTERM1249\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~71_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~165_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~80_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[7]_OTERM1247\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~75_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[6]_OTERM1243\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[5]_OTERM1245\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~81_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~79_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector350~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector347~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~110\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~106\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~102\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~98\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~113_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~114\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~118\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~121_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8679_BDD8680\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~128_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~117_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8681_BDD8682\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM900\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[29]_OTERM970\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~135_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~157_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~136_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~117_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667_BDD8668\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~112_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~113_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~124_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~121_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263_BDD9264\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267_BDD9268\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM798\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~122_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269_BDD9270\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[28]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~106\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~107\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[58]_OTERM1685\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[57]_OTERM1683\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[59]_OTERM1687\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[60]_OTERM1689\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[61]_OTERM1691\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~707_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8649_BDD8650\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8651_BDD8652\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8647_BDD8648\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997_BDD8998\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999_BDD9000\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[27]_OTERM2952\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[27]_OTERM3016\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[27]_OTERM3144\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[27]_OTERM3080\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[27]_OTERM2888\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[27]_OTERM2824\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[27]_OTERM2696\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[27]_OTERM2760\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[27]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~118\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~94\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[29]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~98\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[30]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~102\ : std_logic;
-SIGNAL \myVirtualToplevel|Add17~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][31]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[31]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM79\ : std_logic;
-SIGNAL \SDRAM_DQ[15]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM81\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[31]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~133\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~136_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~122\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~123\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~125_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~122\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~125_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM167\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM195\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~732\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9033_BDD9034\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]_OTERM1707\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM523\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_68\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM517\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_64\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM515\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM521\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM519\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9031_BDD9032\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~122\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~125_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772_BDD12773\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802_BDD12803\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011_BDD9012\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_RESYN12546_BDD12547\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~149_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_RESYN8655_BDD8656\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~150_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~96_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~91_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~97_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774_BDD12775\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003_BDD9004\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776_BDD12777\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[26]_OTERM904\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~98_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~99_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~100_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[26]_OTERM2954\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[26]_OTERM3146\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]_OTERM3018\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]_OTERM3082\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[26]_OTERM2698\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[26]_OTERM2762\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[26]_OTERM2890\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[26]_OTERM2826\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector299~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM762\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM760\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[2]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~337_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674_BDD12675\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8633_BDD8634\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8631_BDD8632\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~346_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[22]_OTERM1175\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~18_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM896\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM890\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109_BDD9110\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_RESYN8969_BDD8970\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107_BDD9108\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_BDD8636\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973_BDD8974\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~354_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1169\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1173\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971_BDD8972\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[23]_OTERM2974\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[23]_OTERM3166\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[23]_OTERM3102\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[23]_OTERM3038\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[23]_OTERM2782\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]_OTERM2910\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[23]_OTERM2846\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[23]_OTERM2718\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector269~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM936\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM934\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~34\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[10]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~42\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~46\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~58\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_COUNTER[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~62\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add0~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[16]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_STATE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_STATE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal5~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA_LOADED~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA_LOADED~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Add8~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[22]_OTERM1267\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[22]_OTERM1269\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][22]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[22]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector270~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM916\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~62\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][23]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~30\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][24]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~58\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][25]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~54\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][26]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~50\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][27]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~38\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][28]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~18\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][29]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~22\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][30]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~2\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ticks~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|INT_DONE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_INTR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_INTR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_INTR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_INTR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INT_ENABLE[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[4]~90_combout\ : std_logic;
-SIGNAL \SDRAM_DQ[4]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[4]~131_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~23\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~27\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[21]_OTERM1215\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_RESYN8961_BDD8962\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_RESYN8629_BDD8630\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[21]_OTERM3154\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[21]_OTERM3090\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[21]_OTERM3026\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[21]_OTERM2962\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[21]_OTERM2706\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[21]_OTERM2898\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[21]_OTERM2834\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[21]_OTERM2770\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector271~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM920\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[5]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~58\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[10]~_wirecell_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~42\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add0~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER[8]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_STATE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_STATE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_DATA_LOADED~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_DATA_LOADED~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add8~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~14\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~18\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~22\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~26\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal6~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~30\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add6~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Equal6~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1084\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[17]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1078\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[17]_OTERM1076\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]_OTERM67\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM593\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM601\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[1]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~382_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~22_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[17]_OTERM1237\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[17]_OTERM3162\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[17]_OTERM3098\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[17]_OTERM3034\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[17]_OTERM2970\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[17]_OTERM2714\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[17]_OTERM2778\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[17]_OTERM2906\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[17]_OTERM2842\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector275~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1617\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal31~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal31~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal31~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal31~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal31~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal31~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add12~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal30~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Equal30~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add13~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[5]_OTERM1771\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~6\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[6]_OTERM1763\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[6]~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[6]~111_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[6]_OTERM2992\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[6]_OTERM3056\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[6]_OTERM3184\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[6]_OTERM3120\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[6]_OTERM2928\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[6]_OTERM2864\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[6]_OTERM2736\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[6]_OTERM2800\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~18\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~34\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~38\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~2\ : std_logic;
-SIGNAL \myVirtualToplevel|Add4~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux267~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux267~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[5]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~23_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[5]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~23_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[5]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_ENABLE_FIFO~q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[5]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[5]~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[5]~127_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[5]_OTERM2930\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[5]_OTERM2866\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[5]_OTERM2738\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[5]_OTERM2802\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[5]_OTERM2994\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[5]_OTERM3186\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[5]_OTERM3058\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[5]_OTERM3122\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux90~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[13]~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_OTERM99\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector345~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux91~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~21_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[3]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_OVERRUN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_OVERRUN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_OVERRUN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_OVERRUN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~21_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[3]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~71_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[3]~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[3]~99_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[3]_OTERM3190\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[3]_OTERM3062\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[3]_OTERM3126\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[3]_OTERM2998\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[3]_OTERM2742\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[3]_OTERM2934\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[3]_OTERM2806\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[3]_OTERM2870\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|INT_ENABLE[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[11]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~22\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[7]_OTERM1761\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~26\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[8]_OTERM1759\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~30\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[9]_OTERM1769\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~10\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[10]_OTERM1767\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~14\ : std_logic;
-SIGNAL \myVirtualToplevel|Add11~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[11]_OTERM1765\ : std_logic;
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~104_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[11]~76_RESYN8725_BDD8726\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[11]~76_combout\ : std_logic;
-SIGNAL \SDRAM_DQ[11]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM21\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_OTERM49\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM529\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM525\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM527\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~309_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SOCCFG_CS_RESYN8753_BDD8754\ : std_logic;
-SIGNAL \myVirtualToplevel|SOCCFG_CS~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][21]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[21]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[21]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[21]_OTERM3347\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_SELECT~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0_CS~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_ENABLE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~19_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[1]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FULL_V~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FULL_V~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FULL_V~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FULL_V~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~19_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[1]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~98_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~96_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~97_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~31_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~99_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux82~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[1]~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[8]_OTERM1221\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~73_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[8]_OTERM3004\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[8]_OTERM3132\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[8]_OTERM3196\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[8]_OTERM3068\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[8]_OTERM2940\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[8]_OTERM2812\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[8]_OTERM2748\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[8]_OTERM2876\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux75~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[8]~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux264~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[8]~100_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux94~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[8]~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_OTERM39\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM547\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM545\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM543\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~186_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~190_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~206_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~202_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~207_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~203_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~191_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~187_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~195_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~199_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~211_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~215_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~214_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~210_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~198_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~194_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]_OTERM1835\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]_OTERM1837\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~193_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~192_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~213_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~205_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~204_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~212_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~201_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~200_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~209_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~188_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~189_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~197_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~196_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8703_BDD8704\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8699_BDD8700\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8701_BDD8702\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[18]_OTERM1235\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN9301_BDD9302\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12798_BDD12799\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12800_BDD12801\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_RESYN9249_BDD9250\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[19]_OTERM1233\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[19]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1401\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1399\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1179\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|BRAM_WREN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][14]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux69~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~112_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[14]~70_combout\ : std_logic;
-SIGNAL \SDRAM_DQ[14]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM85\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]_OTERM97\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER0_CS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER0_CS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[26]~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][26]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[26]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[26]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[2]_OTERM2872\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[2]_OTERM2936\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[2]_OTERM2744\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[2]_OTERM2808\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[2]_OTERM3128\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[2]_OTERM3192\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[2]_OTERM3000\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[2]_OTERM3064\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector274~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM924\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][18]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUSY~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_BUSY~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUSY~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUSY~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[18]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[18]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[18]_OTERM3340\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_SELECT~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTR0_CS_RESYN8755_BDD8756\ : std_logic;
-SIGNAL \myVirtualToplevel|INTR0_CS~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SOCCFG[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][19]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[19]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[19]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]_OTERM63\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|BRAM_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][29]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[29]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[29]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO~25_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_DATA[7]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO~25_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_DATA[7]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~10\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add9~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SOCCFG[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[7]~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[7]~107_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[7]_OTERM3198\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[7]_OTERM3134\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[7]_OTERM3006\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[7]_OTERM3070\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[7]_OTERM2878\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[7]_OTERM2942\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[7]_OTERM2750\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[7]_OTERM2814\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux76~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[7]~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[8]~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1075~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1411\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1583\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1573\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1571\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1599\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1597\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1271\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1275\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1497\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1495\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1375\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1377\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1447\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1445\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|LessThan3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[15]~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_OTERM95\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_SELECT~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SOCCFG_CS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux73~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux73~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux93~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~108_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[10]~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]_OTERM51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector348~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[11]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12612_BDD12613\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614_BDD12615\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]_OTERM3336\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[0]~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[43]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[46]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[47]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[50]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[51]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[52]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[54]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]_OTERM3331\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[39]_OTERM3326\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[33]_OTERM1635\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[35]_OTERM1639\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[34]_OTERM1637\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[32]_OTERM1633\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[56]_OTERM1681\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[55]_OTERM1679\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[54]_OTERM1677\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[53]_OTERM1675\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]_OTERM1673\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[51]_OTERM1671\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[50]_OTERM1669\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[36]_OTERM1641\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]_OTERM1643\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[39]_OTERM1647\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[38]_OTERM1645\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[40]_OTERM1649\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[42]_OTERM1653\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[41]_OTERM1651\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[46]_OTERM1661\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[43]_OTERM1655\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[45]_OTERM1659\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[44]_OTERM1657\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[48]_OTERM1665\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[49]_OTERM1667\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[47]_OTERM1663\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9017_BDD9018\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9019_BDD9020\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8665_BDD8666\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8663_BDD8664\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8659_BDD8660\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657_BDD8658\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8661_BDD8662\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021_BDD9022\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~5_RESYN8715_BDD8716\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023_BDD9024\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~161_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12554_BDD12555\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~116_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359_BDD9360\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_BDD9356\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9357_BDD9358\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_BDD9076\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12556_BDD12557\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_BDD9016\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~152_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542_BDD12543\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_BDD12545\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM898\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780_BDD12781\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782_BDD12783\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~109_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[25]_OTERM2764\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[25]_OTERM2700\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[25]_OTERM2892\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]_OTERM2828\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[25]_OTERM3148\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[25]_OTERM3020\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[25]_OTERM3084\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[25]_OTERM2956\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[25]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][25]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[25]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM27\ : std_logic;
-SIGNAL \SDRAM_DQ[9]~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[25]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector349~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[9]_OTERM3052\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[9]_OTERM3180\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[9]_OTERM3116\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[9]_OTERM2988\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[9]_OTERM2732\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[9]_OTERM2860\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[9]_OTERM2796\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[9]_OTERM2924\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux74~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|status[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[9]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux263~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[9]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[9]~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_OTERM53\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_36\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]_OTERM1585\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]_OTERM1587\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1483\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]_OTERM1535\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[1]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1607\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1605\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1549\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]_OTERM1559\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector276~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM784\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][16]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~116_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux89~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[16]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]_OTERM77\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]_OTERM2912\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[16]_OTERM2720\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[16]_OTERM2848\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[16]_OTERM2784\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[16]_OTERM3104\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[16]_OTERM2976\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[16]_OTERM3168\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[16]_OTERM3040\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[16]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~296_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~103_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~87_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~106_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[1]_OTERM1223\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[1]_OTERM2810\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[1]_OTERM2938\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[1]_OTERM2746\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[1]_OTERM2874\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[1]_OTERM3130\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[1]_OTERM3066\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[1]_OTERM3002\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[1]_OTERM3194\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector15~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector15~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector19~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_DATA_REQ~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_READ~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_DATA_VALID~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_DATA_VALID~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector21~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector17~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector20~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector20~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_OVERRUN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_OVERRUN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_OVERRUN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux77~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM559\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM555\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM557\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~226_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_CHANNEL~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_CHANNEL~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Selector0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][30]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[30]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM83\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~81_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[30]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector344~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[15]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][27]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[27]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM19\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[27]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[3]~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux78~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM565\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM561\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM563\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~351_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[4]_OTERM1225\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[4]_OTERM3060\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[4]_OTERM3124\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[4]_OTERM2996\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[4]_OTERM3188\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[4]_OTERM2932\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[4]_OTERM2740\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[4]_OTERM2804\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[4]_OTERM2868\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux79~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM571\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM567\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM569\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~208_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491_BDD8492\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]_OTERM2880\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[0]_OTERM2752\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]_OTERM2816\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[0]_OTERM2944\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]_OTERM3200\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]_OTERM3072\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]_OTERM3136\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[0]_OTERM3008\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[0]_OTERM3220\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~324_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8985_BDD8986\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~101_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~98_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8987_BDD8988\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1205\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_40\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1601\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1603\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]_OTERM1619\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1545\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1429\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1555\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1479\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1551\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM691\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM689\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM685\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~262_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]_OTERM2688\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8495_BDD8496\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8497_BDD8498\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12404_BDD12405\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402_BDD12403\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12408_BDD12409\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12406_BDD12407\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN12632_BDD12633\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12412_BDD12413\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410_BDD12411\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493_BDD8494\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12396_BDD12397\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394_BDD12395\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12398_BDD12399\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12400_BDD12401\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587_BDD8588\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589_BDD8590\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_RESYN8583_BDD8584\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_RESYN8571_BDD8572\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_RESYN12642_BDD12643\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM758\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504_BDD12505\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_RESYN12726_BDD12727\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_RESYN12698_BDD12699\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_RESYN12728_BDD12729\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_RESYN12732_BDD12733\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_RESYN12484_BDD12485\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_RESYN12734_BDD12735\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_RESYN12730_BDD12731\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500_BDD12501\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12502_BDD12503\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_RESYN12742_BDD12743\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_RESYN12738_BDD12739\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_RESYN12740_BDD12741\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_RESYN12496_BDD12497\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_RESYN12490_BDD12491\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_RESYN12492_BDD12493\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_RESYN12486_BDD12487\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_RESYN12488_BDD12489\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_RESYN12736_BDD12737\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_RESYN12712_BDD12713\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_RESYN12714_BDD12715\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_RESYN12716_BDD12717\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux133~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~79_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_RESYN8929_BDD8930\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_RESYN12708_BDD12709\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_RESYN8935_BDD8936\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_RESYN12564_BDD12565\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710_BDD12711\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_RESYN12696_BDD12697\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_RESYN12694_BDD12695\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_RESYN12700_BDD12701\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_RESYN12804_BDD12805\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_RESYN12702_BDD12703\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089_BDD9090\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_BDD8448\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8449_BDD8450\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165_BDD9166\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9167_BDD9168\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8825_BDD8826\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8823_BDD8824\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827_BDD8828\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457_BDD8458\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833_BDD8834\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12388_BDD12389\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_RESYN12558_BDD12559\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461_BDD8462\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091_BDD9092\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_BDD8460\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8831_BDD8832\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386_BDD12387\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829_BDD8830\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8453_BDD8454\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8455_BDD8456\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8841_BDD8842\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8843_BDD8844\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463_BDD8464\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465_BDD8466\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_RESYN8837_BDD8838\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8861_BDD8862\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8473_BDD8474\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475_BDD8476\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859_BDD8860\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_RESYN12634_BDD12635\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12588_BDD12589\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590_BDD12591\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_BDD8852\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853_BDD8854\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469_BDD8470\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093_BDD9094\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_BDD8468\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179_BDD9180\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173_BDD9174\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177_BDD9178\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169_BDD9170\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171_BDD9172\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175_BDD9176\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323_BDD9324\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_BDD8846\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325_BDD9326\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_BDD8848\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849_BDD8850\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8867_BDD8868\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8869_BDD8870\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12638_BDD12639\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12636_BDD12637\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8873_BDD8874\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8875_BDD8876\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877_BDD8878\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux80~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM577\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM575\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM573\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~277_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tIdx~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8427_BDD8428\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8425_BDD8426\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[1]_OTERM2686\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM513\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM511\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM507\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_RESYN12692_BDD12693\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_RESYN12754_BDD12755\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_RESYN12746_BDD12747\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_RESYN12756_BDD12757\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~158_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~159_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~156_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~157_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~162_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~161_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~163_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~160_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12764_BDD12765\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12510_BDD12511\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766_BDD12767\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762_BDD12763\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~166_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~164_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~167_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~165_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~171_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~168_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~169_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~170_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207_BDD9208\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector301~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM754\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM750\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_RESYN12520_BDD12521\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~113_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_RESYN12522_BDD12523\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~112_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12750_BDD12751\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_RESYN12512_BDD12513\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_RESYN12514_BDD12515\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~102_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526_BDD12527\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524_BDD12525\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~434_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9247_BDD9248\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9245_BDD9246\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~122_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~125_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~124_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~123_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~117_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~114_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~115_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~116_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~118_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~121_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~120_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~119_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639_BDD8640\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641_BDD8642\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add36~71_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult[11]_OTERM1227\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add33~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add34~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~101_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~98_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~102_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]_OTERM3275\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_RESYN12626_BDD12627\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_RESYN8921_BDD8922\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9237_BDD9238\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_RESYN8603_BDD8604\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9239_BDD9240\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9235_BDD9236\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9213_BDD9214\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215_BDD9216\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_RESYN12460_BDD12461\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217_BDD9218\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_RESYN9307_BDD9308\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_RESYN12684_BDD12685\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221_BDD9222\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223_BDD9224\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_RESYN8599_BDD8600\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_RESYN12682_BDD12683\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597_BDD8598\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_RESYN12680_BDD12681\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_RESYN8595_BDD8596\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]_OTERM3281\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER0_CS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_OVERRUN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|TX_OVERRUN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|Add10~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_OVERRUN~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_OVERRUN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[20]_OTERM1387\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[20]_OTERM1389\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][20]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[20]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_OTERM71\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[20]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~106_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~103_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~107_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_RESYN12652_BDD12653\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector899~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector503~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452_BDD12453\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454_BDD12455\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector343~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~116_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~114_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~115_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~113_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~117_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~145_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~144_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~143_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~146_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~147_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~139_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~140_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~141_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~138_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~142_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~135_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~134_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~136_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~133_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~137_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]_OTERM3302\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|LessThan0~0_RESYN12604_BDD12605\ : std_logic;
-SIGNAL \myVirtualToplevel|LessThan0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|Mux71~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[12]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ[12]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[12]~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]_OTERM101\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add7~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector346~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~96_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~93_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~97_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~89_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~91_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~120_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~119_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~121_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~118_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~122_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]_OTERM3293\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151_BDD9152\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9149_BDD9150\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953_BDD8954\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955_BDD8956\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add21~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp[18]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_RESYN12534_BDD12535\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621_BDD8622\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623_BDD8624\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12532_BDD12533\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12530_BDD12531\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~98_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~97_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~99_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~96_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~101_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~103_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~102_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~100_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~104_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~107_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~105_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~106_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~110_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~109_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~108_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~111_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM297\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM301\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1191\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1195\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1197\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1199\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615_BDD8616\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~129_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~127_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~128_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~126_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~132_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~133_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~131_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~130_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_RESYN8617_BDD8618\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~136_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~137_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~135_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~134_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_RESYN12752_BDD12753\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~141_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~138_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~140_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~139_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676_BDD12677\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~131_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~130_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~129_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~128_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~132_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]_OTERM3320\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]_OTERM3317\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pause[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pause[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~62_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pause[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pause[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add10~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_RESYN8613_BDD8614\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_RESYN12748_BDD12749\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~73_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_RESYN12508_BDD12509\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~71_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_RESYN12516_BDD12517\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_RESYN12518_BDD12519\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~79_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225_BDD9226\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229_BDD9230\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233_BDD9234\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_RESYN12686_BDD12687\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601_BDD8602\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231_BDD9232\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add16~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]_OTERM1941\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add15~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]_OTERM1869\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~93_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~91_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_OTERM1861\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~81_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~89_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~87_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~71_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_RESYN12744_BDD12745\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724_BDD12725\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]_OTERM1851\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~73_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~124_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~125_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~126_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~123_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~127_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1675~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[23]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]_OTERM3345\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuLastEN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~154_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~156_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~157_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462_BDD12463\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12464_BDD12465\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~155_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460_BDD13461\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_BDD8942\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~159_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~172_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]_OTERM1855\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_RESYN12528_BDD12529\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_RESYN12758_BDD12759\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760_BDD12761\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_OTERM1853\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~173_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~178_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~181_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~179_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~180_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~185_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~183_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~182_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~184_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~174_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~177_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~175_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~176_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12718_BDD12719\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~149_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722_BDD12723\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720_BDD12721\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458_BDD13459\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_BDD8938\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939_BDD8940\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~153_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~152_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~154_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~155_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~144_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~147_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~146_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~145_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~148_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~151_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~150_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~149_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~143_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]_OTERM1857\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]_OTERM1859\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~142_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~87_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]_OTERM3278\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_CS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_CS_RESYN9119_BDD9120\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_CS_RESYN9121_BDD9122\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_CS~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][17]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[17]_OTERM3334\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_SELECT_RESYN9117_BDD9118\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_SELECT_RESYN9115_BDD9116\ : std_logic;
-SIGNAL \myVirtualToplevel|IO_SELECT~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_BUSY~1_RESYN12610_BDD12611\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_READ_ENABLE_LAST~q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_BUSY~1_RESYN12608_BDD12609\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_BUSY~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add5~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM994\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM998\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr128~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM996\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM988\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM992\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add3~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]_OTERM3314\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_RESYN12620_BDD12621\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add9~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]_OTERM2665\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add6~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]_OTERM3338\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM[3]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[1]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank[0]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDoneLast~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~110_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~109_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add32~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~111_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add23~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add24~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add25~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add22~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~108_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~112_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9139_BDD9140\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9141_BDD9142\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9143_BDD9144\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector218~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1694~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1692~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1691~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1690~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1689~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1688~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1686~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1687~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add56~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add44~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1693~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1_RTM0883~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM882\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536_BDD12537\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[16]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add16~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS_OTERM2181\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1701~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1700~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1699~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC_OTERM2183\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP_OTERM2185\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS_OTERM2179\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1377~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE_OTERM2189\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~46_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~42_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~38_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~39\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~34_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~35\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~30_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~31\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~26_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~27\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~22_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~23\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~18_cout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~19\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_OTERM2223\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE_OTERM2187\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3_OTERM2219\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_OTERM2175\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM349\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_RTM0364_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[0]_OTERM363\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[1]_OTERM2227\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2_OTERM2221\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4_OTERM2217\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector112~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[1]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[30]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[2]_OTERM2191\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[2]_OTERM2197\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[2]_OTERM2199\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_OTERM2193\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[0]_OTERM2211\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM605\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM615\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM607\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM611\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM609\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM613\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[0]_OTERM2213\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[0]_OTERM2215\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT[1]_OTERM2201\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT[1]_OTERM2209\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_OTERM2203\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT[1]_OTERM2207\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector43~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector41~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~125_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~126\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~113_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~114\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~110\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~106\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~102\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~121_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~122\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~117_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~118\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~74\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~98\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~94\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~90\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~86\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~82\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~78\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[26]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[25]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector113~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add15~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~11\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1143\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE_OTERM2171\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM872\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM780\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM874\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM870\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF_OTERM2173\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM774\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM778\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1145\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~30\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector244~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector243~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector242~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector240~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~14\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector239~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~18\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector238~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector237~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~10\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector236~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~26\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add2~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector235~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux175~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux176~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux177~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux179~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux162~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux164~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux165~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux166~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux167~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux168~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux169~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux170~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux171~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux172~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux173~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux174~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~reg0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~enfeeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~en_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[30]_OTERM2157\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819_BDD8820\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786_BDD12787\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_RESYN9163_BDD9164\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_OTERM2546\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM355\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM353\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_163\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM351\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM465\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux404~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM463\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM467\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[32]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[32]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[32]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[32]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[32]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_OTERM2403\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[32]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector76~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[0]_OTERM2013\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[0]_OTERM2015\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM866\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1100\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1104\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM862\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM858\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM842\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM850\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM806\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM814\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM810\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM818\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_OTERM2498\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add40~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_OTERM2281\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM317\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM323\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM325\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN~100_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM581\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add17~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM587\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM589\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM591\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[0]~89_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299_BDD9300\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047_BDD9048\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045_BDD9046\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049_BDD9050\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[8]_OTERM3236\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_OTERM2311\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_OTERM2313\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_OTERM2309\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_OTERM2279\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM309\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM307\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM311\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1_RTM0314~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM313\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM305\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM379\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM383\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM381\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_OTERM2492\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~91_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM585\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM579\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM583\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[1]_OTERM2277\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_OTERM2489\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_OTERM2275\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~96_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~93_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_OTERM2271\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067_BDD9068\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069_BDD9070\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071_BDD9072\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[3]_OTERM3226\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_OTERM2495\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[3]_OTERM2273\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~99_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_OTERM2283\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_OTERM2507\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM387\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM389\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM385\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux428~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM447\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM443\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM435\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM445\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~87_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM455\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux427~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM451\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM453\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_OTERM2293\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_OTERM2501\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057_BDD9058\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055_BDD9056\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9059_BDD9060\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[5]_OTERM3232\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector103~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_OTERM2301\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM479\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux426~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM477\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM481\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM401\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM397\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM399\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_OTERM2504\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~79_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_OTERM2285\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux425~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM928\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM926\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_OTERM2510\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061_BDD9062\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063_BDD9064\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065_BDD9066\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[7]_OTERM3228\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM820\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM393\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM395\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM391\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_OTERM2295\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_OTERM2297\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_OTERM2299\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM812\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_OTERM2305\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_OTERM2303\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9051_BDD9052\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053_BDD9054\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]_OTERM3234\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_OTERM2307\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM816\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_OTERM2287\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_OTERM2289\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297_BDD9298\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295_BDD9296\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_OTERM3230\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_OTERM2291\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM808\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[15]_OTERM1569\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM335\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM329\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM830\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM343\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM345\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM341\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM826\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_OTERM2329\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035_BDD9036\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037_BDD9038\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9039_BDD9040\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[13]_OTERM3242\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_OTERM2325\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_OTERM2327\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM822\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_OTERM2315\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_OTERM2317\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_OTERM2319\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9041_BDD9042\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043_BDD9044\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[12]_OTERM3238\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM824\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM828\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM832\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM836\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM834\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM932\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM930\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM639\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM643\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux362~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM641\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_OTERM2522\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_OTERM2337\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM852\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_OTERM2331\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux417~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM888\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM886\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_OTERM2513\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM693\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM695\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux361~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM697\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM844\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM854\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM838\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM846\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_OTERM2516\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790_BDD12791\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12792_BDD12793\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796_BDD12797\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[18]_OTERM3244\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_OTERM2335\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_OTERM2333\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM848\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[19]_OTERM3240\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_OTERM2323\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_OTERM2519\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_OTERM2321\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM840\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_OTERM2341\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_OTERM2339\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_OTERM2531\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM663\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM657\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM655\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM856\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_OTERM2525\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_OTERM2351\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[21]_OTERM3248\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_OTERM2353\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM860\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_OTERM2361\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_OTERM2363\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_OTERM2528\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[22]_OTERM3252\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM864\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM705\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM701\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM707\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_OTERM2365\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_OTERM2369\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_OTERM2367\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_OTERM2357\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[25]_OTERM3250\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_OTERM2359\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_OTERM2355\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1131\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_OTERM2375\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8695_BDD8696\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693_BDD8694\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8697_BDD8698\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[24]_OTERM3254\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_OTERM2373\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_OTERM2371\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1135\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_OTERM2343\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM407\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM405\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM403\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_OTERM2534\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]_OTERM3246\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1137\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1133\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1141\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1139\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1106\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_OTERM2349\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_OTERM2347\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_OTERM2345\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM703\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM699\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1102\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM473\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM475\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[30]_OTERM2397\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1090\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_OTERM2377\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_OTERM2381\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8689_BDD8690\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8687_BDD8688\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691_BDD8692\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[28]_OTERM3256\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_OTERM2379\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1088\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1086\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_OTERM2393\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1481~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_OTERM2389\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]_OTERM3258\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_OTERM2391\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1092\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1072\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1070\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[31]_OTERM2383\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM669\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM667\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM665\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM868\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[0]_OTERM1955\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[1]_OTERM1949\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[1]_OTERM2003\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[1]_OTERM2005\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM461\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux403~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM457\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM459\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_154\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]_OTERM2169\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_OTERM2395\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_OTERM2537\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector75~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[2]_OTERM1951\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_OTERM2009\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[2]_OTERM2007\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[2]_OTERM2011\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_OTERM2401\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_RTM0716_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1114\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_157\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~4_RTM01120_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1119\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1112\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1116\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_OTERM2399\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_OTERM2540\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]_OTERM1777\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[3]_OTERM2001\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[3]_OTERM1997\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_OTERM1999\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_OTERM2543\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM103\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM111\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_160\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM109\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_OTERM2387\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_OTERM2385\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[3]_OTERM1953\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[35]_OTERM1775\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[4]_OTERM1965\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[4]_OTERM2021\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_OTERM2019\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[4]_OTERM2017\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_OTERM2405\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM117\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_175\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM115\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM113\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_OTERM2407\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_OTERM2555\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[36]_OTERM1783\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[5]_OTERM1957\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[5]_OTERM2039\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[5]_OTERM2035\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_OTERM2037\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_OTERM2549\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_OTERM2417\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_OTERM2419\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM129\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_169\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM127\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM125\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[37]_OTERM1779\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[6]_OTERM1961\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_OTERM2049\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[6]_OTERM2051\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[6]_OTERM2047\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_OTERM2552\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM143\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM141\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_172\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~2_RTM0146_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM145\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM137\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_OTERM2429\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_OTERM2427\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[38]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]_OTERM1781\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[7]_OTERM1967\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[7]_OTERM2027\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_OTERM2025\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[7]_OTERM2023\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_OTERM2558\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_OTERM2409\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM361\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM357\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM359\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_166\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM123\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]_OTERM1785\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[8]_OTERM1971\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[8]_OTERM2063\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_OTERM2061\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[8]_OTERM2059\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM495\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM487\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM497\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~4_RTM0500_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM499\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_OTERM2441\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_OTERM2437\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_OTERM2439\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[40]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[40]_OTERM1793\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[9]_OTERM1959\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_OTERM2043\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[9]_OTERM2041\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[9]_OTERM2045\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM131\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM135\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[9]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM133\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_OTERM2425\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_OTERM2421\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_OTERM2423\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[41]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[41]_OTERM1791\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[10]_OTERM1963\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_OTERM2055\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[10]_OTERM2057\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[10]_OTERM2053\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_OTERM2435\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_OTERM2433\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_OTERM2431\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~2_RTM0152_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM151\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM149\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[42]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[42]_OTERM1789\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[11]_OTERM1969\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[11]_OTERM2029\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[11]_OTERM2033\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_OTERM2031\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[11]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_OTERM2413\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[43]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[43]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[43]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[43]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_OTERM2415\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[43]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM489\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM483\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~4_RTM0492_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM491\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[43]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[43]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_OTERM2411\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[43]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[43]_OTERM1787\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[12]_OTERM1981\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[12]_OTERM2069\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]_OTERM2065\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_OTERM2067\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_OTERM2443\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_OTERM2447\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM159\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_OTERM2445\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[44]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]_OTERM1799\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[13]_OTERM1973\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[13]_OTERM2083\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_OTERM2085\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[13]_OTERM2087\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[13]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_OTERM2453\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_OTERM2455\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_OTERM2457\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM165\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM163\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM161\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[45]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[45]_OTERM1795\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[14]_OTERM1977\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[14]_OTERM2095\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[14]_OTERM2099\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_OTERM2097\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM681\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM679\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[46]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[46]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[46]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM241\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM237\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM235\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[46]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[46]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[46]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[46]_OTERM1797\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[15]_OTERM2071\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_OTERM2073\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[15]_OTERM2075\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM671\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM673\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM675\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[47]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[47]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[47]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[47]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM295\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM293\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM291\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[47]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[47]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[47]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[47]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[15]_OTERM1983\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[15]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]_OTERM1801\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[16]_OTERM1987\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_OTERM2109\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[16]_OTERM2111\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[16]_OTERM2107\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[16]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM649\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM645\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM647\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~2_RTM0652_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM651\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_OTERM2570\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux390~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM429\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM433\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM431\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_OTERM2465\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[48]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[48]_OTERM1809\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[17]_OTERM1975\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[17]_OTERM2089\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[17]_OTERM2093\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_OTERM2561\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM427\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM425\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux389~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM423\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_OTERM2459\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~3_RTM0418_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM417\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM415\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM413\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM411\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[49]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_OTERM2091\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]_OTERM1807\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[18]_OTERM1979\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[18]_OTERM2105\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_OTERM2103\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[18]_OTERM2101\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM723\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM725\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~3_RTM0729_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM728\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[50]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[50]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[50]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_OTERM2463\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[50]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[50]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[50]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[50]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_OTERM2564\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[50]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[50]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_OTERM2461\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[50]_OTERM1805\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[19]_OTERM1985\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[19]_OTERM2081\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_OTERM2079\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[19]_OTERM2077\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_OTERM2449\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[51]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_OTERM2451\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[51]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[51]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM713\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM709\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~3_RTM0720_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM719\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[51]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[51]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_OTERM2567\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[51]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[51]_OTERM1803\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[20]_OTERM1993\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[20]_OTERM2113\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_OTERM2115\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[20]_OTERM2117\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_OTERM2467\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[52]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[52]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[52]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[52]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM619\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM627\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM629\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM625\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM621\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[52]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[52]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[52]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_OTERM2469\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[52]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_OTERM2589\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[52]_OTERM1813\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[21]_OTERM1989\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[21]_OTERM2133\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_OTERM2135\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[21]_OTERM2137\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~1_RTM0258_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM257\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM255\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM253\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_OTERM2481\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_OTERM2483\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_OTERM2576\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[53]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[53]_OTERM1811\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[22]_OTERM1991\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_OTERM2145\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[22]_OTERM2143\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[22]_OTERM2147\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_OTERM2584\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[54]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[54]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[54]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[54]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_OTERM2582\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[54]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM273\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM271\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[54]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[54]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[54]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_OTERM2587\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]_OTERM1817\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[6]_OTERM2259\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[30]_OTERM2159\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM289\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM283\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM287\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM285\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[62]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[62]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[62]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]_OTERM2624\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[62]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[62]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[62]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[62]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector46~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~116_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~112_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[25]_OTERM2129\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[24]_OTERM2149\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]_OTERM1995\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[23]_OTERM2127\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_OTERM2125\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[23]_OTERM2123\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_OTERM2475\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_OTERM2595\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_OTERM2598\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM247\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM245\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~1_RTM0250_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM249\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[55]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[55]_OTERM1815\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[0]_OTERM2247\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[24]_OTERM2151\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[0]_OTERM2250\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_OTERM2606\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_OTERM2603\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM743\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM741\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~3_RTM0747_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM746\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_OTERM2601\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[56]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[1]_OTERM2229\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[25]_OTERM2131\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_OTERM2479\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM631\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM635\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM633\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_OTERM2573\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_OTERM2477\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[57]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[1]_OTERM2232\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[2]_OTERM2238\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[2]_OTERM2235\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[26]_OTERM2141\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_OTERM2487\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_OTERM2579\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM263\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~1_RTM0266_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM265\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM261\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_OTERM2485\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[58]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[26]_OTERM2139\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[27]_OTERM2119\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[3]_OTERM2241\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[27]_OTERM2121\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_OTERM2592\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_OTERM2471\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_OTERM2473\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM732\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM734\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~3_RTM0738_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM737\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[59]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[3]_OTERM2244\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[28]_OTERM2163\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[4]_OTERM2262\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_OTERM2617\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~1_RTM0232_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM231\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM229\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_OTERM2620\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_OTERM2615\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[60]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[4]_OTERM2265\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[28]_OTERM2161\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[29]_OTERM2153\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[5]_OTERM2253\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[29]_OTERM2155\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE[5]_OTERM2256\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_OTERM2608\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_OTERM2610\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_OTERM2613\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~1_RTM0280_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM279\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM277\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[61]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[31]_OTERM2165\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]_OTERM2268\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS[31]_OTERM2167\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM369\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM373\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM367\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM371\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA[63]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA[63]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA[63]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[63]_OTERM2622\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2[63]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2[63]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2[63]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2[63]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2[63]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector45~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~108_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~104_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[7]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal6~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|Equal6~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~25_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~17_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[7]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[6]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~24_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[6]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~23_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[5]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~22_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[4]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[3]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~21_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[3]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[2]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~20_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[2]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~19_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[1]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO~18_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_DATA[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TXD~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TXD~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_DATA_WRITE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[37]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[36]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[35]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[34]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[33]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[32]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[31]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[30]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[29]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[28]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[27]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[26]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[25]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[23]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[22]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[21]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[20]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[19]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[18]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[17]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[14]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[12]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SD_ADDR[0][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[10]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[8]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[2]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[7]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[39]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[43]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector172~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|cs_bo~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[4]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol[5]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux92~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux91~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA[1]~feeder_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_WE_n~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_RAS_n~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_CAS_n~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_index\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\ : std_logic_vector(4 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|timer_enabled\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ticks\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pause\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RESET_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SD_WR\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SD_HNDSHK_IN\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SD_RESET\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\ : std_logic_vector(47 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|TX_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|prescale_counter\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_TICK\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SECOND_DOWN_TICK\ : std_logic_vector(27 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|MILLISEC_UP_TICK\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|divResult\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_TICK\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_TICK\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SD_RESET_TIMER\ : std_logic_vector(6 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SD_DATA_WRITE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_BUFFER\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RTC_YEAR_COUNTER\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\ : std_logic_vector(10 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SD\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SECOND_DOWN_COUNTER\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|MICROSEC_DOWN_COUNTER\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|multResult\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RESET_COUNTER_RX\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RTC_MILLISEC_COUNTER\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SD_RD\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|pc\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\ : std_logic_vector(0 TO 24);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|MILLISEC_DOWN_COUNTER\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|MILLISEC_UP_COUNTER\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|IO_DATA_READ_INTRCTL\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RTC_MICROSEC_COUNTER\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_DATA\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|decode2|eq_node\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\ : std_logic_vector(6 DOWNTO 0);
-SIGNAL \myVirtualToplevel|IO_DATA_READ_SOCCFG\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\ : std_logic_vector(4 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RTC_MONTH_COUNTER\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|sp\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\ : std_logic_vector(6 DOWNTO 0);
-SIGNAL \myVirtualToplevel|INT_ENABLE\ : std_logic_vector(16 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\ : std_logic_vector(16 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_DATA\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_DATA\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RTC_SECOND_COUNTER\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RTC_MINUTE_COUNTER\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RTC_HOUR_COUNTER\ : std_logic_vector(4 DOWNTO 0);
-SIGNAL \myVirtualToplevel|RTC_DAY_COUNTER\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|IO_DATA_READ\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\ : std_logic_vector(0 TO 24);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|TX_BUFFER\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|RX_BUFFER\ : std_logic_vector(8 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_BUFFER\ : std_logic_vector(8 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\ : std_logic_vector(0 TO 24);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM471~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[24]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[33]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[43]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[31]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[28]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_RESYN12804_BDD12805\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~23_RESYN12802_BDD12803\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN12800_BDD12801\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12796_BDD12797\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12794_BDD12795\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12792_BDD12793\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_RESYN12790_BDD12791\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_RESYN12788_BDD12789\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN12798_BDD12799\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_RESYN12786_BDD12787\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_RESYN12782_BDD12783\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_RESYN12780_BDD12781\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_RESYN12778_BDD12779\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12776_BDD12777\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12774_BDD12775\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~10_RESYN12772_BDD12773\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_RESYN12770_BDD12771\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_RESYN12768_BDD12769\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12766_BDD12767\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12764_BDD12765\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12762_BDD12763\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~5_RESYN12760_BDD12761\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~104_RESYN12758_BDD12759\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~5_RESYN12756_BDD12757\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~4_RESYN12754_BDD12755\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_RESYN12752_BDD12753\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_RESYN12750_BDD12751\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_RESYN12748_BDD12749\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~3_RESYN12746_BDD12747\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~7_RESYN12744_BDD12745\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~1_RESYN12742_BDD12743\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_RESYN12740_BDD12741\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_RESYN12738_BDD12739\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_RESYN12736_BDD12737\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_RESYN12734_BDD12735\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_RESYN12732_BDD12733\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_RESYN12730_BDD12731\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_RESYN12728_BDD12729\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_RESYN12726_BDD12727\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136_RESYN12724_BDD12725\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12722_BDD12723\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12720_BDD12721\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12718_BDD12719\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~0_RESYN12716_BDD12717\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_RESYN12714_BDD12715\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_RESYN12712_BDD12713\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_RESYN12710_BDD12711\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_RESYN12708_BDD12709\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_RESYN12706_BDD12707\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_RESYN12704_BDD12705\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_RESYN12702_BDD12703\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_RESYN12700_BDD12701\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_RESYN12698_BDD12699\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_RESYN12696_BDD12697\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_RESYN12694_BDD12695\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_RESYN12692_BDD12693\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_RESYN12690_BDD12691\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_RESYN12688_BDD12689\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~60_RESYN12686_BDD12687\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~43_RESYN12684_BDD12685\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~35_RESYN12682_BDD12683\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~25_RESYN12680_BDD12681\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_RESYN12678_BDD12679\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_RESYN12676_BDD12677\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_RESYN12674_BDD12675\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_RESYN12672_BDD12673\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_RESYN12670_BDD12671\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_RESYN12652_BDD12653\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_RESYN12644_BDD12645\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_RESYN12642_BDD12643\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_RESYN12640_BDD12641\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_RESYN12638_BDD12639\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_RESYN12636_BDD12637\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~6_RESYN12634_BDD12635\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_RESYN12632_BDD12633\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_RESYN12628_BDD12629\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_RESYN12626_BDD12627\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_RESYN12624_BDD12625\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_RESYN12622_BDD12623\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_RESYN12620_BDD12621\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_RESYN12618_BDD12619\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_RESYN12614_BDD12615\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_RESYN12612_BDD12613\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_BUSY~1_RESYN12610_BDD12611\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_BUSY~1_RESYN12608_BDD12609\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal4~0_RESYN12606_BDD12607\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_LessThan0~0_RESYN12604_BDD12605\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN12594_BDD12595\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN12592_BDD12593\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_RESYN12590_BDD12591\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_RESYN12588_BDD12589\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~6_RESYN12564_BDD12565\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~11_RESYN12558_BDD12559\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN12556_BDD12557\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN12554_BDD12555\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_RESYN12546_BDD12547\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12544_BDD12545\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12542_BDD12543\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_RESYN12538_BDD12539\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_RESYN12536_BDD12537\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~13_RESYN12534_BDD12535\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_RESYN12532_BDD12533\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_RESYN12530_BDD12531\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~3_RESYN12528_BDD12529\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_RESYN12526_BDD12527\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_RESYN12524_BDD12525\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~3_RESYN12522_BDD12523\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~1_RESYN12520_BDD12521\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~5_RESYN12518_BDD12519\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~4_RESYN12516_BDD12517\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_RESYN12514_BDD12515\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_RESYN12512_BDD12513\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_RESYN12510_BDD12511\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~4_RESYN12508_BDD12509\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_RESYN12504_BDD12505\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_RESYN12502_BDD12503\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_RESYN12500_BDD12501\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_RESYN12496_BDD12497\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~3_RESYN12492_BDD12493\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_RESYN12490_BDD12491\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~0_RESYN12488_BDD12489\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_RESYN12486_BDD12487\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_RESYN12484_BDD12485\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_RESYN12470_BDD12471\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_RESYN12464_BDD12465\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_RESYN12462_BDD12463\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_RESYN12460_BDD12461\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_RESYN12454_BDD12455\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_RESYN12452_BDD12453\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_RESYN12434_BDD12435\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_RESYN12432_BDD12433\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_RESYN12430_BDD12431\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_RESYN12428_BDD12429\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_RESYN12426_BDD12427\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_RESYN12424_BDD12425\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_RESYN12422_BDD12423\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_RESYN12420_BDD12421\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_RESYN12412_BDD12413\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_RESYN12410_BDD12411\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_RESYN12408_BDD12409\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_RESYN12406_BDD12407\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_RESYN12404_BDD12405\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_RESYN12402_BDD12403\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_RESYN12400_BDD12401\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_RESYN12398_BDD12399\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_RESYN12396_BDD12397\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_RESYN12394_BDD12395\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_RESYN12388_BDD12389\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_RESYN12386_BDD12387\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_RESYN12370_BDD12371\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9077_RESYN9359_BDD9360\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9357_BDD9358\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9355_BDD9356\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9349_BDD9350\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9347_BDD9348\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9345_BDD9346\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN9337_BDD9338\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9335_BDD9336\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9333_BDD9334\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8847_RESYN9325_BDD9326\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8845_RESYN9323_BDD9324\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_RESYN9015_RESYN9351_BDD9352\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_BDD9316\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9313_BDD9314\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9311_BDD9312\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~164_RESYN9307_BDD9308\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN9301_BDD9302\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_RESYN9299_BDD9300\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_RESYN9297_BDD9298\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_RESYN9295_BDD9296\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9277_BDD9278\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_BDD9276\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9269_BDD9270\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9267_BDD9268\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9263_BDD9264\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~4_RESYN9251_BDD9252\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~1_RESYN9249_BDD9250\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_RESYN9247_BDD9248\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_RESYN9245_BDD9246\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9239_BDD9240\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9237_BDD9238\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9235_BDD9236\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9233_BDD9234\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9231_BDD9232\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9229_BDD9230\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9225_BDD9226\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_RESYN9223_BDD9224\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_RESYN9221_BDD9222\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_RESYN9217_BDD9218\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_RESYN9215_BDD9216\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_RESYN9213_BDD9214\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_RESYN9207_BDD9208\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9179_BDD9180\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9177_BDD9178\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9175_BDD9176\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9173_BDD9174\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_RESYN9171_BDD9172\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_RESYN9169_BDD9170\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_RESYN9167_BDD9168\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_RESYN9165_BDD9166\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~12_RESYN9163_BDD9164\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_BDD9162\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9159_BDD9160\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9157_BDD9158\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_RESYN9155_BDD9156\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_RESYN9151_BDD9152\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_RESYN9149_BDD9150\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9147_BDD9148\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9145_BDD9146\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9143_BDD9144\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9141_BDD9142\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9139_BDD9140\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9127_BDD9128\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9125_BDD9126\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_CS_RESYN9121_BDD9122\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_CS_RESYN9119_BDD9120\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT_RESYN9117_BDD9118\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8707_RESYN9111_BDD9112\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_RESYN9109_BDD9110\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_RESYN9107_BDD9108\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT_RESYN9115_BDD9116\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8467_RESYN9093_BDD9094\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8459_RESYN9091_BDD9092\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8447_RESYN9089_BDD9090\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_BDD9076\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9071_BDD9072\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9069_BDD9070\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9067_BDD9068\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9065_BDD9066\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9063_BDD9064\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9061_BDD9062\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9059_BDD9060\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9057_BDD9058\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9055_BDD9056\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_RESYN9053_BDD9054\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_RESYN9051_BDD9052\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9049_BDD9050\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9047_BDD9048\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9045_BDD9046\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_RESYN9043_BDD9044\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_RESYN9041_BDD9042\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9039_BDD9040\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9037_BDD9038\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9035_BDD9036\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_RESYN9033_BDD9034\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_RESYN9031_BDD9032\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9029_BDD9030\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9027_BDD9028\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9025_BDD9026\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~3_RESYN9023_BDD9024\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~3_RESYN9021_BDD9022\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_RESYN9019_BDD9020\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_RESYN9017_BDD9018\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_RESYN9015_BDD9016\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~14_RESYN9011_BDD9012\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_RESYN9009_BDD9010\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN9003_BDD9004\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8999_BDD9000\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8997_BDD8998\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8995_BDD8996\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_RESYN8993_BDD8994\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_RESYN8987_BDD8988\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_RESYN8985_BDD8986\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_BDD8984\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8979_BDD8980\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_RESYN8977_BDD8978\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_RESYN8975_BDD8976\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8973_BDD8974\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8971_BDD8972\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~3_RESYN8969_BDD8970\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8967_BDD8968\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_BDD8966\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_BDD8964\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~4_RESYN8961_BDD8962\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_BDD8960\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_RESYN8957_BDD8958\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_RESYN8955_BDD8956\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_RESYN8953_BDD8954\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_RESYN8941_BDD8942\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8939_BDD8940\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8937_BDD8938\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~0_RESYN8935_BDD8936\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_RESYN8929_BDD8930\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~24_RESYN8923_BDD8924\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_RESYN8921_BDD8922\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8877_BDD8878\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8875_BDD8876\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8873_BDD8874\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_RESYN8869_BDD8870\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_RESYN8867_BDD8868\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_RESYN8861_BDD8862\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_RESYN8859_BDD8860\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8853_BDD8854\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_BDD8852\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8849_BDD8850\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8847_BDD8848\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8845_BDD8846\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_RESYN8843_BDD8844\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_RESYN8841_BDD8842\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~3_RESYN8837_BDD8838\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~10_RESYN8833_BDD8834\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~10_RESYN8831_BDD8832\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~4_RESYN8829_BDD8830\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8827_BDD8828\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8825_BDD8826\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8823_BDD8824\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_RESYN8819_BDD8820\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_RESYN8809_BDD8810\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8803_BDD8804\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8791_BDD8792\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_RESYN8789_BDD8790\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8777_BDD8778\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8775_BDD8776\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8773_BDD8774\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8771_BDD8772\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8769_BDD8770\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8767_BDD8768\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_INTR0_CS_RESYN8755_BDD8756\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SOCCFG_CS_RESYN8753_BDD8754\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~5_RESYN8749_BDD8750\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~5_RESYN8745_BDD8746\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_RESYN8739_BDD8740\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~76_RESYN8725_BDD8726\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~5_RESYN8715_BDD8716\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8711_BDD8712\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8709_BDD8710\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8707_BDD8708\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8705_BDD8706\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8703_BDD8704\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8701_BDD8702\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8699_BDD8700\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8697_BDD8698\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8695_BDD8696\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8693_BDD8694\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8691_BDD8692\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8689_BDD8690\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8687_BDD8688\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_RESYN8685_BDD8686\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_RESYN8683_BDD8684\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8681_BDD8682\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8679_BDD8680\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8677_BDD8678\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8675_BDD8676\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8673_BDD8674\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_RESYN8671_BDD8672\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_RESYN8669_BDD8670\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_RESYN8667_BDD8668\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_RESYN8665_BDD8666\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_RESYN8663_BDD8664\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8661_BDD8662\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8659_BDD8660\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8657_BDD8658\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~94_RESYN8655_BDD8656\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8651_BDD8652\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8649_BDD8650\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8647_BDD8648\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[21]~1_RESYN8641_BDD8642\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[21]~1_RESYN8639_BDD8640\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_BDD8636\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_RESYN8633_BDD8634\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_RESYN8631_BDD8632\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_RESYN8623_BDD8624\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_RESYN8621_BDD8622\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~8_RESYN8629_BDD8630\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~6_RESYN8617_BDD8618\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~8_RESYN8615_BDD8616\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_RESYN8613_BDD8614\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_RESYN8605_BDD8606\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_RESYN8603_BDD8604\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~58_RESYN8601_BDD8602\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~48_RESYN8599_BDD8600\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~40_RESYN8597_BDD8598\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~31_RESYN8595_BDD8596\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector573~1_RESYN8589_BDD8590\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector507~1_RESYN8587_BDD8588\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector639~1_RESYN8583_BDD8584\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector771~2_RESYN8571_BDD8572\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_RESYN8497_BDD8498\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_RESYN8495_BDD8496\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~4_RESYN8493_BDD8494\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_RESYN8491_BDD8492\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_RESYN8489_BDD8490\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_RESYN8487_BDD8488\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_RESYN8483_BDD8484\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~4_RESYN8479_BDD8480\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_RESYN8475_BDD8476\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_RESYN8473_BDD8474\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8469_BDD8470\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8467_BDD8468\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_RESYN8465_BDD8466\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_RESYN8463_BDD8464\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8461_BDD8462\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8459_BDD8460\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~6_RESYN8457_BDD8458\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_RESYN8455_BDD8456\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_RESYN8453_BDD8454\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8449_BDD8450\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8447_BDD8448\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_RESYN8443_BDD8444\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8437_BDD8438\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8435_BDD8436\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8429_BDD8430\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_RESYN8427_BDD8428\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_RESYN8425_BDD8426\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_RESYN8423_BDD8424\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8413_BDD8414\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8411_BDD8412\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13466_BDD13467\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13464_BDD13465\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_RESYN13462_BDD13463\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_RESYN8941_RESYN13460_BDD13461\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8937_RESYN13458_BDD13459\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_INT_ENABLE[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_INT_ENABLE[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_VALID~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_RESET_TIMER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[34]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[38]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[26]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[30]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[35]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[32]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[48]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[37]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[42]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[40]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[52]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[44]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[47]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[49]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[30]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[25]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[31]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[29]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[27]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[26]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[28]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[25]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[26]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[7]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[10]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_RESET_TIMER[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[13]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[12]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[19]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[20]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[22]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount[3]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~131_Duplicate_173\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~111_Duplicate_170\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~127_Duplicate_167\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~95_Duplicate_161\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~99_Duplicate_158\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_155\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~65_Duplicate_152\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[0]_OTERM1619\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]_OTERM1617\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]_OTERM1615\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1607\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1605\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]_OTERM1603\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]_OTERM1601\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]_OTERM1599\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]_OTERM1597\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[1]_OTERM1587\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[1]_OTERM1585\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]_OTERM1583\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]_OTERM1581\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]_OTERM1573\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]_OTERM1571\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[15]_OTERM1569\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1567\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1565\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1563\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1561\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[1]_OTERM1559\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1557\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1555\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1553\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1551\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1549\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1547\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1545\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1543\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1541\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1539\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1537\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[1]_OTERM1535\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1533\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1531\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1527\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]_OTERM1497\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]_OTERM1495\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1485\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1483\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1481\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1479\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1477\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1475\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1473\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1471\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]_OTERM1447\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]_OTERM1445\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1437\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1429\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1427\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1425\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1423\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1421\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]_OTERM1411\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]_OTERM1409\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]_OTERM1401\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]_OTERM1399\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[20]_OTERM1389\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[20]_OTERM1387\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1385\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1383\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1379\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]_OTERM1377\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]_OTERM1375\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1357\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1355\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1353\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1351\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1349\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1347\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1345\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1343\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1341\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1339\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1337\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1335\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1333\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1331\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1329\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1327\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1325\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1323\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1321\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1319\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1317\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1315\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1313\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1309\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1307\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1305\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1283\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1281\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1279\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1277\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1275\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1271\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1269\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1267\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1265\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1263\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1261\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1259\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1255\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1253\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1251\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[9]_OTERM1249\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[7]_OTERM1247\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[5]_OTERM1245\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[6]_OTERM1243\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[12]_OTERM1241\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[16]_OTERM1239\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[17]_OTERM1237\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[18]_OTERM1235\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[19]_OTERM1233\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1231\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1229\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[11]_OTERM1227\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[4]_OTERM1225\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[1]_OTERM1223\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[8]_OTERM1221\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[21]_OTERM1215\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[20]_OTERM1213\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1205\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1199\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1197\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1195\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1193\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1191\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1189\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1187\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1185\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1183\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1181\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]_OTERM1179\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]_OTERM1177\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[22]_OTERM1175\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1173\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1169\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_END_OTERM1145\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_END_OTERM1143\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]_OTERM1141\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]_OTERM1139\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]_OTERM1137\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]_OTERM1135\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]_OTERM1133\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]_OTERM1131\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1119\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1116\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1114\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1112\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]_OTERM1106\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]_OTERM1104\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]_OTERM1102\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]_OTERM1100\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]_OTERM1092\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]_OTERM1090\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]_OTERM1088\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]_OTERM1086\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1084\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1082\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1080\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1078\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1076\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1074\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]_OTERM1072\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]_OTERM1070\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM998\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM996\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM994\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM992\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM990\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM988\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[29]_OTERM970\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]_OTERM936\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]_OTERM934\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[16]_OTERM932\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[16]_OTERM930\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[7]_OTERM928\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[7]_OTERM926\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]_OTERM924\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]_OTERM922\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]_OTERM920\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]_OTERM918\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]_OTERM916\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]_OTERM914\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM912\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM910\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM908\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM906\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[26]_OTERM904\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM902\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM900\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM898\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM896\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM894\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM892\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM890\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[17]_OTERM888\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[17]_OTERM886\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM882\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM880\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM878\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM876\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM874\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM872\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM870\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]_OTERM868\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]_OTERM866\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]_OTERM864\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]_OTERM862\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]_OTERM860\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]_OTERM858\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]_OTERM856\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]_OTERM854\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]_OTERM852\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]_OTERM850\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]_OTERM848\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]_OTERM846\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]_OTERM844\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]_OTERM842\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]_OTERM840\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]_OTERM838\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]_OTERM836\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]_OTERM834\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]_OTERM832\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]_OTERM830\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]_OTERM828\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]_OTERM826\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]_OTERM824\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]_OTERM822\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]_OTERM820\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]_OTERM818\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]_OTERM816\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]_OTERM814\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]_OTERM812\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]_OTERM810\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM808\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM806\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM800\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM798\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM796\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM792\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM790\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM788\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM784\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM782\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM780\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM778\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM776\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM774\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM772\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]_OTERM770\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]_OTERM768\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]_OTERM766\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]_OTERM764\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]_OTERM762\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]_OTERM760\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]_OTERM758\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]_OTERM756\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM754\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM750\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM746\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM743\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM741\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM737\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM734\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM732\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM728\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM725\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM723\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM719\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM715\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM713\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM709\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[26]_OTERM707\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[26]_OTERM705\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM703\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM701\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM699\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM697\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM695\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM693\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM691\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM689\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM687\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM685\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM683\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM681\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM679\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM677\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM675\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM673\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM671\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM669\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM667\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM665\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM663\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM661\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM659\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM657\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM655\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM651\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM649\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM647\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM645\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM643\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM641\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM639\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM637\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM635\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM633\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM631\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM629\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM627\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM625\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM623\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM621\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM619\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM617\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM615\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM613\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM611\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM609\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM607\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM605\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM603\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM601\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM599\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM597\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM595\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM593\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM591\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM589\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM587\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM585\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM583\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM581\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM579\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM577\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM575\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM573\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM571\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM569\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM567\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM565\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM563\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM561\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM559\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM557\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM555\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM553\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM551\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM549\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM547\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM545\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM543\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM541\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM539\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM537\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM535\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM533\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM531\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM529\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM527\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM525\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM523\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM521\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM519\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM517\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM515\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM513\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM511\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM507\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM499\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM497\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM495\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM491\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM489\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM487\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM485\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM483\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM481\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM479\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM477\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM475\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM473\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM471\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM469\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM467\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM465\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM463\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM461\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM459\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM457\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM455\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM453\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM451\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM449\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM447\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM445\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM443\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM435\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM433\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM431\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM429\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM427\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM425\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM423\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM421\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM417\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM415\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM413\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM411\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM409\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM407\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM405\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM403\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM401\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM399\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM397\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM395\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM393\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM391\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM389\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM387\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM385\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM383\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM381\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM379\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM373\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM371\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM369\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM367\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA[0]_OTERM363\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM361\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM359\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM357\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM355\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM353\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM351\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM349\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM347\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM345\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM343\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM341\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM339\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM337\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM335\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM333\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM329\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM327\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM325\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM323\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM317\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM313\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM311\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM309\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM307\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM305\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM303\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM301\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM299\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM297\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM295\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM293\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM291\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM289\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM287\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM285\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM283\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM279\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM277\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM275\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM273\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM271\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM269\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM265\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM263\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM261\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM257\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM255\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM253\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM249\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM247\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM245\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM243\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM241\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM239\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM237\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM235\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM231\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM229\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM227\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM223\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM165\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM163\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM161\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM159\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM157\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM155\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]_OTERM151\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]_OTERM149\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM145\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM143\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM141\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM139\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM137\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM135\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM133\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM131\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM129\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM127\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM125\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM123\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM121\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM119\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM117\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM115\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM113\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM111\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM109\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM103\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[12]_OTERM101\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[13]_OTERM99\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[14]_OTERM97\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[15]_OTERM95\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM93\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM91\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM89\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector77~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\ : std_logic_vector(63 DOWNTO 1);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux316~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux316~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux370~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux370~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux340~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux340~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux402~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux402~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux118~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux118~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux54~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux54~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux182~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux182~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux246~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux246~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux312~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux312~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux366~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux366~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux336~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux336~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux398~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux398~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux114~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux114~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux50~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux50~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux178~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux178~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux242~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux242~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\ : std_logic_vector(63 DOWNTO 1);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1455~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1455~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1391~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\ : std_logic_vector(30 DOWNTO 1);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1571~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1571~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1453~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1453~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector79~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux318~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux318~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux372~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux372~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux342~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux342~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux404~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux404~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux120~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux120~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux56~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux56~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux184~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux184~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux248~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux248~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector75~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux314~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux314~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux368~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux368~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux338~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux338~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux400~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux400~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux116~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux116~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux52~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux52~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux180~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux180~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux244~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux244~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1457~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1457~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1393~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1573~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1573~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1452~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1452~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1388~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector78~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux317~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux317~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux371~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux371~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux341~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux341~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux403~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux403~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux119~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux119~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux55~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux55~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux183~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux183~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux247~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux247~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux313~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux313~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux367~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux367~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux337~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux337~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux399~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux399~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux115~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux115~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux51~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux51~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux179~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux179~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux243~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux243~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1456~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1456~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1392~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1572~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1572~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\ : std_logic_vector(16 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\ : std_logic_vector(4 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1377~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\ : std_logic_vector(47 DOWNTO 1);
-SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_WRITE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~23_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\ : std_logic_vector(24 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\ : std_logic_vector(16 DOWNTO 0);
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][20]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][19]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][18]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][14]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][17]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][22]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][24]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][25]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][26]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][16]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][15]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][27]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][23]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][21]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][29]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][28]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][31]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][30]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_TIMER_REG_REQ~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\ : std_logic_vector(16 DOWNTO 8);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector117~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector76~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux315~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux315~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux369~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux369~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux339~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux339~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux401~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux401~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux117~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux117~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux53~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux53~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux181~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux181~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux245~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux245~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1454~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1454~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux311~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux311~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux365~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux365~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux335~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux335~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux397~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux397~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux113~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux113~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux49~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux49~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux177~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux177~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux241~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux241~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1450~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1450~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1386~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux308~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux308~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux362~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux362~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux332~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux332~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux394~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux394~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux110~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux110~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux46~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux46~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux304~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux304~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux358~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux358~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux328~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux328~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux390~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux390~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux106~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux106~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux42~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux42~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux170~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux170~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux234~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux234~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux310~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux310~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux364~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux364~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux334~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux334~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux396~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux396~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux112~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux112~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux48~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux48~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux176~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux176~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux240~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux240~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\ : std_logic_vector(63 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux306~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux306~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux360~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux360~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux330~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux330~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux392~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux392~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux108~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux108~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux44~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux44~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux172~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux172~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux236~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux236~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1449~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1449~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1385~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[62]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux309~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux309~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux363~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux363~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux333~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux333~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux395~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux395~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux111~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux111~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux47~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux47~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux305~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux305~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux359~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux359~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux329~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux329~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux391~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux391~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux107~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux107~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux43~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux43~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux171~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux171~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux235~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux235~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux208~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux208~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux272~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux272~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1481~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1417~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]~81_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector99~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux140~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux140~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux76~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux76~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux204~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux204~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux268~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux268~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1477~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1535~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1535~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~79_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector102~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux79~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux79~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector98~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux139~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux139~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux75~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux75~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux203~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux203~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux267~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux267~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1476~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1476~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1534~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1534~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1478~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1536~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1536~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector100~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux141~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux141~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux77~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux77~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux205~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux205~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux269~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux269~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector96~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux137~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux137~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux73~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux73~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux201~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux201~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux265~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux265~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1474~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1474~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1532~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1532~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector93~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux134~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux134~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux70~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux70~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux198~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux198~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux262~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux262~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1471~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1471~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1529~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1529~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1585~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]~73_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector89~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux130~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux130~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux66~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux66~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux194~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux194~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux258~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux258~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1467~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1467~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector95~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux136~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux136~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux72~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux72~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux200~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux200~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux264~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux264~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1473~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1473~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1531~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1531~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]~71_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector91~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux132~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux132~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux68~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux68~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux196~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux196~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux260~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux260~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\ : std_logic_vector(33 DOWNTO 3);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1469~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1469~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector94~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux135~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux135~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux71~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux71~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux199~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux199~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux263~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux263~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1472~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1472~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1530~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1530~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector90~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux131~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux131~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux67~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux67~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux195~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux195~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux259~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux259~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1468~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1468~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~25_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector115~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector92~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux133~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux133~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux69~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux69~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux197~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux197~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux261~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux261~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1470~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1470~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector88~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux129~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux129~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux65~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux65~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux193~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux193~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux257~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux257~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1466~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1466~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector85~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux126~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux126~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux62~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux62~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1399~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector81~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux320~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux320~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux374~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux374~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux344~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux344~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux406~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux406~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux122~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux122~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux58~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux58~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux186~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux186~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux250~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux250~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1459~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1459~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1575~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1575~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector87~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux128~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux128~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux64~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux64~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux192~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux192~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux256~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux256~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1465~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1465~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector83~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux322~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux322~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux408~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux408~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux376~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux376~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux124~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux124~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux60~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux60~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux188~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux188~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux252~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux252~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1461~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1577~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1577~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector86~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux127~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux127~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux63~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux63~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1400~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector82~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux321~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux321~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux375~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux375~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux345~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux345~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux407~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux407~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux123~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux123~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux59~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux59~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux187~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux187~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux251~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux251~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1460~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1460~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1576~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1576~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[40]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[40]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~24_q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_index\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux409~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux409~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux377~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux377~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux125~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux125~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux61~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux61~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux189~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux189~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux253~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux253~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector84~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux323~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux323~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1578~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1578~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector80~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux319~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux319~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux373~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux373~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux343~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux343~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux405~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux405~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux121~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux121~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux57~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux57~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux185~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux185~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux249~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux249~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1458~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1458~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1574~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1574~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1451~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1451~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM87\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM85\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM83\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM81\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM79\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[16]_OTERM77\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]_OTERM75\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]_OTERM73\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[20]_OTERM71\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]_OTERM69\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[17]_OTERM67\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]_OTERM65\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[19]_OTERM63\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM61\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM59\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM57\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM55\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[9]_OTERM53\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[10]_OTERM51\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[11]_OTERM49\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM47\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM45\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM43\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM41\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[8]_OTERM39\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM37\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM35\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM33\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM31\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM29\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM27\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM25\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM23\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM21\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM19\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM17\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM15\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM11\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM9\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\ : std_logic;
-SIGNAL \mypll|altpll_component|auto_generated|ALT_INV_wire_generic_pll1_locked\ : std_logic;
-SIGNAL \ALT_INV_UART_RX_1~input_o\ : std_logic;
-SIGNAL \ALT_INV_UART_RX_0~input_o\ : std_logic;
-SIGNAL \ALT_INV_SDCARD_MISO[0]~input_o\ : std_logic;
-SIGNAL \ALT_INV_KEY~input_o\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~438_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~436_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~435_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~160_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~166_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~165_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~434_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~432_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~164_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector214~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector213~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector212~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector211~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector210~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector209~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector208~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector207~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector206~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector205~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector203~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector202~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector201~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector199~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector198~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector197~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector196~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector195~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector194~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector193~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~157_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~156_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~155_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~152_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~150_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~149_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector157~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector157~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[3]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector154~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[5]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[9]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[11]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[13]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[15]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[16]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1561~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1561~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1563~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1563~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1506~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1562~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1562~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1508~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1564~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1564~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR:tInsnExec~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux428~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1560~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1560~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux425~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1557~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1557~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1497~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1497~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1503~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1559~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1559~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1499~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1499~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1502~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1558~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1558~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1498~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1498~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1500~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1500~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1496~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1496~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux282~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux282~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux154~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux154~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux90~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux90~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux218~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux218~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1491~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1427~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1495~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1495~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add40~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux284~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux284~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux156~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux156~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux92~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux92~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1493~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux283~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux283~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux155~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux155~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux91~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux91~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux219~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux219~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1548~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1548~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux93~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux93~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux285~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux285~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux157~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux157~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux221~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux221~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1494~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux418~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux418~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1550~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1550~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux153~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux153~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux89~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux89~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux217~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux217~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux281~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux281~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1546~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1546~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux150~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux150~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux86~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux86~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux214~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux214~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux278~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux278~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1487~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1599~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[3]~98_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[3]~97_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux146~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux146~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux82~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux82~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux210~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux210~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux274~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux274~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1483~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux152~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux152~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux88~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux88~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux216~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux216~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux280~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux280~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1489~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1425~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux148~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux148~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux84~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux84~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux212~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux212~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux276~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux276~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1485~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1421~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux151~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux151~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux87~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux87~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux215~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux215~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux279~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux279~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1544~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1544~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[2]~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[2]~91_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux147~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux147~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux83~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux83~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux211~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux211~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux275~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux275~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux149~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux149~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux85~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux85~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux213~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux213~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux277~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux277~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[4]~87_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector104~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux145~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux145~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux81~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux81~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux209~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux209~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux273~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux273~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector101~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux142~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux142~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux78~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux78~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1415~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector97~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux138~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux138~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux74~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux74~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux202~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux202~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux266~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux266~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1475~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1475~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1533~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1533~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[5]~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector103~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux144~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux144~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux80~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux80~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~22_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~19_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\ : std_logic_vector(24 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\ : std_logic_vector(8 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~19_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\ : std_logic_vector(24 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\ : std_logic_vector(8 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~18_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~18_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescaled_tick~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\ : std_logic_vector(10 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector300~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector298~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector295~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector297~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_PreSetAddr~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux307~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux307~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux361~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux361~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux331~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux331~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux393~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux393~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux109~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux109~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux45~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux45~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux173~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux173~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux237~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux237~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux303~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux303~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux357~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux357~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux327~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux327~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux389~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux389~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux105~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux105~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux41~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux41~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux169~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux169~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux233~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux233~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux350~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux350~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux290~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux290~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux382~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux382~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux296~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux296~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux98~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux98~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux34~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux34~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux162~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux162~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux226~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux226~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux300~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux300~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux354~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux354~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux324~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux324~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux386~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux386~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux102~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux102~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux38~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux38~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux166~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux166~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux230~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux230~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux352~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux352~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux292~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux292~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux384~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux384~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux298~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux298~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux100~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux100~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux36~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux36~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux164~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux164~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux228~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux228~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux302~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux302~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux356~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux356~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux326~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux326~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux388~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux388~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux104~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux104~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux40~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux40~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux168~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux168~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux232~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux232~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux351~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux351~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux291~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux291~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux383~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux383~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux297~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux297~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux99~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux99~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux35~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux35~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux163~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux163~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux227~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux227~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux301~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux301~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux355~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux355~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux325~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux325~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux387~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux387~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux103~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux103~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux39~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux39~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux167~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux167~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux231~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux231~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 1);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Decoder0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 1);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~21_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~98_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FULL_V~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FULL_V~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~97_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~96_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~147_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~144_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~142_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~137_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_EMPTY_V~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_EMPTY_V~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~91_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~89_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~135_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~130_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~129_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~128_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~122_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~121_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~120_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~113_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~112_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][24]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[24]~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][27]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][26]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][25]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~99_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~98_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~97_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~96_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~91_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_TICK_HALT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal3~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal3~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_process_3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_process_3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_ticks\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][31]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][30]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][29]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][28]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1349~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~104_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~102_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~157_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~156_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~155_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~154_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~152_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~149_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal131~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~79_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux133~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux135~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal67~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~71_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal46~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal99~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux121~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux123~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~146_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~145_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~144_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~143_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~141_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~140_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~139_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~138_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~136_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~135_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~134_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~133_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~131_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~130_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~129_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~128_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~126_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~125_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~124_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~123_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~121_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~120_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~119_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~118_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~116_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~115_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~114_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~113_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~111_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~110_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~109_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~108_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~106_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~105_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~104_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~103_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~101_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~100_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~99_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~98_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~96_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~95_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~94_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~93_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~91_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~90_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~89_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~88_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~73_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector120~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector120~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector52~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector52~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector48~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector48~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector45~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector47~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector47~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector46~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SEPERATOR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_CRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector13~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector111~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector14~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[45]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[45]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal6~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal6~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~19_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[0]~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[1]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[1]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[1]~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[1]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[1]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[0]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector573~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~79_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~21_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal3~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal3~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~21_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector355~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~92_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\ : std_logic_vector(17 DOWNTO 4);
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~73_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~25_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~25_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~71_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_OVERRUN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~24_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~24_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector352~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~23_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~23_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector353~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_process_1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add9~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\ : std_logic_vector(4 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_process_1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_process_1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_process_1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_process_1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_process_1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_Add7~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal13~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal35~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal35~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal35~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal35~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal35~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal35~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal35~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal35~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal36~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal36~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~17_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~22_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal2~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal2~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~17_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~22_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal2~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal2~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector354~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal34~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal34~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal34~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal34~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal34~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_RESET~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal33~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal33~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal33~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal33~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal32~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal32~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal32~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal32~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal32~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal31~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal31~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal31~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal31~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal31~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal31~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal30~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal30~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_MemoryFetch~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_0~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\ : std_logic_vector(16 DOWNTO 11);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_0~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr128~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1659~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~160_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugOutputOnce~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add59~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add61~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_INT_DONE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\ : std_logic_vector(30 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddrPause~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddr~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector119~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector119~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux353~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux353~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux293~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux293~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux385~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux385~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux299~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux299~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux101~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux101~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux37~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux37~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux165~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux165~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux229~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux229~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux349~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux349~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux289~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux289~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux381~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux381~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux295~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux295~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux97~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux97~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux33~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux33~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux161~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux161~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux225~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux225~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector49~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector49~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux378~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux378~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux286~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux286~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux94~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux94~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux30~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux30~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux346~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux346~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector51~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector51~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux348~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux348~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux288~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux288~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux380~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux380~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux294~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux294~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux96~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux96~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux32~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux32~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux160~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux160~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux224~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux224~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector50~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector50~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux379~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux379~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux287~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux287~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux95~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux95~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux31~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux31~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux347~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux347~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux8~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux14~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector507~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector639~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector771~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector503~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector701~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector701~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector635~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector899~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector568~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector502~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1115~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1115~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1083~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1083~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector500~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector500~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1179~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1179~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector698~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector698~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1147~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1147~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector632~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector632~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1307~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1307~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector962~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector962~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1275~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1275~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector896~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector896~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector830~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector830~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector565~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector565~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[25]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~74_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~73_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\ : std_logic_vector(20 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~69_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_OVERRUN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_OVERRUN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~68_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[3]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[3]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[3]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[3]~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[3]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[3]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[3]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[8]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux75~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[8]~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux264~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\ : std_logic_vector(11 DOWNTO 4);
-SIGNAL \myVirtualToplevel|ALT_INV_INT_ENABLE\ : std_logic_vector(11 DOWNTO 4);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]~55_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~61_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~60_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~57_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_RESET~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_RESET~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[7]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[7]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[7]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[7]~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[7]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[7]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[7]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[7]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_OVERRUN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[6]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[6]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[6]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[6]~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[6]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[6]~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[6]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[6]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[11]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[11]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[11]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[11]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[11]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[11]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[11]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[11]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[10]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux73~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[11]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[10]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[10]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[10]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[10]~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[10]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[10]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[10]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[10]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[9]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux74~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[9]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux263~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux267~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux267~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[5]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[5]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[5]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[5]~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[5]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[5]~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[5]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[5]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM0_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux92~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux268~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux268~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_INTR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_INTR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[4]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[4]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[4]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[4]~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[4]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[4]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[4]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[4]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[15]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][15]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[15]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[15]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[15]~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[15]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[15]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[15]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[15]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[14]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][14]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[14]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[14]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[14]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[14]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[14]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[14]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[14]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[13]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[13]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[13]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[13]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[13]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[13]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[13]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[13]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[13]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[12]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM1_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[12]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[12]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[12]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[12]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[12]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[12]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[12]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[12]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[12]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[19]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Mux86~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][19]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[19]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[19]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[19]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[19]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[19]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[19]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[19]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[19]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][18]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_BUSY~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_BUSY~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[18]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[18]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[18]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[18]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[18]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[18]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[18]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[18]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][17]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal6~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal6~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[17]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[17]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[17]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[17]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[17]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[17]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[17]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[17]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[17]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][23]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[23]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[23]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[23]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[23]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[23]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[23]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[23]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[20]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][20]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[20]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[20]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[20]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[20]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[20]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[20]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[20]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[20]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][22]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE_FIFO~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[22]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[22]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[22]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[22]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[22]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[22]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_ADDR[0][21]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[21]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[21]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[21]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[21]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[21]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[21]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[21]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[21]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[16]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM2_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_LessThan3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal5~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal5~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal5~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal5~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal153~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugAllInfo~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_StartAddr\ : std_logic_vector(16 DOWNTO 16);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[16]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[16]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[16]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[16]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[16]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[16]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[16]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\ : std_logic_vector(7 DOWNTO 1);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\ : std_logic_vector(4 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_WR\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_SD_RD\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\ : std_logic_vector(6 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_RESET\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_RESET~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RESET_n~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQM\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR\ : std_logic_vector(10 DOWNTO 10);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_cs_bo~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TXD~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TXD~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux28~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~143_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~139_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~135_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~115_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~65_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~116_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~108_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ~104_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~116_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~112_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~108_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~104_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~165_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[44]~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~161_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1464~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1463~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1416~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1417~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1421~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1425~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1432~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1427~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\ : std_logic_vector(5 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA4~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA3~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~735_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~731_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~727_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~723_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~719_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~715_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~711_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][20]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][14]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][17]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][22]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][24]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][25]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][26]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][16]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][27]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][23]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][21]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][29]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][28]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][30]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~707_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM195\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM197\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM199\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM201\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM203\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM205\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM207\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM209\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM211\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM213\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM215\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM217\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM219\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM221\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~125_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~121_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~117_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~113_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux3~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux5~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux21~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux20~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux23~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux22~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux29~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux28~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux26~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux27~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux25~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux24~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux4~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~136_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~125_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~125_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~121_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~121_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~132_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~36_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~117_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~128_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~117_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~113_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~113_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~124_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\ : std_logic_vector(27 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~120_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~109_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~105_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~116_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~101_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~112_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~108_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~97_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~362_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~354_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~350_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~346_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~342_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\ : std_logic_vector(60 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\ : std_logic_vector(61 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM167\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM169\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM171\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM173\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM175\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM177\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM179\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM181\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM183\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM185\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM187\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM189\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM191\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM193\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux21~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux20~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux23~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux22~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux29~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux28~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux26~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux27~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux25~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux24~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\ : std_logic_vector(16 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~103_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~98_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~31_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~94_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add2~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add2~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~80_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~75_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~71_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~66_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_Add11~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\ : std_logic_vector(27 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add5~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add5~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~52_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector245~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS_2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector114~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector121~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector121~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTCRLF~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_WideOr18~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector216~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux93~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector63~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_WRITE[7]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_VALID~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector15~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector15~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector15~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector15~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector15~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector15~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector15~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_ACMD41_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_CMD0_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[46]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_BLK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~17_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~18_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\ : std_logic_vector(10 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\ : std_logic_vector(23 DOWNTO 1);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector18~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector203~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector198~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~26_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector199~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector193~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_LessThan0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector195~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr116~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|ALT_INV_l1_w0_n0_mux_dataout~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_INTR0_CS~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr2~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\ : std_logic_vector(10 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_READ_ENABLE_LAST~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_CS~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_CS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_UART1_CS~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_TIMER0_CS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SOCCFG_CS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[11]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDoneLast~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn[21]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~0_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_LessThan0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_BRAM_WREN~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuLastEN~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~81_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~80_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~78_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~77_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~76_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD0~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~75_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD41~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~72_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD55~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~70_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WAIT_FOR_HOST_RW~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.GET_CMD8_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~67_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~66_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_WAIT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_STD_MATCH~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~62_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~59_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~58_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[4]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal4~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.RD_BLK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o[3]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~54_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~52_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.START_INIT~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~51_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnData_v~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Selector20~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_DATA_VALID~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\ : std_logic_vector(6 DOWNTO 0);
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector21~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal8~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\ : std_logic_vector(6 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_SD_CHANNEL~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~44_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector87~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector66~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector67~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector69~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~43_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~42_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_doDeselect_v~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal5~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal5~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal5~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Equal5~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_UART0_CS~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal3~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal3~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\ : std_logic;
-SIGNAL \ALT_INV_reset~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RESET_n~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal12~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RESET_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_Equal12~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal11~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal11~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Equal11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_Equal11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\ : std_logic_vector(11 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal2~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\ : std_logic_vector(3 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux11~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux7~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux18~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~36_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~32_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~30_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[26]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[18]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr171~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tIdx~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_intTriggered~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inInterrupt~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~47_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~43_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~39_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~35_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~30_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~26_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~22_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~18_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~14_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~10_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~6_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\ : std_logic_vector(17 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\ : std_logic_vector(23 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add6~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_INTR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_TX_INTR~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add10~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~93_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~89_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\ : std_logic_vector(31 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ALT_INV_Add0~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add0~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add0~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add0~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add0~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add0~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\ : std_logic_vector(23 DOWNTO 2);
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_Add6~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~85_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~81_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~77_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~73_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~69_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~65_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~61_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~57_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~53_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~49_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add2~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~45_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~41_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~37_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~33_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~17_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~29_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~25_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~21_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~13_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~9_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~5_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~1_sumout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\ : std_logic_vector(15 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][10]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][9]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][7]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][6]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][8]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][5]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][4]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][3]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][2]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][1]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][0]~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\ : std_logic_vector(7 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\ : std_logic;
-SIGNAL \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\ : std_logic_vector(9 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux14~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux17~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\ : std_logic_vector(2 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux12~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux12~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux9~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux9~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux15~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux18~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux18~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux13~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux13~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux10~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux10~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux16~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux19~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux19~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux1~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux1~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_DATA_PRTMODE\ : std_logic_vector(0 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_SPLIT_DATA\ : std_logic_vector(1 DOWNTO 0);
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT[2]~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_DATA~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_TX_FIFO~20_q\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector357~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~64_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~63_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~87_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~106_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~86_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~85_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~49_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~48_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~84_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~83_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector358~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~101_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~47_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~46_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~41_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~25_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~24_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~23_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~22_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~21_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~20_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~19_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~40_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~39_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~18_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~17_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~16_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~15_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr160~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~20_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~20_q\ : std_logic;
-SIGNAL \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|UART1|ALT_INV_Add9~29_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector356~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~1_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~0_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~14_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~13_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~82_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~12_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~11_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~10_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~9_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~8_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~7_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~6_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~5_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~4_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~3_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~2_combout\ : std_logic;
-SIGNAL \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~81_combout\ : std_logic;
-
-BEGIN
-
-ww_CLOCK_50 <= CLOCK_50;
-LEDR <= ww_LEDR;
-ww_KEY <= KEY;
-ww_SDCARD_MISO <= SDCARD_MISO;
-SDCARD_MOSI <= ww_SDCARD_MOSI;
-SDCARD_CLK <= ww_SDCARD_CLK;
-SDCARD_CS <= ww_SDCARD_CS;
-ww_UART_RX_0 <= UART_RX_0;
-UART_TX_0 <= ww_UART_TX_0;
-ww_UART_RX_1 <= UART_RX_1;
-UART_TX_1 <= ww_UART_TX_1;
-SDRAM_CLK <= ww_SDRAM_CLK;
-SDRAM_CKE <= ww_SDRAM_CKE;
-SDRAM_ADDR <= ww_SDRAM_ADDR;
-SDRAM_DQM <= ww_SDRAM_DQM;
-SDRAM_BA <= ww_SDRAM_BA;
-SDRAM_CS <= ww_SDRAM_CS;
-SDRAM_WE <= ww_SDRAM_WE;
-SDRAM_RAS <= ww_SDRAM_RAS;
-SDRAM_CAS <= ww_SDRAM_CAS;
-ww_devoe <= devoe;
-ww_devclrn <= devclrn;
-ww_devpor <= devpor;
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(0));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[0]~0_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[5]~1_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[4]~3_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[2]~6_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[3]~7_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[4]~0_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[5]~1_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[6]~2_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[7]~3_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[1]~4_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[2]~5_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[3]~6_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_DATA[0]~7_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
-& gnd & gnd & gnd & gnd & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0));
-
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(5) &
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(2) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0));
-
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|UART0|Add8~5_sumout\ & \myVirtualToplevel|UART0|Add8~1_sumout\ & \myVirtualToplevel|UART0|Add8~29_sumout\ & \myVirtualToplevel|UART0|Add8~25_sumout\
-& \myVirtualToplevel|UART0|Add8~21_sumout\ & \myVirtualToplevel|UART0|Add8~17_sumout\ & \myVirtualToplevel|UART0|Add8~13_sumout\ & \myVirtualToplevel|UART0|Add8~9_sumout\);
-
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(2));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(1);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[7]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[6]~1_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[5]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[4]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[3]~5_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[2]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[0]~4_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\
-& \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\
-& \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[1]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[0]~1_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\
-& \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6) &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\
-& \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[4]~0_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[5]~1_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[6]~2_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[7]~3_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[1]~4_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[2]~5_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[3]~6_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7_combout\;
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1);
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(8) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2));
-
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\ <= \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\(0);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTADATAIN_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(4));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4_PORTBDATAOUT_bus\(1);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ACLR_bus\ <= (gnd & gnd);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_CLK_bus\ <= (gnd & gnd & \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ENA_bus\ <= (vcc & vcc & \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AX_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AY_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(0) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(1) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(2) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(3) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(4) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(5) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(6) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(7) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(8) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(9) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(10) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(11) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(12) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(13) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(14) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(15) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(16) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult\(17) <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM191\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM189\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM187\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM185\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM183\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM181\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM179\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM177\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM175\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM173\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM171\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM169\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM167\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~40\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~41\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~42\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~43\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~44\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~45\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~46\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~47\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~48\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~49\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~50\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~51\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~52\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~53\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~54\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~55\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~56\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~57\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~58\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~59\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~60\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~61\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~62\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~63\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~64\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~65\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~66\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~67\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~68\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~69\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~70\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~71\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\(63);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_ACLR_bus\ <= (gnd & gnd);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_CLK_bus\ <= (gnd & gnd & \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_ENA_bus\ <= (vcc & vcc & \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1_combout\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_AX_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_AY_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_BX_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_BY_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ &
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM219\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM217\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM215\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM213\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM211\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM209\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM207\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM205\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM203\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM201\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM199\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM197\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM195\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~387\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~388\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~389\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~390\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~391\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~392\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~393\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~394\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~395\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~396\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~397\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~398\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~399\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~400\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~401\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~402\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~403\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~404\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~405\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~406\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~407\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~408\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~409\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~410\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~411\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~412\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~413\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~414\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~415\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~416\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~417\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~418\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~419\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~420\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~421\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~422\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~423\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~424\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~425\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~426\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~427\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~428\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~429\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~430\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~431\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~432\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~433\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~434\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~435\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~436\ <= \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~373_RESULTA_bus\(63);
-
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
-& gnd & gnd & gnd & gnd & \myVirtualToplevel|UART1|RX_BUFFER\(8) & \myVirtualToplevel|UART1|RX_BUFFER\(7) & \myVirtualToplevel|UART1|RX_BUFFER\(6) & \myVirtualToplevel|UART1|RX_BUFFER[5]~DUPLICATE_q\ &
-\myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\ & \myVirtualToplevel|UART1|RX_BUFFER\(3) & \myVirtualToplevel|UART1|RX_BUFFER\(2) & \myVirtualToplevel|UART1|RX_BUFFER\(1));
-
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) &
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0));
-
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|UART1|Add3~29_sumout\ & \myVirtualToplevel|UART1|Add3~21_sumout\ & \myVirtualToplevel|UART1|Add3~25_sumout\ & \myVirtualToplevel|UART1|Add3~1_sumout\
-& \myVirtualToplevel|UART1|Add3~13_sumout\ & \myVirtualToplevel|UART1|Add3~17_sumout\ & \myVirtualToplevel|UART1|Add3~9_sumout\ & \myVirtualToplevel|UART1|Add3~5_sumout\);
-
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);
-
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\ <= (gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd & gnd
-& gnd & gnd & gnd & gnd & \myVirtualToplevel|UART0|RX_BUFFER\(8) & \myVirtualToplevel|UART0|RX_BUFFER\(7) & \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_BUFFER\(5) &
-\myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_BUFFER\(1));
-
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\ <= (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) &
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) & \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) &
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\);
-
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\ <= (\myVirtualToplevel|UART0|Add3~21_sumout\ & \myVirtualToplevel|UART0|Add3~17_sumout\ & \myVirtualToplevel|UART0|Add3~29_sumout\ & \myVirtualToplevel|UART0|Add3~1_sumout\
-& \myVirtualToplevel|UART0|Add3~13_sumout\ & \myVirtualToplevel|UART0|Add3~25_sumout\ & \myVirtualToplevel|UART0|Add3~9_sumout\ & \myVirtualToplevel|UART0|Add3~5_sumout\);
-
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a1\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(1);
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a2\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(2);
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a3\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(3);
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a4\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(4);
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a5\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(5);
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a6\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(6);
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\(7);
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(6));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\ <= (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(6) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1) &
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0));
-
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6~portbdataout\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a7\ <= \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\(1);
-
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH0\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(0);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH1\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(1);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH2\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(2);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH3\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(3);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH4\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(4);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH5\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(5);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH6\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(6);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH7\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\(7);
-
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI0\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(0);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI1\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(1);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI2\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(2);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI3\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(3);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI4\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(4);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI5\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(5);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI6\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(6);
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI7\ <= \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\(7);
-
-\mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_CLKIN_bus\ <= (gnd & gnd & gnd & \CLOCK_50~input_o\);
-
-\mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_MHI_bus\ <= (\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI7\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI6\ &
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI5\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI4\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI3\ &
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI2\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI1\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_MHI0\);
-
-\mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTEN0\ <= \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_SHIFTEN_bus\(0);
-\mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIGSHIFTEN2\ <= \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_SHIFTEN_bus\(2);
-
-\mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER_VCO0PH_bus\ <= (\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH7\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH6\ &
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH5\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH4\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH3\ &
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH2\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH1\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH0\);
-
-\mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER_VCO0PH_bus\ <= (\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH7\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH6\ &
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH5\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH4\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH3\ &
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH2\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH1\ & \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_VCOPH0\);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM471~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[24]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[33]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[33]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause[7]~DUPLICATE_q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[43]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[43]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[31]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[28]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[28]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[17]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12948_BDD12949\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[12]_NEW2314_RESYN12946_BDD12947\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12944_BDD12945\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[8]_NEW2312_RESYN12942_BDD12943\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12940_BDD12941\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[8]_NEW2310_RESYN12938_BDD12939\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12936_BDD12937\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[8]_NEW2308_RESYN12934_BDD12935\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12932_BDD12933\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[10]_NEW2306_RESYN12930_BDD12931\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12928_BDD12929\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]_NEW2304_RESYN12926_BDD12927\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12924_BDD12925\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[10]_NEW2302_RESYN12922_BDD12923\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12920_BDD12921\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[6]_NEW2300_RESYN12918_BDD12919\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12916_BDD12917\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[9]_NEW2298_RESYN12914_BDD12915\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12912_BDD12913\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[9]_NEW2296_RESYN12910_BDD12911\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12908_BDD12909\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[9]_NEW2294_RESYN12906_BDD12907\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12904_BDD12905\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[5]_NEW2292_RESYN12902_BDD12903\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12900_BDD12901\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[11]_NEW2290_RESYN12898_BDD12899\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12896_BDD12897\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[11]_NEW2288_RESYN12894_BDD12895\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12892_BDD12893\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[11]_NEW2286_RESYN12890_BDD12891\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12888_BDD12889\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[7]_NEW2284_RESYN12886_BDD12887\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12884_BDD12885\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[4]_NEW2282_RESYN12882_BDD12883\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12880_BDD12881\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[0]_NEW2280_RESYN12878_BDD12879\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12876_BDD12877\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[2]_NEW2278_RESYN12874_BDD12875\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12872_BDD12873\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[1]_NEW2274_RESYN12870_BDD12871\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12868_BDD12869\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[3]_NEW2270_RESYN12866_BDD12867\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR_NEW2222_RESYN12864_BDD12865\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[1]_NEW2202_RESYN12862_BDD12863\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]_NEW2192_RESYN12860_BDD12861\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA_NEW2174_RESYN12858_BDD12859\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[22]_NEW2144_RESYN12856_BDD12857\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[21]_NEW2134_RESYN12854_BDD12855\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]_NEW2124_RESYN12852_BDD12853\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[20]_NEW2114_RESYN12850_BDD12851\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[16]_NEW2108_RESYN12848_BDD12849\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[18]_NEW2102_RESYN12846_BDD12847\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[14]_NEW2096_RESYN12844_BDD12845\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[17]_NEW2090_RESYN12842_BDD12843\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[13]_NEW2084_RESYN12840_BDD12841\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[19]_NEW2078_RESYN12838_BDD12839\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[15]_NEW2072_RESYN12836_BDD12837\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[8]_NEW2060_RESYN12832_BDD12833\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[12]_NEW2066_RESYN12834_BDD12835\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[6]_NEW2048_RESYN12828_BDD12829\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[9]_NEW2042_RESYN12826_BDD12827\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[5]_NEW2036_RESYN12824_BDD12825\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[10]_NEW2054_RESYN12830_BDD12831\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[7]_NEW2024_RESYN12820_BDD12821\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[4]_NEW2018_RESYN12818_BDD12819\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[2]_NEW2008_RESYN12816_BDD12817\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[3]_NEW1998_RESYN12814_BDD12815\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[11]_NEW2030_RESYN12822_BDD12823\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]_NEW1860_RESYN12810_BDD12811\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]_NEW1852_RESYN12808_BDD12809\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_RESYN12804_BDD12805\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_RESYN12804_BDD12805\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~23_RESYN12802_BDD12803\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_RESYN12802_BDD12803\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN12800_BDD12801\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12800_BDD12801\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12796_BDD12797\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12796_BDD12797\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12794_BDD12795\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12794_BDD12795\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_RESYN12792_BDD12793\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_RESYN12792_BDD12793\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_RESYN12790_BDD12791\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12790_BDD12791\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_RESYN12788_BDD12789\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_RESYN12788_BDD12789\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN12798_BDD12799\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN12798_BDD12799\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_RESYN12786_BDD12787\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_RESYN12786_BDD12787\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_RESYN12782_BDD12783\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12782_BDD12783\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_RESYN12780_BDD12781\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_RESYN12780_BDD12781\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_RESYN12778_BDD12779\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778_BDD12779\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12776_BDD12777\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12776_BDD12777\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12774_BDD12775\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12774_BDD12775\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~10_RESYN12772_BDD12773\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_RESYN12772_BDD12773\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_RESYN12770_BDD12771\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_RESYN12770_BDD12771\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_RESYN12768_BDD12769\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12766_BDD12767\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12766_BDD12767\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12764_BDD12765\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12764_BDD12765\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_RESYN12762_BDD12763\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_RESYN12762_BDD12763\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~5_RESYN12760_BDD12761\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~5_RESYN12760_BDD12761\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~104_RESYN12758_BDD12759\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_RESYN12758_BDD12759\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~5_RESYN12756_BDD12757\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_RESYN12756_BDD12757\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~4_RESYN12754_BDD12755\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_RESYN12754_BDD12755\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_RESYN12752_BDD12753\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_RESYN12752_BDD12753\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_RESYN12750_BDD12751\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12750_BDD12751\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_RESYN12748_BDD12749\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_RESYN12748_BDD12749\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~3_RESYN12746_BDD12747\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_RESYN12746_BDD12747\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~7_RESYN12744_BDD12745\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~7_RESYN12744_BDD12745\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~1_RESYN12742_BDD12743\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_RESYN12742_BDD12743\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_RESYN12740_BDD12741\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_RESYN12740_BDD12741\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_RESYN12738_BDD12739\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_RESYN12738_BDD12739\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_RESYN12736_BDD12737\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_RESYN12736_BDD12737\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_RESYN12734_BDD12735\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_RESYN12734_BDD12735\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_RESYN12732_BDD12733\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_RESYN12732_BDD12733\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_RESYN12730_BDD12731\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_RESYN12730_BDD12731\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_RESYN12728_BDD12729\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_RESYN12728_BDD12729\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_RESYN12726_BDD12727\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_RESYN12726_BDD12727\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136_RESYN12724_BDD12725\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136_RESYN12724_BDD12725\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12722_BDD12723\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12722_BDD12723\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12720_BDD12721\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12720_BDD12721\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~153_RESYN12718_BDD12719\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~153_RESYN12718_BDD12719\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~0_RESYN12716_BDD12717\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_RESYN12716_BDD12717\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_RESYN12714_BDD12715\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_RESYN12714_BDD12715\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_RESYN12712_BDD12713\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_RESYN12712_BDD12713\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_RESYN12710_BDD12711\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_RESYN12710_BDD12711\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_RESYN12708_BDD12709\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_RESYN12708_BDD12709\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_RESYN12706_BDD12707\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706_BDD12707\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_RESYN12704_BDD12705\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_RESYN12702_BDD12703\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_RESYN12702_BDD12703\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_RESYN12700_BDD12701\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_RESYN12700_BDD12701\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_RESYN12698_BDD12699\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_RESYN12698_BDD12699\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_RESYN12696_BDD12697\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_RESYN12696_BDD12697\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_RESYN12694_BDD12695\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_RESYN12694_BDD12695\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_RESYN12692_BDD12693\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_RESYN12692_BDD12693\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_RESYN12690_BDD12691\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690_BDD12691\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_RESYN12688_BDD12689\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~60_RESYN12686_BDD12687\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_RESYN12686_BDD12687\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~43_RESYN12684_BDD12685\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_RESYN12684_BDD12685\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~35_RESYN12682_BDD12683\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_RESYN12682_BDD12683\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~25_RESYN12680_BDD12681\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_RESYN12680_BDD12681\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_RESYN12678_BDD12679\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678_BDD12679\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_RESYN12676_BDD12677\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_RESYN12676_BDD12677\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_RESYN12674_BDD12675\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_RESYN12674_BDD12675\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_RESYN12672_BDD12673\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_RESYN12670_BDD12671\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670_BDD12671\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12668_BDD12669\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12666_BDD12667\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12664_BDD12665\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~3_RESYN12662_BDD12663\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12660_BDD12661\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12658_BDD12659\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12656_BDD12657\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~4_RESYN12654_BDD12655\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_RESYN12652_BDD12653\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_RESYN12652_BDD12653\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_RESYN12644_BDD12645\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644_BDD12645\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_RESYN12642_BDD12643\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_RESYN12642_BDD12643\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_RESYN12640_BDD12641\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_RESYN12638_BDD12639\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12638_BDD12639\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_RESYN12636_BDD12637\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_RESYN12636_BDD12637\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~6_RESYN12634_BDD12635\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_RESYN12634_BDD12635\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_RESYN12632_BDD12633\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN12632_BDD12633\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_RESYN12628_BDD12629\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628_BDD12629\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_RESYN12626_BDD12627\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_RESYN12626_BDD12627\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_RESYN12624_BDD12625\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624_BDD12625\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_RESYN12622_BDD12623\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_RESYN12620_BDD12621\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_RESYN12620_BDD12621\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_RESYN12618_BDD12619\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_RESYN12614_BDD12615\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12614_BDD12615\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_RESYN12612_BDD12613\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_RESYN12612_BDD12613\;
-\myVirtualToplevel|ALT_INV_MEM_BUSY~1_RESYN12610_BDD12611\ <= NOT \myVirtualToplevel|MEM_BUSY~1_RESYN12610_BDD12611\;
-\myVirtualToplevel|ALT_INV_MEM_BUSY~1_RESYN12608_BDD12609\ <= NOT \myVirtualToplevel|MEM_BUSY~1_RESYN12608_BDD12609\;
-\myVirtualToplevel|ALT_INV_Equal4~0_RESYN12606_BDD12607\ <= NOT \myVirtualToplevel|Equal4~0_RESYN12606_BDD12607\;
-\myVirtualToplevel|ALT_INV_LessThan0~0_RESYN12604_BDD12605\ <= NOT \myVirtualToplevel|LessThan0~0_RESYN12604_BDD12605\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_RESYN12602_BDD12603\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN12594_BDD12595\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12594_BDD12595\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN12592_BDD12593\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN12592_BDD12593\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_RESYN12590_BDD12591\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12590_BDD12591\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_RESYN12588_BDD12589\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_RESYN12588_BDD12589\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12586_BDD12587\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12584_BDD12585\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_RESYN12582_BDD12583\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12578_BDD12579\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[29]_NEW2390_RESYN12576_BDD12577\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12574_BDD12575\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[25]_NEW2356_RESYN12572_BDD12573\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12570_BDD12571\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[27]_NEW2346_RESYN12568_BDD12569\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~6_RESYN12564_BDD12565\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_RESYN12564_BDD12565\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~11_RESYN12558_BDD12559\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_RESYN12558_BDD12559\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN12556_BDD12557\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12556_BDD12557\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN12554_BDD12555\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN12554_BDD12555\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_RESYN12546_BDD12547\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_RESYN12546_BDD12547\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12544_BDD12545\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_BDD12545\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12542_BDD12543\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12542_BDD12543\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_RESYN12538_BDD12539\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12538_BDD12539\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_RESYN12536_BDD12537\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_RESYN12536_BDD12537\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~13_RESYN12534_BDD12535\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_RESYN12534_BDD12535\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_RESYN12532_BDD12533\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12532_BDD12533\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_RESYN12530_BDD12531\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_RESYN12530_BDD12531\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~3_RESYN12528_BDD12529\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_RESYN12528_BDD12529\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_RESYN12526_BDD12527\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12526_BDD12527\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_RESYN12524_BDD12525\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_RESYN12524_BDD12525\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~3_RESYN12522_BDD12523\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_RESYN12522_BDD12523\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~1_RESYN12520_BDD12521\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_RESYN12520_BDD12521\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~5_RESYN12518_BDD12519\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_RESYN12518_BDD12519\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~4_RESYN12516_BDD12517\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_RESYN12516_BDD12517\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_RESYN12514_BDD12515\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_RESYN12514_BDD12515\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_RESYN12512_BDD12513\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_RESYN12512_BDD12513\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_RESYN12510_BDD12511\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_RESYN12510_BDD12511\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~4_RESYN12508_BDD12509\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_RESYN12508_BDD12509\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_RESYN12504_BDD12505\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_RESYN12504_BDD12505\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_RESYN12502_BDD12503\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12502_BDD12503\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_RESYN12500_BDD12501\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_RESYN12500_BDD12501\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_RESYN12496_BDD12497\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_RESYN12496_BDD12497\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~3_RESYN12492_BDD12493\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_RESYN12492_BDD12493\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_RESYN12490_BDD12491\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_RESYN12490_BDD12491\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~0_RESYN12488_BDD12489\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_RESYN12488_BDD12489\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_RESYN12486_BDD12487\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_RESYN12486_BDD12487\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_RESYN12484_BDD12485\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_RESYN12484_BDD12485\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_RESYN12470_BDD12471\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470_BDD12471\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_RESYN12464_BDD12465\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12464_BDD12465\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_RESYN12462_BDD12463\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_RESYN12462_BDD12463\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_RESYN12460_BDD12461\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_RESYN12460_BDD12461\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_RESYN12454_BDD12455\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12454_BDD12455\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_RESYN12452_BDD12453\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_RESYN12452_BDD12453\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_RESYN12434_BDD12435\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_RESYN12432_BDD12433\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_RESYN12430_BDD12431\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_RESYN12428_BDD12429\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_RESYN12426_BDD12427\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_RESYN12424_BDD12425\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_RESYN12422_BDD12423\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_RESYN12420_BDD12421\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12418_BDD12419\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12416_BDD12417\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~1_RESYN12414_BDD12415\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_RESYN12412_BDD12413\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12412_BDD12413\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_RESYN12410_BDD12411\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_RESYN12410_BDD12411\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_RESYN12408_BDD12409\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12408_BDD12409\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_RESYN12406_BDD12407\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_RESYN12406_BDD12407\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_RESYN12404_BDD12405\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12404_BDD12405\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_RESYN12402_BDD12403\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_RESYN12402_BDD12403\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_RESYN12400_BDD12401\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12400_BDD12401\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_RESYN12398_BDD12399\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_RESYN12398_BDD12399\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_RESYN12396_BDD12397\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12396_BDD12397\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_RESYN12394_BDD12395\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_RESYN12394_BDD12395\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_RESYN12388_BDD12389\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12388_BDD12389\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_RESYN12386_BDD12387\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_RESYN12386_BDD12387\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_RESYN12370_BDD12371\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370_BDD12371\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9367_BDD9368\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_RESYN9365_BDD9366\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9363_BDD9364\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_RESYN9361_BDD9362\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9077_RESYN9359_BDD9360\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9077_RESYN9359_BDD9360\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9357_BDD9358\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9357_BDD9358\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_RESYN9355_BDD9356\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_RESYN9355_BDD9356\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9349_BDD9350\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9349_BDD9350\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9347_BDD9348\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9347_BDD9348\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_RESYN9345_BDD9346\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_RESYN9345_BDD9346\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_RESYN9337_BDD9338\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_RESYN9337_BDD9338\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9335_BDD9336\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9335_BDD9336\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9333_BDD9334\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_BDD9334\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8847_RESYN9325_BDD9326\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_RESYN9325_BDD9326\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8845_RESYN9323_BDD9324\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_RESYN9323_BDD9324\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_RESYN9015_RESYN9351_BDD9352\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_RESYN9351_BDD9352\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_BDD9316\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9313_BDD9314\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9311_BDD9312\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~164_RESYN9307_BDD9308\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_RESYN9307_BDD9308\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_RESYN9301_BDD9302\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_RESYN9301_BDD9302\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_RESYN9299_BDD9300\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_RESYN9299_BDD9300\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_RESYN9297_BDD9298\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9297_BDD9298\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_RESYN9295_BDD9296\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_RESYN9295_BDD9296\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_RESYN9285_BDD9286\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9285_BDD9286\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_RESYN9283_BDD9284\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_RESYN9283_BDD9284\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9277_BDD9278\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9277_BDD9278\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_BDD9276\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_BDD9276\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9269_BDD9270\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9269_BDD9270\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9267_BDD9268\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9267_BDD9268\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~123_RESYN9263_BDD9264\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~123_RESYN9263_BDD9264\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~4_RESYN9251_BDD9252\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~4_RESYN9251_BDD9252\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~1_RESYN9249_BDD9250\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_RESYN9249_BDD9250\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_RESYN9247_BDD9248\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9247_BDD9248\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_RESYN9245_BDD9246\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_RESYN9245_BDD9246\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9239_BDD9240\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9239_BDD9240\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9237_BDD9238\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9237_BDD9238\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~82_RESYN9235_BDD9236\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_RESYN9235_BDD9236\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9233_BDD9234\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9233_BDD9234\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9231_BDD9232\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9231_BDD9232\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9229_BDD9230\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9229_BDD9230\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~61_RESYN9225_BDD9226\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_RESYN9225_BDD9226\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_RESYN9223_BDD9224\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9223_BDD9224\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_RESYN9221_BDD9222\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_RESYN9221_BDD9222\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_RESYN9217_BDD9218\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_RESYN9217_BDD9218\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_RESYN9215_BDD9216\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9215_BDD9216\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_RESYN9213_BDD9214\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_RESYN9213_BDD9214\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_RESYN9207_BDD9208\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_RESYN9207_BDD9208\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9197_BDD9198\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9195_BDD9196\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9193_BDD9194\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9191_BDD9192\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~5_RESYN9189_BDD9190\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9179_BDD9180\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9179_BDD9180\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9177_BDD9178\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9177_BDD9178\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9175_BDD9176\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9175_BDD9176\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~5_RESYN9173_BDD9174\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~5_RESYN9173_BDD9174\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_RESYN9171_BDD9172\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9171_BDD9172\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_RESYN9169_BDD9170\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_RESYN9169_BDD9170\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_RESYN9167_BDD9168\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9167_BDD9168\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_RESYN9165_BDD9166\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_RESYN9165_BDD9166\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~12_RESYN9163_BDD9164\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_RESYN9163_BDD9164\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_BDD9162\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_BDD9162\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9159_BDD9160\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159_BDD9160\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9157_BDD9158\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157_BDD9158\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_RESYN9155_BDD9156\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_RESYN9151_BDD9152\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9151_BDD9152\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_RESYN9149_BDD9150\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_RESYN9149_BDD9150\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9147_BDD9148\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9145_BDD9146\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9143_BDD9144\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9143_BDD9144\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9141_BDD9142\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9141_BDD9142\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_RESYN9139_BDD9140\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_RESYN9139_BDD9140\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9127_BDD9128\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9125_BDD9126\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125_BDD9126\;
-\myVirtualToplevel|ALT_INV_SD_CS_RESYN9121_BDD9122\ <= NOT \myVirtualToplevel|SD_CS_RESYN9121_BDD9122\;
-\myVirtualToplevel|ALT_INV_SD_CS_RESYN9119_BDD9120\ <= NOT \myVirtualToplevel|SD_CS_RESYN9119_BDD9120\;
-\myVirtualToplevel|ALT_INV_IO_SELECT_RESYN9117_BDD9118\ <= NOT \myVirtualToplevel|IO_SELECT_RESYN9117_BDD9118\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8707_RESYN9111_BDD9112\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_RESYN9111_BDD9112\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_RESYN9109_BDD9110\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9109_BDD9110\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_RESYN9107_BDD9108\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_RESYN9107_BDD9108\;
-\myVirtualToplevel|ALT_INV_IO_SELECT_RESYN9115_BDD9116\ <= NOT \myVirtualToplevel|IO_SELECT_RESYN9115_BDD9116\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9105_BDD9106\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_RESYN9103_BDD9104\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8467_RESYN9093_BDD9094\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_RESYN9093_BDD9094\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8459_RESYN9091_BDD9092\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_RESYN9091_BDD9092\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8447_RESYN9089_BDD9090\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_RESYN9089_BDD9090\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_RESYN9095_BDD9096\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9087_BDD9088\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[11]_NEW3229_RESYN9085_BDD9086\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_RESYN9075_BDD9076\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_RESYN9075_BDD9076\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9071_BDD9072\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9071_BDD9072\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9069_BDD9070\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9069_BDD9070\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_RESYN9067_BDD9068\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_RESYN9067_BDD9068\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9065_BDD9066\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9065_BDD9066\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9063_BDD9064\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9063_BDD9064\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_RESYN9061_BDD9062\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_RESYN9061_BDD9062\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9059_BDD9060\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9059_BDD9060\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9057_BDD9058\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9057_BDD9058\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_RESYN9055_BDD9056\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_RESYN9055_BDD9056\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_RESYN9053_BDD9054\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9053_BDD9054\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_RESYN9051_BDD9052\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_RESYN9051_BDD9052\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9049_BDD9050\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9049_BDD9050\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9047_BDD9048\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9047_BDD9048\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_RESYN9045_BDD9046\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_RESYN9045_BDD9046\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_RESYN9043_BDD9044\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9043_BDD9044\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_RESYN9041_BDD9042\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_RESYN9041_BDD9042\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9039_BDD9040\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9039_BDD9040\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9037_BDD9038\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9037_BDD9038\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_RESYN9035_BDD9036\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_RESYN9035_BDD9036\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_RESYN9033_BDD9034\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9033_BDD9034\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_RESYN9031_BDD9032\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_RESYN9031_BDD9032\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9029_BDD9030\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9029_BDD9030\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9027_BDD9028\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9027_BDD9028\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_RESYN9025_BDD9026\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_RESYN9025_BDD9026\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~3_RESYN9023_BDD9024\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9023_BDD9024\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~3_RESYN9021_BDD9022\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~3_RESYN9021_BDD9022\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_RESYN9019_BDD9020\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9019_BDD9020\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_RESYN9017_BDD9018\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_RESYN9017_BDD9018\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_RESYN9015_BDD9016\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_RESYN9015_BDD9016\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~14_RESYN9011_BDD9012\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_RESYN9011_BDD9012\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_RESYN9009_BDD9010\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN9003_BDD9004\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN9003_BDD9004\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8999_BDD9000\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8999_BDD9000\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8997_BDD8998\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8997_BDD8998\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~3_RESYN8995_BDD8996\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~3_RESYN8995_BDD8996\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_RESYN8993_BDD8994\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993_BDD8994\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_RESYN8987_BDD8988\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8987_BDD8988\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_RESYN8985_BDD8986\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_RESYN8985_BDD8986\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8983_BDD8984\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8983_BDD8984\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~3_RESYN8979_BDD8980\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~3_RESYN8979_BDD8980\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_RESYN8977_BDD8978\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8977_BDD8978\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_RESYN8975_BDD8976\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_RESYN8975_BDD8976\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8973_BDD8974\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8973_BDD8974\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8971_BDD8972\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8971_BDD8972\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~3_RESYN8969_BDD8970\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_RESYN8969_BDD8970\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8967_BDD8968\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8967_BDD8968\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8965_BDD8966\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8965_BDD8966\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_BDD8964\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_BDD8964\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~4_RESYN8961_BDD8962\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_RESYN8961_BDD8962\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_BDD8960\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_BDD8960\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_RESYN8957_BDD8958\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_RESYN8957_BDD8958\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_RESYN8955_BDD8956\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8955_BDD8956\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_RESYN8953_BDD8954\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_RESYN8953_BDD8954\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_RESYN8941_BDD8942\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_BDD8942\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8939_BDD8940\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8939_BDD8940\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8937_BDD8938\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_BDD8938\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~0_RESYN8935_BDD8936\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_RESYN8935_BDD8936\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_RESYN8929_BDD8930\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_RESYN8929_BDD8930\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~24_RESYN8923_BDD8924\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_RESYN8921_BDD8922\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_RESYN8921_BDD8922\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8887_BDD8888\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~3_RESYN8885_BDD8886\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_RESYN8883_BDD8884\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_RESYN8879_BDD8880\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8877_BDD8878\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8877_BDD8878\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8875_BDD8876\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8875_BDD8876\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_RESYN8873_BDD8874\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_RESYN8873_BDD8874\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_RESYN8869_BDD8870\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8869_BDD8870\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_RESYN8867_BDD8868\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_RESYN8867_BDD8868\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_RESYN8861_BDD8862\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8861_BDD8862\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_RESYN8859_BDD8860\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_RESYN8859_BDD8860\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8853_BDD8854\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8853_BDD8854\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_RESYN8851_BDD8852\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_RESYN8851_BDD8852\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8849_BDD8850\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8849_BDD8850\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8847_BDD8848\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8847_BDD8848\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_RESYN8845_BDD8846\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_RESYN8845_BDD8846\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_RESYN8843_BDD8844\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8843_BDD8844\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_RESYN8841_BDD8842\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_RESYN8841_BDD8842\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~3_RESYN8837_BDD8838\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_RESYN8837_BDD8838\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~10_RESYN8833_BDD8834\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8833_BDD8834\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~10_RESYN8831_BDD8832\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~10_RESYN8831_BDD8832\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~4_RESYN8829_BDD8830\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_RESYN8829_BDD8830\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8827_BDD8828\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8827_BDD8828\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8825_BDD8826\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8825_BDD8826\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_RESYN8823_BDD8824\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_RESYN8823_BDD8824\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_RESYN8819_BDD8820\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_RESYN8819_BDD8820\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_RESYN8809_BDD8810\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8803_BDD8804\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803_BDD8804\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8791_BDD8792\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791_BDD8792\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_RESYN8789_BDD8790\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8777_BDD8778\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8775_BDD8776\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8773_BDD8774\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8771_BDD8772\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8769_BDD8770\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8767_BDD8768\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\;
-\myVirtualToplevel|ALT_INV_INTR0_CS_RESYN8755_BDD8756\ <= NOT \myVirtualToplevel|INTR0_CS_RESYN8755_BDD8756\;
-\myVirtualToplevel|ALT_INV_SOCCFG_CS_RESYN8753_BDD8754\ <= NOT \myVirtualToplevel|SOCCFG_CS_RESYN8753_BDD8754\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~5_RESYN8749_BDD8750\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8749_BDD8750\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~5_RESYN8745_BDD8746\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~5_RESYN8745_BDD8746\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ <= NOT \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_RESYN8741_BDD8742\ <= NOT \myVirtualToplevel|MEM_DATA_READ[3]~92_RESYN8741_BDD8742\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_RESYN8739_BDD8740\ <= NOT \myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739_BDD8740\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_RESYN8737_BDD8738\ <= NOT \myVirtualToplevel|MEM_DATA_READ[5]~88_RESYN8737_BDD8738\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_RESYN8735_BDD8736\ <= NOT \myVirtualToplevel|MEM_DATA_READ[6]~86_RESYN8735_BDD8736\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_RESYN8733_BDD8734\ <= NOT \myVirtualToplevel|MEM_DATA_READ[7]~84_RESYN8733_BDD8734\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~82_RESYN8731_BDD8732\ <= NOT \myVirtualToplevel|MEM_DATA_READ[8]~82_RESYN8731_BDD8732\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~80_RESYN8729_BDD8730\ <= NOT \myVirtualToplevel|MEM_DATA_READ[9]~80_RESYN8729_BDD8730\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~78_RESYN8727_BDD8728\ <= NOT \myVirtualToplevel|MEM_DATA_READ[10]~78_RESYN8727_BDD8728\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~76_RESYN8725_BDD8726\ <= NOT \myVirtualToplevel|MEM_DATA_READ[11]~76_RESYN8725_BDD8726\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~74_RESYN8723_BDD8724\ <= NOT \myVirtualToplevel|MEM_DATA_READ[12]~74_RESYN8723_BDD8724\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~72_RESYN8721_BDD8722\ <= NOT \myVirtualToplevel|MEM_DATA_READ[13]~72_RESYN8721_BDD8722\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~70_RESYN8719_BDD8720\ <= NOT \myVirtualToplevel|MEM_DATA_READ[14]~70_RESYN8719_BDD8720\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~68_RESYN8717_BDD8718\ <= NOT \myVirtualToplevel|MEM_DATA_READ[15]~68_RESYN8717_BDD8718\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~5_RESYN8715_BDD8716\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~5_RESYN8715_BDD8716\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8711_BDD8712\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8711_BDD8712\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8709_BDD8710\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8709_BDD8710\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8707_BDD8708\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8707_BDD8708\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_RESYN8705_BDD8706\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_RESYN8705_BDD8706\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8703_BDD8704\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8703_BDD8704\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8701_BDD8702\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8701_BDD8702\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_RESYN8699_BDD8700\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_RESYN8699_BDD8700\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8697_BDD8698\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8697_BDD8698\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8695_BDD8696\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8695_BDD8696\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_RESYN8693_BDD8694\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_RESYN8693_BDD8694\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8691_BDD8692\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8691_BDD8692\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8689_BDD8690\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8689_BDD8690\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_RESYN8687_BDD8688\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_RESYN8687_BDD8688\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_RESYN8685_BDD8686\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8685_BDD8686\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_RESYN8683_BDD8684\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_RESYN8683_BDD8684\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8681_BDD8682\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8681_BDD8682\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8679_BDD8680\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8679_BDD8680\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_RESYN8677_BDD8678\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677_BDD8678\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8675_BDD8676\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8673_BDD8674\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_RESYN8671_BDD8672\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_RESYN8669_BDD8670\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669_BDD8670\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_RESYN8667_BDD8668\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8667_BDD8668\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_RESYN8665_BDD8666\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8665_BDD8666\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_RESYN8663_BDD8664\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_RESYN8663_BDD8664\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8661_BDD8662\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8661_BDD8662\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8659_BDD8660\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8659_BDD8660\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_RESYN8657_BDD8658\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_RESYN8657_BDD8658\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~94_RESYN8655_BDD8656\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_RESYN8655_BDD8656\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8651_BDD8652\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8651_BDD8652\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8649_BDD8650\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8649_BDD8650\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_RESYN8647_BDD8648\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_RESYN8647_BDD8648\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[21]~1_RESYN8641_BDD8642\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8641_BDD8642\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[21]~1_RESYN8639_BDD8640\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_RESYN8639_BDD8640\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~4_RESYN8635_BDD8636\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~4_RESYN8635_BDD8636\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_RESYN8633_BDD8634\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8633_BDD8634\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_RESYN8631_BDD8632\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_RESYN8631_BDD8632\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8627_BDD8628\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8627_BDD8628\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_RESYN8625_BDD8626\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_RESYN8625_BDD8626\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_RESYN8623_BDD8624\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8623_BDD8624\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_RESYN8621_BDD8622\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_RESYN8621_BDD8622\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~8_RESYN8629_BDD8630\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_RESYN8629_BDD8630\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~6_RESYN8617_BDD8618\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_RESYN8617_BDD8618\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~8_RESYN8615_BDD8616\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_RESYN8615_BDD8616\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_RESYN8613_BDD8614\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_RESYN8613_BDD8614\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_RESYN8605_BDD8606\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_RESYN8605_BDD8606\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_RESYN8603_BDD8604\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_RESYN8603_BDD8604\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~58_RESYN8601_BDD8602\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_RESYN8601_BDD8602\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~48_RESYN8599_BDD8600\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_RESYN8599_BDD8600\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~40_RESYN8597_BDD8598\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_RESYN8597_BDD8598\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~31_RESYN8595_BDD8596\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_RESYN8595_BDD8596\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector573~1_RESYN8589_BDD8590\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_RESYN8589_BDD8590\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector507~1_RESYN8587_BDD8588\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_RESYN8587_BDD8588\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8585_BDD8586\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector639~1_RESYN8583_BDD8584\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_RESYN8583_BDD8584\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~2_RESYN8577_BDD8578\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8575_BDD8576\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_RESYN8573_BDD8574\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector771~2_RESYN8571_BDD8572\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_RESYN8571_BDD8572\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8565_BDD8566\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8563_BDD8564\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8561_BDD8562\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~2_RESYN8559_BDD8560\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8557_BDD8558\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_BDD8556\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8551_BDD8552\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8549_BDD8550\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8547_BDD8548\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~2_RESYN8545_BDD8546\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8529_BDD8530\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_RESYN8527_BDD8528\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8525_BDD8526\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8523_BDD8524\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~4_RESYN8521_BDD8522\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8519_BDD8520\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8517_BDD8518\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8515_BDD8516\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~4_RESYN8513_BDD8514\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8511_BDD8512\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8509_BDD8510\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~4_RESYN8507_BDD8508\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8505_BDD8506\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8503_BDD8504\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8501_BDD8502\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~4_RESYN8499_BDD8500\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_RESYN8497_BDD8498\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8497_BDD8498\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_RESYN8495_BDD8496\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_RESYN8495_BDD8496\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~4_RESYN8493_BDD8494\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_RESYN8493_BDD8494\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_RESYN8491_BDD8492\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8491_BDD8492\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_RESYN8489_BDD8490\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489_BDD8490\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_RESYN8487_BDD8488\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_RESYN8483_BDD8484\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~4_RESYN8479_BDD8480\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_RESYN8479_BDD8480\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_RESYN8475_BDD8476\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8475_BDD8476\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_RESYN8473_BDD8474\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_RESYN8473_BDD8474\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8469_BDD8470\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8469_BDD8470\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_RESYN8467_BDD8468\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_RESYN8467_BDD8468\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_RESYN8465_BDD8466\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8465_BDD8466\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_RESYN8463_BDD8464\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_RESYN8463_BDD8464\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8461_BDD8462\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8461_BDD8462\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_RESYN8459_BDD8460\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_RESYN8459_BDD8460\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~6_RESYN8457_BDD8458\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~6_RESYN8457_BDD8458\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_RESYN8455_BDD8456\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8455_BDD8456\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_RESYN8453_BDD8454\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_RESYN8453_BDD8454\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8449_BDD8450\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8449_BDD8450\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_RESYN8447_BDD8448\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_RESYN8447_BDD8448\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_RESYN8443_BDD8444\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8437_BDD8438\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437_BDD8438\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8435_BDD8436\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435_BDD8436\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8429_BDD8430\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_RESYN8427_BDD8428\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8427_BDD8428\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_RESYN8425_BDD8426\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_RESYN8425_BDD8426\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_RESYN8423_BDD8424\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8413_BDD8414\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8411_BDD8412\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_RESYN12544_RESYN13472_BDD13473\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~3_RESYN8963_RESYN9333_RESYN13470_BDD13471\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13466_BDD13467\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466_BDD13467\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13464_BDD13465\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_RESYN13462_BDD13463\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_RESYN8941_RESYN13460_BDD13461\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_RESYN8941_RESYN13460_BDD13461\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_RESYN8937_RESYN13458_BDD13459\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_RESYN8937_RESYN13458_BDD13459\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13456_BDD13457\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_RESYN8555_RESYN13454_BDD13455\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13448_BDD13449\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[60]_NEW2619_RESYN13446_BDD13447\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13444_BDD13445\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]_NEW2616_RESYN13442_BDD13443\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13440_BDD13441\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]_NEW2614_RESYN13438_BDD13439\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13436_BDD13437\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[61]_NEW2612_RESYN13434_BDD13435\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13432_BDD13433\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]_NEW2609_RESYN13430_BDD13431\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13428_BDD13429\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[61]_NEW2607_RESYN13426_BDD13427\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13424_BDD13425\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[56]_NEW2605_RESYN13422_BDD13423\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13420_BDD13421\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]_NEW2602_RESYN13418_BDD13419\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13416_BDD13417\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[56]_NEW2600_RESYN13414_BDD13415\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13412_BDD13413\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[55]_NEW2597_RESYN13410_BDD13411\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13408_BDD13409\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]_NEW2594_RESYN13406_BDD13407\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13404_BDD13405\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]_NEW2591_RESYN13402_BDD13403\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13400_BDD13401\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[52]_NEW2588_RESYN13398_BDD13399\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13396_BDD13397\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[54]_NEW2586_RESYN13394_BDD13395\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13392_BDD13393\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[54]_NEW2583_RESYN13390_BDD13391\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13388_BDD13389\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[54]_NEW2581_RESYN13386_BDD13387\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13384_BDD13385\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]_NEW2578_RESYN13382_BDD13383\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13380_BDD13381\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]_NEW2575_RESYN13378_BDD13379\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13376_BDD13377\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]_NEW2572_RESYN13374_BDD13375\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13372_BDD13373\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[48]_NEW2569_RESYN13370_BDD13371\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13368_BDD13369\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[51]_NEW2566_RESYN13366_BDD13367\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13364_BDD13365\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[50]_NEW2563_RESYN13362_BDD13363\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13360_BDD13361\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[49]_NEW2560_RESYN13358_BDD13359\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13356_BDD13357\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[39]_NEW2557_RESYN13354_BDD13355\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13352_BDD13353\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]_NEW2554_RESYN13350_BDD13351\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13348_BDD13349\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[38]_NEW2551_RESYN13346_BDD13347\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13344_BDD13345\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[37]_NEW2548_RESYN13342_BDD13343\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13340_BDD13341\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[32]_NEW2545_RESYN13338_BDD13339\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13336_BDD13337\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[35]_NEW2542_RESYN13334_BDD13335\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13332_BDD13333\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]_NEW2539_RESYN13330_BDD13331\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13328_BDD13329\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]_NEW2536_RESYN13326_BDD13327\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13324_BDD13325\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[23]_NEW2533_RESYN13322_BDD13323\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13320_BDD13321\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[20]_NEW2530_RESYN13318_BDD13319\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13316_BDD13317\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[22]_NEW2527_RESYN13314_BDD13315\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13312_BDD13313\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]_NEW2524_RESYN13310_BDD13311\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13308_BDD13309\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]_NEW2521_RESYN13306_BDD13307\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13304_BDD13305\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]_NEW2518_RESYN13302_BDD13303\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13300_BDD13301\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]_NEW2515_RESYN13298_BDD13299\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13296_BDD13297\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]_NEW2512_RESYN13294_BDD13295\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13292_BDD13293\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]_NEW2509_RESYN13290_BDD13291\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13288_BDD13289\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[4]_NEW2506_RESYN13286_BDD13287\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13284_BDD13285\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]_NEW2503_RESYN13282_BDD13283\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13280_BDD13281\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]_NEW2500_RESYN13278_BDD13279\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13276_BDD13277\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]_NEW2497_RESYN13274_BDD13275\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13272_BDD13273\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[3]_NEW2494_RESYN13270_BDD13271\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13268_BDD13269\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[2]_NEW2491_RESYN13266_BDD13267\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13264_BDD13265\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]_NEW2488_RESYN13262_BDD13263\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13260_BDD13261\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[58]_NEW2486_RESYN13258_BDD13259\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13256_BDD13257\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[58]_NEW2484_RESYN13254_BDD13255\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13252_BDD13253\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[53]_NEW2482_RESYN13250_BDD13251\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13248_BDD13249\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[53]_NEW2480_RESYN13246_BDD13247\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13244_BDD13245\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[57]_NEW2478_RESYN13242_BDD13243\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13240_BDD13241\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[57]_NEW2476_RESYN13238_BDD13239\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13236_BDD13237\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[55]_NEW2474_RESYN13234_BDD13235\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13232_BDD13233\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[59]_NEW2472_RESYN13230_BDD13231\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13228_BDD13229\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[59]_NEW2470_RESYN13226_BDD13227\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13224_BDD13225\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[52]_NEW2468_RESYN13222_BDD13223\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13220_BDD13221\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[52]_NEW2466_RESYN13218_BDD13219\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13216_BDD13217\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[48]_NEW2464_RESYN13214_BDD13215\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13212_BDD13213\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[50]_NEW2462_RESYN13210_BDD13211\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13208_BDD13209\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[50]_NEW2460_RESYN13206_BDD13207\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13204_BDD13205\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[49]_NEW2458_RESYN13202_BDD13203\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13200_BDD13201\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[45]_NEW2456_RESYN13198_BDD13199\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13196_BDD13197\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[45]_NEW2454_RESYN13194_BDD13195\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13192_BDD13193\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[45]_NEW2452_RESYN13190_BDD13191\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13188_BDD13189\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[51]_NEW2450_RESYN13186_BDD13187\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13184_BDD13185\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[51]_NEW2448_RESYN13182_BDD13183\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13180_BDD13181\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[44]_NEW2446_RESYN13178_BDD13179\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13176_BDD13177\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[44]_NEW2444_RESYN13174_BDD13175\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13172_BDD13173\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[44]_NEW2442_RESYN13170_BDD13171\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13168_BDD13169\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[40]_NEW2440_RESYN13166_BDD13167\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13164_BDD13165\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[40]_NEW2438_RESYN13162_BDD13163\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13160_BDD13161\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[40]_NEW2436_RESYN13158_BDD13159\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13156_BDD13157\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]_NEW2434_RESYN13154_BDD13155\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13152_BDD13153\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]_NEW2432_RESYN13150_BDD13151\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13148_BDD13149\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[42]_NEW2430_RESYN13146_BDD13147\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13144_BDD13145\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[38]_NEW2428_RESYN13142_BDD13143\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13140_BDD13141\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[38]_NEW2426_RESYN13138_BDD13139\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13136_BDD13137\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[41]_NEW2424_RESYN13134_BDD13135\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13132_BDD13133\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[41]_NEW2422_RESYN13130_BDD13131\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13128_BDD13129\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[41]_NEW2420_RESYN13126_BDD13127\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13124_BDD13125\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[37]_NEW2418_RESYN13122_BDD13123\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13120_BDD13121\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[37]_NEW2416_RESYN13118_BDD13119\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13116_BDD13117\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[43]_NEW2414_RESYN13114_BDD13115\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13112_BDD13113\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[43]_NEW2412_RESYN13110_BDD13111\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13108_BDD13109\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[43]_NEW2410_RESYN13106_BDD13107\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13104_BDD13105\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[39]_NEW2408_RESYN13102_BDD13103\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13100_BDD13101\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[36]_NEW2406_RESYN13098_BDD13099\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13096_BDD13097\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[36]_NEW2404_RESYN13094_BDD13095\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13092_BDD13093\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[32]_NEW2402_RESYN13090_BDD13091\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13088_BDD13089\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[34]_NEW2400_RESYN13086_BDD13087\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13084_BDD13085\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]_NEW2398_RESYN13082_BDD13083\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13080_BDD13081\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[33]_NEW2394_RESYN13078_BDD13079\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13076_BDD13077\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[29]_NEW2392_RESYN13074_BDD13075\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13072_BDD13073\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[29]_NEW2388_RESYN13070_BDD13071\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13068_BDD13069\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[35]_NEW2386_RESYN13066_BDD13067\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13064_BDD13065\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[35]_NEW2384_RESYN13062_BDD13063\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13060_BDD13061\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[28]_NEW2380_RESYN13058_BDD13059\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13056_BDD13057\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[28]_NEW2378_RESYN13054_BDD13055\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[28]_NEW2376_RESYN13052_BDD13053\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13050_BDD13051\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[24]_NEW2374_RESYN13048_BDD13049\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13046_BDD13047\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[24]_NEW2372_RESYN13044_BDD13045\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[24]_NEW2370_RESYN13042_BDD13043\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13040_BDD13041\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[26]_NEW2368_RESYN13038_BDD13039\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13036_BDD13037\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[26]_NEW2366_RESYN13034_BDD13035\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[26]_NEW2364_RESYN13032_BDD13033\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13030_BDD13031\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[22]_NEW2362_RESYN13028_BDD13029\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[22]_NEW2360_RESYN13026_BDD13027\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13024_BDD13025\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[25]_NEW2358_RESYN13022_BDD13023\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13020_BDD13021\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[25]_NEW2354_RESYN13018_BDD13019\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13016_BDD13017\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[21]_NEW2352_RESYN13014_BDD13015\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13012_BDD13013\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[21]_NEW2350_RESYN13010_BDD13011\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13008_BDD13009\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[27]_NEW2348_RESYN13006_BDD13007\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13004_BDD13005\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[27]_NEW2344_RESYN13002_BDD13003\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN13000_BDD13001\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[23]_NEW2342_RESYN12998_BDD12999\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12996_BDD12997\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[20]_NEW2340_RESYN12994_BDD12995\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[20]_NEW2338_RESYN12992_BDD12993\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12990_BDD12991\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[16]_NEW2336_RESYN12988_BDD12989\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12986_BDD12987\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[18]_NEW2334_RESYN12984_BDD12985\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[18]_NEW2332_RESYN12982_BDD12983\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12980_BDD12981\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[17]_NEW2330_RESYN12978_BDD12979\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12976_BDD12977\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[13]_NEW2328_RESYN12974_BDD12975\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12972_BDD12973\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[13]_NEW2326_RESYN12970_BDD12971\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12968_BDD12969\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[13]_NEW2324_RESYN12966_BDD12967\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12964_BDD12965\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[19]_NEW2322_RESYN12962_BDD12963\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12960_BDD12961\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[19]_NEW2320_RESYN12958_BDD12959\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12956_BDD12957\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]_NEW2318_RESYN12954_BDD12955\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12952_BDD12953\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[12]_NEW2316_RESYN12950_BDD12951\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[16]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_ADDR[0][2]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_INT_ENABLE[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|INT_ENABLE[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER[5]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_ADDR[0][4]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_INT_ENABLE[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|INT_ENABLE[4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_ADDR[0][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_ADDR[0][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_ADDR[0][16]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_DATA_VALID~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_RESET_TIMER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~DUPLICATE_q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[19]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[17]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[21]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[33]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[33]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[34]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[34]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[36]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[36]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[59]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[59]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[55]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[55]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[57]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[57]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[53]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[53]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[58]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[58]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[34]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[34]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE_q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[56]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[56]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[60]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[60]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[61]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[61]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[38]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[38]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[2]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[1]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[26]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[19]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[14]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[30]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[30]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[35]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[35]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[32]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[32]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[48]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[48]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[37]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[37]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[42]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[42]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[40]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[40]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[52]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[52]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[44]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[44]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[47]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[47]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[49]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[49]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[30]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[30]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[25]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[9]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[0]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[21]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[31]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[29]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[27]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[26]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[28]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[3]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[3]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[8]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[8]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[7]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[6]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[11]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[10]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[9]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[5]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[5]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[14]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[13]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[23]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[20]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[21]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[15]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[25]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[25]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[26]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[26]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[7]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[10]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_SD_RESET_TIMER[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|TX_COUNTER[14]~DUPLICATE_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[13]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[12]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[19]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[19]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[20]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[20]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[22]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[22]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[9]~DUPLICATE_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount[3]~DUPLICATE_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]~DUPLICATE_q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~131_Duplicate_173\ <= NOT \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~111_Duplicate_170\ <= NOT \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~127_Duplicate_167\ <= NOT \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\ <= NOT \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~95_Duplicate_161\ <= NOT \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~99_Duplicate_158\ <= NOT \myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_155\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~65_Duplicate_152\ <= NOT \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[31]~31_Duplicate_66\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[31]~31_Duplicate_66\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[0]_OTERM1619\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]_OTERM1619\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]_OTERM1617\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1617\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]_OTERM1615\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1615\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1613\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1611\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS_OTERM1609\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1607\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1607\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]_OTERM1605\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]_OTERM1605\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]_OTERM1603\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1603\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]_OTERM1601\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]_OTERM1601\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]_OTERM1599\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1599\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]_OTERM1597\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]_OTERM1597\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1595\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1593\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1591\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS_OTERM1589\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[1]_OTERM1587\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]_OTERM1587\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[1]_OTERM1585\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]_OTERM1585\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]_OTERM1583\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1583\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]_OTERM1581\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]_OTERM1581\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1579\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1577\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS_OTERM1575\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]_OTERM1573\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1573\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]_OTERM1571\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]_OTERM1571\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[15]_OTERM1569\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[15]_OTERM1569\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1567\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1567\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1565\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1563\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1561\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[1]_OTERM1559\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]_OTERM1559\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1557\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1557\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]_OTERM1555\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]_OTERM1555\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1553\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1553\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]_OTERM1551\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]_OTERM1551\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1549\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1549\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1547\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1547\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]_OTERM1545\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]_OTERM1545\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1543\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1543\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1541\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1539\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1537\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[1]_OTERM1535\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]_OTERM1535\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1533\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1533\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1531\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1527\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1525\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1523\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS_OTERM1521\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1519\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1517\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS_OTERM1515\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1513\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1511\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1509\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS_OTERM1507\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1505\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1503\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1501\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS_OTERM1499\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]_OTERM1497\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1497\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]_OTERM1495\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]_OTERM1495\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1493\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1491\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1489\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1485\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1485\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]_OTERM1483\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]_OTERM1483\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1481\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1481\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]_OTERM1479\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]_OTERM1479\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1477\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1477\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1475\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1473\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1471\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1469\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1467\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1465\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS_OTERM1463\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1461\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1459\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1457\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS_OTERM1455\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]_OTERM1447\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1447\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]_OTERM1445\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]_OTERM1445\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1443\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1441\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS_OTERM1439\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1437\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1437\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1435\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1433\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1433\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1431\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]_OTERM1429\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1429\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1427\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1427\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1425\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1423\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1421\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1419\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1417\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1415\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS_OTERM1413\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]_OTERM1411\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1411\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]_OTERM1409\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1409\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]_OTERM1401\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1401\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]_OTERM1399\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]_OTERM1399\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1397\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1395\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1393\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS_OTERM1391\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[20]_OTERM1389\ <= NOT \myVirtualToplevel|IO_DATA_READ[20]_OTERM1389\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[20]_OTERM1387\ <= NOT \myVirtualToplevel|IO_DATA_READ[20]_OTERM1387\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1385\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1385\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1383\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1379\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]_OTERM1377\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1377\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]_OTERM1375\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]_OTERM1375\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1357\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1355\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1355\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1353\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1351\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1349\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1349\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1347\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1347\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1345\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1343\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1343\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1341\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1341\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1339\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1337\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1337\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1335\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1335\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1333\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1331\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1329\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1327\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1325\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1325\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1323\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1323\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1321\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1319\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1319\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1317\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1315\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1313\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1313\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1309\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1307\ <= NOT \myVirtualToplevel|IO_DATA_READ[23]_OTERM1307\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1305\ <= NOT \myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1303\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1301\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1299\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS_OTERM1297\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1283\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1283\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1281\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1279\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1277\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1275\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1275\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1273\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1273\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]_OTERM1271\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]_OTERM1271\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1269\ <= NOT \myVirtualToplevel|IO_DATA_READ[22]_OTERM1269\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1267\ <= NOT \myVirtualToplevel|IO_DATA_READ[22]_OTERM1267\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1265\ <= NOT \myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1263\ <= NOT \myVirtualToplevel|IO_DATA_READ[22]_OTERM1263\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1261\ <= NOT \myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1259\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1259\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1255\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1253\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1251\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[9]_OTERM1249\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[9]_OTERM1249\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[7]_OTERM1247\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[7]_OTERM1247\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[5]_OTERM1245\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[5]_OTERM1245\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[6]_OTERM1243\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[6]_OTERM1243\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[12]_OTERM1241\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[12]_OTERM1241\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[16]_OTERM1239\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[16]_OTERM1239\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[17]_OTERM1237\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[17]_OTERM1237\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[18]_OTERM1235\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[18]_OTERM1235\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[19]_OTERM1233\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[19]_OTERM1233\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1231\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1231\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[10]_OTERM1229\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[10]_OTERM1229\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[11]_OTERM1227\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[11]_OTERM1227\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[4]_OTERM1225\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[4]_OTERM1225\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[1]_OTERM1223\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[1]_OTERM1223\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[8]_OTERM1221\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[8]_OTERM1221\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1219\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1217\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[21]_OTERM1215\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[21]_OTERM1215\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[20]_OTERM1213\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[20]_OTERM1213\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1211\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1211\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1209\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1209\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1207\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1207\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[0]_OTERM1205\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[0]_OTERM1205\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1203\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1201\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1199\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1199\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1197\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1197\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1195\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1195\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1193\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1193\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Start_OTERM1191\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Start_OTERM1191\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1189\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1189\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[13]_OTERM1187\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[13]_OTERM1187\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1185\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1185\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1183\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1183\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[15]_OTERM1181\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[15]_OTERM1181\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]_OTERM1179\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1179\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]_OTERM1177\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1177\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[22]_OTERM1175\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[22]_OTERM1175\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1173\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1173\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1171\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1171\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[23]_OTERM1169\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[23]_OTERM1169\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1159\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1157\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1155\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_END_OTERM1145\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1145\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_END_OTERM1143\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_END_OTERM1143\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]_OTERM1141\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1141\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]_OTERM1139\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]_OTERM1139\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]_OTERM1137\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1137\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]_OTERM1135\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]_OTERM1135\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]_OTERM1133\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1133\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]_OTERM1131\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]_OTERM1131\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1119\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1119\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1116\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1116\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1114\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1114\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]_OTERM1112\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]_OTERM1112\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1110\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1108\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]_OTERM1106\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1106\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]_OTERM1104\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]_OTERM1104\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]_OTERM1102\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1102\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]_OTERM1100\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]_OTERM1100\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]_OTERM1092\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1092\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]_OTERM1090\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]_OTERM1090\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]_OTERM1088\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1088\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]_OTERM1086\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]_OTERM1086\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1084\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1084\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1082\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1082\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1080\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1078\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1078\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1076\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1076\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]_OTERM1074\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]_OTERM1074\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]_OTERM1072\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1072\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]_OTERM1070\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]_OTERM1070\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1054\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1052\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM998\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM998\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM996\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM996\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM994\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM994\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM992\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM992\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM990\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM990\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write_OTERM988\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM988\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM984\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM982\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM980\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM978\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[29]_OTERM970\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[29]_OTERM970\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM948\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM946\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM938\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]_OTERM936\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM936\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]_OTERM934\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]_OTERM934\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[16]_OTERM932\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM932\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[16]_OTERM930\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[16]_OTERM930\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[7]_OTERM928\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM928\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[7]_OTERM926\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[7]_OTERM926\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]_OTERM924\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM924\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]_OTERM922\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM922\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]_OTERM920\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM920\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]_OTERM918\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM918\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]_OTERM916\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM916\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]_OTERM914\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM914\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM912\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM910\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM908\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM906\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[26]_OTERM904\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[26]_OTERM904\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM902\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM902\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM900\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM900\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[25]_OTERM898\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[25]_OTERM898\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM896\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM896\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM894\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM892\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]_OTERM890\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM890\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[17]_OTERM888\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM888\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[17]_OTERM886\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[17]_OTERM886\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM882\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM882\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM880\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM880\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM878\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM878\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad_OTERM876\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad_OTERM876\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM874\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM874\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM872\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM872\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTSPACE_OTERM870\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTSPACE_OTERM870\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]_OTERM868\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM868\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]_OTERM866\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]_OTERM866\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]_OTERM864\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM864\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]_OTERM862\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]_OTERM862\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]_OTERM860\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM860\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]_OTERM858\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]_OTERM858\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]_OTERM856\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM856\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]_OTERM854\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]_OTERM854\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]_OTERM852\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM852\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]_OTERM850\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]_OTERM850\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]_OTERM848\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM848\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]_OTERM846\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]_OTERM846\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]_OTERM844\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM844\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]_OTERM842\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]_OTERM842\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]_OTERM840\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM840\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]_OTERM838\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]_OTERM838\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]_OTERM836\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM836\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]_OTERM834\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]_OTERM834\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]_OTERM832\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM832\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]_OTERM830\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]_OTERM830\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]_OTERM828\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM828\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]_OTERM826\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]_OTERM826\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]_OTERM824\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM824\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]_OTERM822\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]_OTERM822\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]_OTERM820\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM820\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]_OTERM818\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]_OTERM818\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]_OTERM816\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM816\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]_OTERM814\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]_OTERM814\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]_OTERM812\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM812\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]_OTERM810\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]_OTERM810\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM808\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM808\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM806\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM806\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM804\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM804\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]_OTERM802\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]_OTERM802\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM800\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM800\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[28]_OTERM798\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[28]_OTERM798\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM796\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM796\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM794\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM794\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM792\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM792\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM790\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM790\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[30]_OTERM788\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[30]_OTERM788\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM784\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM784\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM782\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM782\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM780\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM780\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM778\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM778\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM776\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM776\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM774\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM774\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTLF_OTERM772\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTLF_OTERM772\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]_OTERM770\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM770\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]_OTERM768\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]_OTERM768\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]_OTERM766\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM766\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]_OTERM764\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]_OTERM764\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]_OTERM762\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM762\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]_OTERM760\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]_OTERM760\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]_OTERM758\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM758\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]_OTERM756\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM754\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM754\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM750\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM750\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM746\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM746\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM743\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM743\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[56]_OTERM741\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[56]_OTERM741\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM737\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM737\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM734\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM734\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[59]_OTERM732\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[59]_OTERM732\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM728\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM728\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM725\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM725\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[50]_OTERM723\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[50]_OTERM723\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM719\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM719\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM715\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM715\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM713\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM713\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM711\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM711\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[51]_OTERM709\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[51]_OTERM709\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[26]_OTERM707\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM707\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[26]_OTERM705\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[26]_OTERM705\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM703\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM703\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM701\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM701\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[27]_OTERM699\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[27]_OTERM699\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM697\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM697\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM695\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM695\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[17]_OTERM693\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[17]_OTERM693\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM691\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM691\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM689\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM689\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM687\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM685\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM685\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]_OTERM683\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM683\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM681\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM681\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM679\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM679\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[46]_OTERM677\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[46]_OTERM677\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM675\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM675\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM673\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM673\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[47]_OTERM671\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[47]_OTERM671\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM669\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM669\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM667\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM667\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[31]_OTERM665\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[31]_OTERM665\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM663\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM663\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM661\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM661\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM659\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM659\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM657\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM657\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[20]_OTERM655\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[20]_OTERM655\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM651\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM651\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM649\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM649\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM647\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM647\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[48]_OTERM645\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[48]_OTERM645\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM643\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM643\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM641\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM641\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM639\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM639\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[16]_OTERM637\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[16]_OTERM637\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM635\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM635\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM633\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM633\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]_OTERM631\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]_OTERM631\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM629\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM629\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM627\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM627\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM625\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM625\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM623\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM623\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM621\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM621\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM619\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM619\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[52]_OTERM617\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[52]_OTERM617\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM615\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM615\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM613\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM613\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM611\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM611\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM609\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM609\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM607\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM607\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT[0]_OTERM605\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT[0]_OTERM605\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM603\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM603\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM601\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM601\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM599\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM599\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM597\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM597\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM595\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM595\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]_OTERM593\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM593\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM591\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM591\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM589\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM589\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[0]_OTERM587\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[0]_OTERM587\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM585\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM585\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM583\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM583\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM581\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM581\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[1]_OTERM579\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[1]_OTERM579\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM577\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM577\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM575\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM575\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]_OTERM573\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]_OTERM573\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM571\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM571\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM569\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM569\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]_OTERM567\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]_OTERM567\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM565\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM565\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM563\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM563\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]_OTERM561\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]_OTERM561\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM559\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM559\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM557\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM557\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]_OTERM555\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]_OTERM555\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM553\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM553\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM551\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM551\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM549\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM547\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM547\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM545\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM545\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]_OTERM543\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]_OTERM543\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM541\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM539\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM537\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM535\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM533\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM531\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM529\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM529\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM527\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM527\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]_OTERM525\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]_OTERM525\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM523\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM523\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM521\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM521\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM519\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM519\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM517\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM517\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult[31]_OTERM515\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult[31]_OTERM515\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM513\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM513\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM511\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM511\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM507\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM507\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM499\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM499\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM497\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM497\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[40]_OTERM495\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[40]_OTERM495\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM491\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM491\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM489\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM489\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM487\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM487\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM485\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM485\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[43]_OTERM483\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[43]_OTERM483\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM481\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM481\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM479\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM479\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[6]_OTERM477\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[6]_OTERM477\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM475\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM475\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM473\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM473\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM471\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM471\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[30]_OTERM469\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[30]_OTERM469\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM467\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM467\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM465\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM465\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[32]_OTERM463\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[32]_OTERM463\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM461\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM461\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM459\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM459\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[33]_OTERM457\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[33]_OTERM457\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM455\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM455\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM453\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM453\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM451\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM451\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[5]_OTERM449\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[5]_OTERM449\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM447\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM447\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM445\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM445\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM443\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM443\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM441\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM441\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM439\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM439\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM437\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM437\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[4]_OTERM435\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[4]_OTERM435\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM433\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM433\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM431\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM431\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[48]_OTERM429\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[48]_OTERM429\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM427\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM427\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM425\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM425\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM423\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM423\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[49]_OTERM421\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[49]_OTERM421\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM417\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM417\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM415\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM415\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM413\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM413\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM411\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM411\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[49]_OTERM409\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[49]_OTERM409\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM407\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM407\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM405\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM405\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[23]_OTERM403\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[23]_OTERM403\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM401\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM401\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM399\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM399\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[6]_OTERM397\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[6]_OTERM397\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM395\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM395\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM393\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM393\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[9]_OTERM391\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[9]_OTERM391\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM389\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM389\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM387\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM387\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[4]_OTERM385\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[4]_OTERM385\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM383\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM383\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM381\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM381\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM379\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM379\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM377\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM377\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[2]_OTERM375\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[2]_OTERM375\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM373\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM373\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM371\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM371\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM369\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM369\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[63]_OTERM367\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[63]_OTERM367\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA[0]_OTERM363\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA[0]_OTERM363\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM361\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM361\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM359\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM359\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[39]_OTERM357\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[39]_OTERM357\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM355\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM355\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM353\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM353\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM351\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM351\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM349\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM349\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[32]_OTERM347\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[32]_OTERM347\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM345\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM345\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM343\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM343\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM341\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM341\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[14]_OTERM339\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[14]_OTERM339\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM337\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM337\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM335\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM335\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM333\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM333\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM331\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM331\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM329\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM329\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[15]_OTERM327\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[15]_OTERM327\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM325\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM325\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM323\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM323\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM321\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM321\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM319\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM319\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[0]_OTERM317\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[0]_OTERM317\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM313\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM313\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM311\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM311\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM309\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM309\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM307\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM307\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM305\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM305\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[2]_OTERM303\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[2]_OTERM303\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM301\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM301\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM299\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM299\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_2_OTERM297\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_2_OTERM297\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM295\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM295\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM293\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM293\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[47]_OTERM291\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[47]_OTERM291\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM289\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM289\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM287\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM287\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM285\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM285\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[62]_OTERM283\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[62]_OTERM283\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM279\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM279\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM277\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM277\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[61]_OTERM275\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[61]_OTERM275\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM273\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM273\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM271\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM271\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[54]_OTERM269\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[54]_OTERM269\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM265\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM265\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM263\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM263\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[58]_OTERM261\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[58]_OTERM261\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM257\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM257\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM255\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM255\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[53]_OTERM253\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[53]_OTERM253\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM249\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM249\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM247\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM247\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[55]_OTERM245\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[55]_OTERM245\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM243\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM243\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM241\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM241\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM239\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM239\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM237\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM237\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[46]_OTERM235\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[46]_OTERM235\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM231\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM231\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM229\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM229\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM227\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM227\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM225\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM225\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[60]_OTERM223\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[60]_OTERM223\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM165\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM165\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM163\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM163\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[45]_OTERM161\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[45]_OTERM161\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM159\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM159\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM157\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM157\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[44]_OTERM155\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[44]_OTERM155\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]_OTERM151\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM151\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]_OTERM149\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]_OTERM149\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM145\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM145\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM143\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM143\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM141\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM141\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM139\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM139\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[38]_OTERM137\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[38]_OTERM137\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM135\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM135\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM133\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM133\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[41]_OTERM131\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[41]_OTERM131\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM129\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM129\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM127\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM127\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[37]_OTERM125\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[37]_OTERM125\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM123\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM123\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM121\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM121\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[39]_OTERM119\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[39]_OTERM119\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM117\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM117\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM115\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM115\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[36]_OTERM113\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[36]_OTERM113\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM111\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM111\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM109\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM109\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM107\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM107\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM105\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM105\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[35]_OTERM103\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[35]_OTERM103\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[12]_OTERM101\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]_OTERM101\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[13]_OTERM99\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]_OTERM99\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[14]_OTERM97\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]_OTERM97\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[15]_OTERM95\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]_OTERM95\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM93\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM93\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]_OTERM91\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]_OTERM91\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM89\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[31]~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[31]~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector77~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector77~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux316~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux316~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux316~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux370~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux370~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux370~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux340~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux340~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux340~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux402~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux402~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux402~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux118~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux118~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux118~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux54~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux54~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux54~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux182~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux182~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux182~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux246~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux246~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux246~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector73~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector73~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux312~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux312~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux312~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux366~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux366~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux366~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux336~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux336~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux336~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux398~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux398~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux398~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux114~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux114~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux114~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux50~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux50~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux50~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux178~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux178~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux178~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux242~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux242~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux242~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1455~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1455~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1455~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1391~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1391~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux327~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux327~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1571~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1571~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1571~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1453~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1453~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1453~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux325~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux325~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1569~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1569~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux266~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux266~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[29]~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[29]~57_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector79~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector79~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux318~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux318~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux318~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux372~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux372~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux372~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux342~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux342~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux342~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux404~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux404~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux404~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux120~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux120~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux120~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux56~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux56~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux56~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux184~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux184~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux184~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux248~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux248~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux248~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[33]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[33]~52_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector75~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector75~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux314~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux314~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux314~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux368~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux368~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux368~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux338~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux338~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux338~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux400~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux400~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux400~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux116~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux116~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux116~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux52~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux52~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux52~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux180~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux180~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux180~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux244~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux244~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux244~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1457~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1457~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1457~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1393~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1393~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux329~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux329~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1573~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1573~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1573~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1452~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1452~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1452~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1388~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1388~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux324~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux324~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1568~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1568~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux265~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux265~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[30]~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[30]~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector78~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector78~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux317~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux317~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux317~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux371~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux371~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux371~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux341~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux341~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux341~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux403~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux403~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux403~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux119~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux119~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux119~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux55~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux55~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux55~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux183~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux183~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux183~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux247~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux247~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux247~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector74~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector74~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux313~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux313~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux313~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux367~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux367~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux367~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux337~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux337~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux337~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux399~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux399~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux399~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux115~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux115~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux115~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux51~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux51~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux51~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux179~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux179~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux179~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux243~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux243~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux243~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1456~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1456~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1456~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1392~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1392~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux328~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux328~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1572~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1572~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1572~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1358~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1358~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1379~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1379~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_WidthCounter\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_WidthCounter\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1377~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1377~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~17_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~17_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(40) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(40);
-\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(1) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(1);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[41]~16_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[41]~16_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA~14_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~14_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~23_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~23_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(22) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(22);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(6) <= NOT \myVirtualToplevel|UART0|TX_DATA\(6);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(14) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(14);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][20]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][19]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][18]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][8]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][14]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][13]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][2]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][1]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][7]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][6]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][12]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][5]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][4]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][3]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][17]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][22]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][22]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][24]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][24]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][25]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][25]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][26]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][26]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][16]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][15]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][27]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][27]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][11]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][23]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][23]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][21]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][29]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][29]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][28]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][28]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][10]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][9]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][31]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][31]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][30]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][30]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~3_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal0~3_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~2_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal0~2_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~1_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal0~1_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal0~0_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~1_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\;
-\myVirtualToplevel|ALT_INV_TIMER_REG_REQ~q\ <= NOT \myVirtualToplevel|TIMER_REG_REQ~q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(11) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector117~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector117~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~47_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector76~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector76~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[32]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[32]~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux315~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux315~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux315~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux369~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux369~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux369~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux339~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux339~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux339~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux401~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux401~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux401~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux117~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux117~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux117~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux53~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux53~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux53~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux181~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux181~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux181~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux245~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux245~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux245~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1454~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1454~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1454~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1390~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1390~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux326~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux326~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1570~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1570~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux267~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux267~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector72~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector72~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux311~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux311~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux311~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux365~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux365~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux365~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux335~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux335~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux335~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux397~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux397~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux397~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux113~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux113~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux113~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux49~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux49~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux49~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux177~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux177~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux177~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux241~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux241~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux241~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1450~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1450~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1450~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1386~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1386~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux322~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux322~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1566~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1566~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux263~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux263~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1383~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1383~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector69~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector69~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux308~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux308~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux308~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux362~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux362~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux362~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux332~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux332~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux332~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux394~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux394~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux394~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux110~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux110~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux110~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux46~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux46~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux46~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector65~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector65~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux304~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux304~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux304~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux358~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux358~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux358~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux328~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux328~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux328~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux390~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux390~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux390~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux106~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux106~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux106~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux42~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux42~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux42~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux170~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux170~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux170~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux234~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux234~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux234~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector71~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector71~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux310~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux310~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux310~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux364~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux364~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux364~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux334~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux334~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux334~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux396~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux396~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux396~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux112~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux112~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux112~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux48~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux48~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux48~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux176~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux176~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux176~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux240~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux240~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux240~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector67~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector67~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux306~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux306~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux306~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux360~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux360~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux360~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux330~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux330~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux330~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux392~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux392~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux392~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux108~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux108~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux108~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux44~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux44~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux44~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux172~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux172~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux172~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux236~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux236~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux236~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[60]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[60]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1449~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1449~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1449~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1385~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1385~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[34]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[34]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add48~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add48~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux321~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux321~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add45~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1565~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1565~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux262~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux262~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add52~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add52~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE[7]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE[7]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[62]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[62]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1384~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1384~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~163_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~163_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector70~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector70~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux309~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux309~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux309~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux363~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux363~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux363~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux333~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux333~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux333~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux395~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux395~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux395~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux111~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux111~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux111~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux47~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux47~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux47~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector66~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector66~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux305~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux305~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux305~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux359~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux359~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux359~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux329~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux329~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux329~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux391~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux391~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux391~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux107~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux107~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux107~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux43~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux43~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux43~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux171~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux171~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux171~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux235~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux235~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux235~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP[23]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_POST_CRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_POST_CRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_POST_CRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_POST_CRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_POST_CRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr172~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr172~combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA4~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA4~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA4~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA4~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DATA3~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DATA3~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DATA3~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DATA3~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_STACK_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_STACK_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_STACK_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux208~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux208~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux208~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux272~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux272~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux272~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1481~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1481~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[29]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[29]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1417~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[23]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[23]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1537~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1537~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add39~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add39~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add39~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add39~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1593~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1593~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[9]~81_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[9]~81_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector99~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector99~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux140~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux140~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux140~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux76~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux76~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux76~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux204~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux204~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux204~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux268~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux268~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux268~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1477~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1477~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1413~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1413~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1535~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1535~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1535~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1591~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1591~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~79_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~79_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector102~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector102~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[6]~78_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[6]~78_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux79~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux79~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux79~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[10]~77_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[10]~77_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector98~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector98~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux139~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux139~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux139~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux75~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux75~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux75~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux203~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux203~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux203~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux267~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux267~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux267~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1476~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1476~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1476~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1412~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1412~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1534~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1534~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1534~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1590~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1590~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector120~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector120~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(14) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1478~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1478~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1536~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1536~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1536~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1592~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1592~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[8]~76_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[8]~76_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector100~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector100~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux141~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux141~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux141~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux77~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux77~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux77~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux205~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux205~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux205~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux269~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux269~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux269~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[12]~75_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[12]~75_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector96~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector96~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux137~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux137~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux137~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux73~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux73~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux73~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux201~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux201~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux201~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux265~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux265~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux265~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1474~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1474~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1474~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1532~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1532~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1532~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1588~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1588~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[15]~74_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[15]~74_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector93~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector93~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux134~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux134~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux134~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux70~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux70~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux70~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux198~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux198~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux198~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux262~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux262~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux262~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1471~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1471~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1471~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1529~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1529~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1529~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1585~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1585~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux509~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux509~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[19]~73_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[19]~73_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector89~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector89~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux130~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux130~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux130~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux66~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux66~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux66~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux194~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux194~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux194~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux258~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux258~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux258~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1467~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1467~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1467~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1403~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1403~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1525~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1525~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1581~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1581~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[13]~72_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[13]~72_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector95~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector95~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux136~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux136~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux136~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux72~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux72~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux72~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux200~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux200~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux200~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux264~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux264~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux264~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1473~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1473~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1473~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1531~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1531~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1531~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1587~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1587~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[17]~71_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[17]~71_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector91~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector91~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux132~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux132~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux132~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux68~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux68~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux68~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux196~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux196~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux196~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux260~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux260~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux260~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1469~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1469~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1469~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1527~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1527~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1583~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1583~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[14]~70_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[14]~70_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector94~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector94~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux135~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux135~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux135~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux71~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux71~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux71~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux199~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux199~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux199~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux263~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux263~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux263~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1472~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1472~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1472~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1530~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1530~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1530~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1586~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1586~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[18]~69_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[18]~69_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector90~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector90~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux131~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux131~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux131~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux67~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux67~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux67~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux195~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux195~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux195~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux259~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux259~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux259~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1468~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1468~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1468~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1526~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1526~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1582~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1582~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~24_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~24_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[24]~23_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[24]~23_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(38) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(38);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA~18_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~18_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~25_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~25_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(24) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(24);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(16) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(16);
-\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(13) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector115~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector115~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[16]~68_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[16]~68_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector92~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector92~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux133~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux133~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux133~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux69~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux69~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux69~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux197~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux197~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux197~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux261~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux261~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux261~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1470~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1470~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1470~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1406~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1406~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1528~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1528~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1584~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1584~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[20]~67_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[20]~67_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector88~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector88~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux129~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux129~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux129~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux65~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux65~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux65~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux193~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux193~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux193~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux257~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux257~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux257~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1466~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1466~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1466~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1524~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1524~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1580~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1580~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[23]~66_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[23]~66_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector85~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector85~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux126~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux126~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux126~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux62~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux62~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux62~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1399~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1399~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[27]~65_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[27]~65_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector81~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector81~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux320~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux320~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux320~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux374~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux374~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux374~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux344~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux344~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux344~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux406~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux406~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux406~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux122~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux122~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux122~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux58~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux58~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux58~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux186~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux186~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux186~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux250~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux250~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux250~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1459~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1459~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1459~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1395~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1395~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux331~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux331~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1575~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1575~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1575~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[21]~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[21]~64_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector87~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector87~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux128~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux128~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux128~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux64~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux64~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux64~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux192~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux192~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux192~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux256~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux256~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux256~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2[34]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2[34]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add45~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add45~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1465~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1465~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1465~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[42]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[42]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1523~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1523~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[42]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[42]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1579~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1579~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[42]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[42]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[25]~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[25]~63_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector83~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector83~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux322~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux322~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux322~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux408~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux408~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux408~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux376~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux376~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux376~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux124~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux124~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux124~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux60~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux60~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux60~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux188~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux188~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux188~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux252~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux252~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux252~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1461~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1461~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1397~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1397~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux333~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux333~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1577~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1577~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1577~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[22]~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[22]~62_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector86~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector86~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux127~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux127~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux127~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux63~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux63~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux63~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1400~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1400~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[26]~61_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[26]~61_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector82~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector82~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux321~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux321~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux321~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux375~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux375~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux375~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux345~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux345~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux345~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux407~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux407~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux407~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux123~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux123~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux123~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux59~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux59~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux59~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux187~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux187~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux187~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux251~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux251~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux251~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1460~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1460~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1460~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1396~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1396~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux332~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux332~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1576~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1576~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1576~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(16);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[40]~21_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~21_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[40]~20_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[40]~20_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~19_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~19_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal8~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal8~0_combout\;
-\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(0) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(0);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA~16_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~16_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~24_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~24_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(23) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(23);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(7) <= NOT \myVirtualToplevel|UART0|TX_DATA\(7);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(15) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(15);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_index\(0) <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_index\(0);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(12) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector116~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector116~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux409~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux409~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux409~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux377~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux377~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux377~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux125~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux125~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux125~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux61~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux61~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux61~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux189~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux189~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux189~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux253~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux253~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux253~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[24]~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[24]~60_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector84~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector84~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux323~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux323~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux323~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1462~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1462~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1398~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1398~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux334~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux334~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1578~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1578~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1578~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[28]~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[28]~59_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector80~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector80~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux319~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux319~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux319~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux373~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux373~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux373~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux343~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux343~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux343~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux405~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux405~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux405~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux121~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux121~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux121~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux57~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux57~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux57~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux185~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux185~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux185~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux249~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux249~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux249~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.SP\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1458~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1458~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1458~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux330~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux330~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1574~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1574~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1574~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1451~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1451~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1451~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1387~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1387~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.word\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.word\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux323~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux323~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1567~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1567~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux264~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux264~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM87\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM85\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM85\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]_OTERM83\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]_OTERM83\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM81\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM81\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]_OTERM79\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]_OTERM79\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[16]_OTERM77\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]_OTERM77\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]_OTERM75\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]_OTERM73\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[20]_OTERM71\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]_OTERM71\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]_OTERM69\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[17]_OTERM67\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]_OTERM67\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]_OTERM65\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[19]_OTERM63\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]_OTERM63\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM61\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM61\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]_OTERM59\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]_OTERM59\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM57\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM55\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[9]_OTERM53\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]_OTERM53\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[10]_OTERM51\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]_OTERM51\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[11]_OTERM49\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]_OTERM49\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM47\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM45\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM45\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM43\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM41\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM41\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[8]_OTERM39\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]_OTERM39\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM37\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM35\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM35\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM33\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM31\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM31\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM29\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM29\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]_OTERM27\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]_OTERM27\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM25\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM23\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM23\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM21\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM21\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]_OTERM19\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]_OTERM19\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM17\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM15\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM15\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM11\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM9\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM7\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM5\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM5\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1\;
-\mypll|altpll_component|auto_generated|ALT_INV_wire_generic_pll1_locked\ <= NOT \mypll|altpll_component|auto_generated|wire_generic_pll1_locked\;
-\ALT_INV_UART_RX_1~input_o\ <= NOT \UART_RX_1~input_o\;
-\ALT_INV_UART_RX_0~input_o\ <= NOT \UART_RX_0~input_o\;
-\ALT_INV_SDCARD_MISO[0]~input_o\ <= NOT \SDCARD_MISO[0]~input_o\;
-\ALT_INV_KEY~input_o\ <= NOT \KEY~input_o\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~438_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~436_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~436_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~435_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~435_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~160_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1404~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1404~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~166_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~166_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~165_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~17_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~17_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~16_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1409~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1409~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1405~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1405~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1408~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1408~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1410~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1410~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1407~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1407~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1401~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1401~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~434_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~434_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~433_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~433_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~432_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~432_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~431_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~431_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~430_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~430_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~429_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~429_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~428_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~428_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~427_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~427_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~426_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~426_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC[23]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC[23]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~164_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~164_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~92_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[3]~92_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~90_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[4]~90_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~88_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[5]~88_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~86_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[6]~86_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~84_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[7]~84_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~82_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[8]~82_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~80_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[9]~80_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~78_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[10]~78_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~76_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[11]~76_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~74_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[12]~74_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~72_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[13]~72_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~70_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[14]~70_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~68_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[15]~68_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1402~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1402~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector214~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector214~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector213~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector213~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector212~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector211~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector210~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector209~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector209~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector208~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector207~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector207~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector206~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector206~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector205~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector203~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector202~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector202~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector201~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector201~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector199~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector198~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector197~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector197~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector196~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector196~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector195~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector194~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector194~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector193~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~157_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~157_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~156_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~155_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1414~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1414~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~152_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~152_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~151_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~151_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~150_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~150_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~149_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~149_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector157~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector157~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector157~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(1);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[3]~41_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[3]~41_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(2);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector154~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector154~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(3);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[5]~39_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[5]~39_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(4);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[6]~37_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[6]~37_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(5);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(6);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(7);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[9]~34_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[9]~34_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(9) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(9);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[11]~32_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[11]~32_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(11) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(11);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[13]~30_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[13]~30_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(13) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(13);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[15]~28_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[15]~28_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[16]~26_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[16]~26_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(15) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(15);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(16) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1617~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1617~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1505~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1505~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1443~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1443~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1561~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1561~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1561~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1619~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1619~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1507~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1507~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1445~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1445~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1563~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1563~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1563~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1618~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1618~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1506~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1506~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1444~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1444~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1562~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1562~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1562~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1446~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1446~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1620~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1620~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1508~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1508~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux432~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux432~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1564~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1564~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1564~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR:tInsnExec~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR:tInsnExec~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux428~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux428~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1442~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1442~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1560~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1560~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1560~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1616~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1616~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1501~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1501~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux425~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux425~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1439~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1439~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1557~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1557~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1557~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1613~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1613~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1497~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1497~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1497~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1553~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1553~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1609~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1609~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1503~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1503~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1441~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1441~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1559~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1559~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1559~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1615~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1615~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1499~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1499~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1499~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1437~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1437~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1555~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1555~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1611~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1611~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1502~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1502~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1440~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1440~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1558~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1558~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1558~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1614~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1614~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1498~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1498~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1498~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1436~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1436~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1554~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1554~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1610~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1610~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1500~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1500~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1500~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1438~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1438~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1556~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1556~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1612~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1612~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1496~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1496~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1496~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1434~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1434~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1552~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1552~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1608~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1608~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1431~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1431~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux282~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux282~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux282~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux154~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux154~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux154~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux90~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux90~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux90~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux218~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux218~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux218~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1491~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1491~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1427~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1547~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1547~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1603~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1603~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1495~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1495~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1495~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1433~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1433~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[10]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[10]~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1551~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1551~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3[10]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3[10]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1607~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1607~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4[12]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4[12]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add40~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add40~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux284~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux284~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux284~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux156~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux156~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux156~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux92~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux92~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux92~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux220~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux220~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1493~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1493~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1429~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1429~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1549~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1549~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1605~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1605~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux283~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux283~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux283~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux155~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux155~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux155~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux91~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux91~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux91~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux219~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux219~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux219~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1548~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1548~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1548~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1604~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1604~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(16) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux93~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux93~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux93~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux285~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux285~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux285~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux157~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux157~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux157~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux221~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux221~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux221~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1494~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1494~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux418~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux418~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux418~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1430~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1430~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1550~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1550~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1550~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1606~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1606~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux153~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux153~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux153~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux89~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux89~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux89~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux217~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux217~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux217~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux281~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux281~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux281~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1426~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1426~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1546~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1546~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1546~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1602~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1602~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux150~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux150~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux150~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux86~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux86~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux86~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux214~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux214~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux214~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux278~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux278~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux278~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1487~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1487~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1543~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1543~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1599~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1599~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux523~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux523~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[3]~98_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~98_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[3]~97_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[3]~97_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux146~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux146~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux146~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux82~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux82~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux82~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux210~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux210~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux210~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux274~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux274~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux274~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1483~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1483~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1539~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1539~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1595~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1595~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux152~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux152~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux152~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux88~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux88~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux88~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux216~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux216~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux216~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux280~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux280~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux280~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1489~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1489~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1425~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1545~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1545~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1601~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1601~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~95_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~95_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~94_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~94_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux148~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux148~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux148~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux84~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux84~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux84~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux212~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux212~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux212~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux276~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux276~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux276~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1485~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1485~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1421~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1541~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1541~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1597~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1597~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux151~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux151~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux151~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux87~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux87~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux87~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux215~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux215~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux215~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux279~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux279~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux279~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1544~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1544~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1544~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1600~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1600~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[2]~92_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~92_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[2]~91_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[2]~91_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[1]~90_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[1]~90_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux147~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux147~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux147~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux83~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux83~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux83~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux211~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux211~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux211~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux275~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux275~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux275~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1420~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1420~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1419~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1419~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1596~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1596~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(15) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux149~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux149~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux149~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux85~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux85~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux85~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux213~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux213~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux213~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux277~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux277~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux277~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1422~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1422~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1598~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1598~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[4]~87_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[4]~87_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector104~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector104~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux145~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux145~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux145~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux81~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux81~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux81~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux209~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux209~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux209~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux273~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux273~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux273~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1418~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1418~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1594~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1594~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[7]~85_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[7]~85_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector101~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector101~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux142~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux142~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux142~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux78~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux78~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux78~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1415~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1415~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[11]~84_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[11]~84_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector97~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector97~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux138~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux138~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux138~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux74~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux74~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux74~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux202~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux202~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux202~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux266~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux266~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux266~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1475~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1475~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1475~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1411~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1411~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1533~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1533~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1533~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1589~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1589~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[5]~82_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[5]~82_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector103~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector103~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux144~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux144~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux144~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux80~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux80~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux80~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_STACK_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_STACK_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_PC~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_PC~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_PC~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_PC~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_SP~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_SP~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_SP~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_SP~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_SP~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_DECODED_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_DECODED_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_DECODED_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_DECODED_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DECODED_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].WRITE_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].WRITE_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].WRITE_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].WRITE_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1354~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1354~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_PC~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_PC~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA[57]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA[57]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_DATA_PRTMODE[0]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_DATA_PRTMODE[0]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~162_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~162_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1356~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1356~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_PRE_CR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_PRE_CR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_PRE_CR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_PRE_CR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_PRE_CR~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~14_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~14_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~13_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~13_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(41) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(41);
-\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(2) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(2);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA~12_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~12_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~22_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~22_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(21) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(21);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(5) <= NOT \myVirtualToplevel|UART0|TX_DATA\(5);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(13) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(13);
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA~18_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~18_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~19_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~19_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(18) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(18);
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(2) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(2);
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA~18_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~18_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~19_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~19_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(18) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(18);
-\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(2) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~30_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA~16_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~16_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~18_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~18_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(17) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(17);
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA~16_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~16_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~18_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~18_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(17) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(17);
-\myVirtualToplevel|UART1|ALT_INV_Add9~39_combout\ <= NOT \myVirtualToplevel|UART1|Add9~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~25_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(14) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(14);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(0) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(0);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(15) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(13) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(13);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(12) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(12);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(6) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(6);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(5) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(5);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(4) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(4);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(3) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(3);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(2) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(2);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(1) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(1);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(11) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(10) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(10);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(9) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(9);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(8) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8);
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(7) <= NOT \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(7);
-\myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~2_combout\ <= NOT \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(1) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(1);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(14) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(0) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(0);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(15) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(13) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(13);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(12) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(12);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(6) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(6);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(5) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(5);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(4) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(4);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(3) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(3);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(2) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(2);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(1) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(1);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(11) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(11);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(10) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(10);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(9) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(9);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(8) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8);
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(7) <= NOT \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(7);
-\myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~2_combout\ <= NOT \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(1) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(1);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~8_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~7_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~7_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~6_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~6_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~5_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~5_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~4_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~4_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~3_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~3_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~2_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~2_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~1_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Equal1~0_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescaled_tick~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|prescaled_tick~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled\(0) <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(0) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(0);
-\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(2) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(2);
-\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(3) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(3);
-\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(4) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(4);
-\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(5) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(5);
-\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(10) <= NOT \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(10);
-\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(10) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy[0]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy[0]~1_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending~6_combout\ <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~6_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending~5_combout\ <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[17]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector300~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[26]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[26]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector298~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector298~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[31]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[31]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector295~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector295~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[8]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[8]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[6]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[6]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[5]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[5]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[4]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[4]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[3]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[3]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector297~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector297~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan9~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan9~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_PreSetAddr~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_PreSetAddr~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector118~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector118~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector68~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector68~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux307~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux307~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux307~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux361~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux361~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux361~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux331~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux331~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux331~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux393~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux393~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux393~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux109~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux109~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux109~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux45~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux45~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux45~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux173~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux173~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux173~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux237~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux237~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux237~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector64~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector64~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux303~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux303~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux303~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux357~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux357~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux357~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux327~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux327~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux327~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux389~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux389~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux389~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux105~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux105~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux105~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux41~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux41~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux41~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux169~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux169~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux169~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux233~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux233~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux233~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux350~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux350~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux350~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux290~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux290~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux290~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux382~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux382~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux382~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux296~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux296~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux296~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux98~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux98~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux98~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux34~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux34~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux34~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux162~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux162~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux162~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux226~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux226~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux226~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector61~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector61~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector57~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector57~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux300~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux300~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux300~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux354~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux354~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux354~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux324~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux324~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux324~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux386~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux386~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux386~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux102~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux102~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux102~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux38~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux38~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux38~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux166~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux166~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux166~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux230~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux230~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux230~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux352~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux352~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux352~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux292~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux292~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux292~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux384~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux384~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux384~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux298~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux298~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux298~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux100~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux100~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux100~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux36~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux36~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux36~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux164~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux164~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux164~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux228~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux228~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux228~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector63~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector63~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector59~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector59~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux302~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux302~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux302~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux356~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux356~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux356~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux326~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux326~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux326~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux388~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux388~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux388~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux104~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux104~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux104~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux40~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux40~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux40~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux168~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux168~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux168~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux232~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux232~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux232~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux351~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux351~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux351~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux291~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux291~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux291~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux383~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux383~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux383~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux297~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux297~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux297~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux99~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux99~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux99~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux35~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux35~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux35~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux163~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux163~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux163~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux227~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux227~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux227~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_NOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector62~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector62~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector58~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector58~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux301~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].PC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].PC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].PC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].PC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux301~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux301~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].PC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].PC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].PC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].PC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux355~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux355~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux355~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux325~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].SP\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].SP\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].SP\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].SP\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux325~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux325~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].SP\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].SP\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].SP\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].SP\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux387~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux387~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux387~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux103~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux103~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux103~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux39~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux39~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux39~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux167~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux167~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux167~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux231~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux231~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux231~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.STACK_TOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_POST_CRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_POST_CRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_POST_CRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_POST_CRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA4~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA4~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA4~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA4~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DATA3~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DATA3~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DATA3~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DATA3~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_STACK_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_STACK_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_STACK_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_STACK_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_PC~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_PC~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_PC~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_PC~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_SP~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_SP~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_SP~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_SP~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_DECODED_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_DECODED_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_DECODED_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_DECODED_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].WRITE_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].WRITE_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].WRITE_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].WRITE_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Decoder0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Decoder0~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT[2]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.FMT_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_PRE_CR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_PRE_CR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_PRE_CR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_PRE_CR~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~4_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~4_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~3_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~3_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector115~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector115~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(42) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(42);
-\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(3) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(3);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA~10_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~10_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~21_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~21_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(20) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(20);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(4) <= NOT \myVirtualToplevel|UART0|TX_DATA\(4);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(12) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(12);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]~35_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(1);
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][1]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][1]~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(1) <= NOT \myVirtualToplevel|UART0|RX_DATA\(1);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~98_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~98_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FULL_V~q\ <= NOT \myVirtualToplevel|UART1|RX_FULL_V~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FULL_V~q\ <= NOT \myVirtualToplevel|UART0|RX_FULL_V~q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(1) <= NOT \myVirtualToplevel|UART1|RX_DATA\(1);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~97_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~97_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~96_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~96_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~95_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~95_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~94_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~94_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1316~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1316~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~147_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~147_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~146_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~146_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~144_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~142_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~142_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~141_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~141_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~137_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~137_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]~34_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(0);
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][0]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][0]~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(0) <= NOT \myVirtualToplevel|UART0|RX_DATA\(0);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~92_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~92_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_EMPTY_V~q\ <= NOT \myVirtualToplevel|UART1|RX_EMPTY_V~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_EMPTY_V~q\ <= NOT \myVirtualToplevel|UART0|RX_EMPTY_V~q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(0) <= NOT \myVirtualToplevel|UART1|RX_DATA\(0);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~91_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~91_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~90_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~90_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~89_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~89_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~88_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~88_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Add9~34_combout\ <= NOT \myVirtualToplevel|UART1|Add9~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~135_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~135_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~134_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~130_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~130_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~129_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~128_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~122_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~122_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~121_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~121_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~120_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~116_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~113_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~113_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~112_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~112_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]~33_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][24]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][24]~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(8) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[24]~86_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[24]~86_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1323~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1323~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector981~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector981~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~47_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~108_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~108_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~101_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~101_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][27]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][27]~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(11) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(11);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[27]~32_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[27]~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~16_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]~31_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][26]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][26]~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(10) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~15_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][25]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][25]~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(9) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(9);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[25]~30_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[25]~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~99_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~99_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~98_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~98_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~97_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~97_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~96_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~96_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~95_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~95_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~94_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~94_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~92_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~92_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~91_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~91_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~88_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~88_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~8_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\;
-\myVirtualToplevel|ALT_INV_RTC_TICK_HALT~q\ <= NOT \myVirtualToplevel|RTC_TICK_HALT~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~33_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~33_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~32_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~32_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~31_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~31_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal3~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal3~3_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\ <= NOT \myVirtualToplevel|UART0|RX_STATE.start~q\;
-\myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\ <= NOT \myVirtualToplevel|UART0|Equal1~4_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal1~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal1~3_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(15) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(15);
-\myVirtualToplevel|UART0|ALT_INV_Equal1~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal1~2_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal1~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal1~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~0_combout\ <= NOT \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[0]~1_combout\ <= NOT \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\ <= NOT \myVirtualToplevel|UART0|RX_STATE.idle~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\ <= NOT \myVirtualToplevel|UART0|RX_STATE.bits~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(0) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(0);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~33_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~33_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~32_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~32_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~31_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~31_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal3~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal3~3_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~q\ <= NOT \myVirtualToplevel|UART1|RX_STATE.start~q\;
-\myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\ <= NOT \myVirtualToplevel|UART1|Equal1~4_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal1~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal1~3_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(15) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(15);
-\myVirtualToplevel|UART1|ALT_INV_Equal1~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal1~2_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal1~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal1~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~0_combout\ <= NOT \myVirtualToplevel|UART1|RX_STATE.stop~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~1_combout\ <= NOT \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\ <= NOT \myVirtualToplevel|UART1|RX_STATE.idle~q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(0) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(0);
-\myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\ <= NOT \myVirtualToplevel|UART1|RX_STATE.bits~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_process_3~0_combout\ <= NOT \myVirtualToplevel|UART0|process_3~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_process_3~0_combout\ <= NOT \myVirtualToplevel|UART1|process_3~0_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_ticks\(0) <= NOT \myVirtualToplevel|TIMER:TIMER1|ticks\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1320~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1320~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~29_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~29_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][31]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][31]~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(15) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~11_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][30]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][30]~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(14) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(14);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[30]~28_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[30]~28_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]~27_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][29]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][29]~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(13) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~9_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][28]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][28]~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(12) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(12);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[26]~78_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[28]~26_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[28]~26_combout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~1_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR[2]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[2]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR[0]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[0]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal1~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1349~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1349~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_int~q\ <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|int~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal138~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal138~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_interruptSuspendedAddr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|interruptSuspendedAddr\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~104_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~104_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~102_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~102_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~95_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~95_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr137~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr137~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr133~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr133~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~94_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~94_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~92_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~92_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~90_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~90_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr141~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr141~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~88_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~88_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr140~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr140~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~87_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~87_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr147~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr147~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr146~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr146~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~85_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~85_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr143~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr143~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~83_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~83_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal12~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr135~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr135~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~82_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~82_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~158_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~158_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~157_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~157_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~156_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~156_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~155_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~155_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~154_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~154_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~152_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~152_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~151_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~151_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~149_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~149_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector387~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector387~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal131~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal131~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~80_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~80_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~79_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~79_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux133~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux133~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux135~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux135~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr151~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr151~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr150~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr150~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~78_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~78_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr149~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr149~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~77_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~77_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~76_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~76_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal67~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal67~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr139~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr139~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~71_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~71_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal46~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal46~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr138~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr138~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~69_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~69_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~68_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~68_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~67_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~67_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr144~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr144~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~66_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~66_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~64_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~63_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~59_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr148~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr148~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal99~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal99~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux121~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux121~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux123~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux123~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr136~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr136~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr131~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr131~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~50_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr132~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr132~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tDecodedOpcode~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tDecodedOpcode~47_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal135~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~57_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~56_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~146_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~146_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~145_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~145_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~144_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~144_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~143_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~143_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~141_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~141_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~140_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~140_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~139_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~139_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~138_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~138_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~136_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~136_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~135_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~135_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~134_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~134_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~133_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~133_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~131_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~131_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~130_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~130_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~129_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~129_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~128_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~128_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~126_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~126_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~125_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~125_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~124_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~124_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~123_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~123_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~121_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~121_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~120_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~120_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~119_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~119_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~118_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~118_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~116_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~116_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~115_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~115_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~114_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~114_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~113_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~113_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~111_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~111_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~110_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~110_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~109_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~109_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~108_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~108_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~106_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~106_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~105_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~105_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~104_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~104_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~103_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~103_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~101_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~101_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~100_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~100_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~99_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~99_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~98_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~98_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~96_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~96_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~95_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~95_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~94_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~94_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~93_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~93_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~91_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~91_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~90_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~90_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~89_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~89_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~88_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~88_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~86_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~86_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~85_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~85_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~84_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~84_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~83_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~83_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~81_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~81_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~78_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~78_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~77_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~77_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~75_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~75_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~74_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~74_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~73_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~73_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~72_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~72_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~70_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~70_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~69_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~69_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~68_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~68_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~67_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~67_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~65_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~65_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~64_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~63_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~62_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~60_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal143~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal143~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~50_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~47_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux11~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux81~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux12~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux82~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux13~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux13~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux83~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux14~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux14~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector120~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector120~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector120~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[56]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[56]~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector52~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector52~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector52~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector48~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector48~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector48~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector45~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector45~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[61]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[61]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector47~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector47~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector47~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[60]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[60]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector46~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector46~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_ADD_SEPERATOR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_ADD_SEPERATOR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~50_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_POST_CRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_POST_CRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add4~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector13~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector13~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector13~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_DATA_PRTMODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[3]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[3]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA4~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DATA3~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT[21]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT[21]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector44~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector44~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector42~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector42~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_STACK_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_STACK_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_PC~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_PC~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_SP~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_SP~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_DECODED_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_DECODED_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.WRITE_OPCODE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.WRITE_OPCODE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal2~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal2~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.FMT_PRE_CR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.FMT_PRE_CR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_SPLITSPACE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_SPLITSPACE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector111~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector111~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_NIBBLECNT~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_NIBBLECNT~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~1_combout\;
-\myVirtualToplevel|ALT_INV_Selector14~1_combout\ <= NOT \myVirtualToplevel|Selector14~1_combout\;
-\myVirtualToplevel|ALT_INV_Selector14~0_combout\ <= NOT \myVirtualToplevel|Selector14~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[45]~9_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~9_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(44) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(44);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[45]~8_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[45]~8_combout\;
-\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(5) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux80~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~58_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(2);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~33_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~33_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~32_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~32_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~31_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~31_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal6~4_combout\ <= NOT \myVirtualToplevel|UART0|Equal6~4_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal6~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal6~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA~6_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~6_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~19_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~19_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(18) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(18);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(2) <= NOT \myVirtualToplevel|UART0|TX_DATA\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(10) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[0]~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[0]~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[0]~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[0]~56_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[0]~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~65_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~65_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[0]~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[0]~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[0]~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[0]~59_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[0]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[0]~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[1]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[1]~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[1]~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[1]~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~57_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[1]~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[1]~64_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[1]~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[1]~57_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[1]~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[1]~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[1]~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[0]~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[0]~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~62_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~61_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~61_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[0]~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[0]~60_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector573~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector573~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~80_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~80_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~79_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~79_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~78_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~78_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux176~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux176~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~67_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~67_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector442~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector442~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA~12_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~12_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~21_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~21_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(20) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(20);
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(4) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(4);
-\myVirtualToplevel|UART1|ALT_INV_Equal3~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal3~2_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal3~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal3~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal3~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal3~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal3~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal3~2_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal3~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal3~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal3~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal3~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA~12_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~12_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~21_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~21_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(20) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(20);
-\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(4) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(4);
-\myVirtualToplevel|UART1|ALT_INV_Add9~28_combout\ <= NOT \myVirtualToplevel|UART1|Add9~28_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~5_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector355~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector355~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1344~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1344~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~77_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~77_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~92_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~92_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~76_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~76_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~75_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~75_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux175~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux175~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux97~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~0_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(8) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(8);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~62_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~61_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~60_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(24) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(24);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(24) <= NOT \myVirtualToplevel|IO_DATA_READ\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1339~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1339~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~74_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~74_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~73_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~73_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux170~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux170~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~64_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~63_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA~10_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~10_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~25_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~25_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(24) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(24);
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(8) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(8);
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA~10_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~10_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~25_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~25_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(24) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(24);
-\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(8) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(8);
-\myVirtualToplevel|UART1|ALT_INV_Add9~27_combout\ <= NOT \myVirtualToplevel|UART1|Add9~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~72_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~72_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~83_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~83_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1340~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1340~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~71_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~71_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~70_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~70_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux171~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux171~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector998~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector998~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~61_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~61_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~60_combout\;
-\myVirtualToplevel|ALT_INV_SD_OVERRUN~0_combout\ <= NOT \myVirtualToplevel|SD_OVERRUN~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA~8_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~8_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~24_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~24_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(23) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(23);
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(7) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(7);
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA~8_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~8_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~24_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~24_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(23) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(23);
-\myVirtualToplevel|UART1|ALT_INV_Add9~26_combout\ <= NOT \myVirtualToplevel|UART1|Add9~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector352~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector352~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1341~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1341~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~69_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~69_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~78_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~78_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~68_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~68_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[26]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[26]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux172~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux172~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~57_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(11) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(11);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~59_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~58_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[27]~58_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~57_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[27]~57_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(27) <= NOT \myVirtualToplevel|IO_DATA_READ\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1336~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1336~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~67_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~67_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~66_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~66_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~65_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~65_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~64_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~63_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector994~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector994~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(10) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(10);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~56_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[26]~56_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~55_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[26]~55_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[26]~54_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[26]~54_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(26) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(26);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(26) <= NOT \myVirtualToplevel|IO_DATA_READ\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1337~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1337~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~62_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~69_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~69_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~61_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~61_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~60_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~59_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~57_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~56_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~52_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux96~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~0_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(9) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(9);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~52_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[25]~52_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~51_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[25]~51_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(25) <= NOT \myVirtualToplevel|IO_DATA_READ\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~64_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~64_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1338~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1338~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~52_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~50_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux169~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux169~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector996~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector996~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~48_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA~6_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~6_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~23_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~23_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(22) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(22);
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(6) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(6);
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA~6_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~6_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~23_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~23_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(22) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(22);
-\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(6) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(6);
-\myVirtualToplevel|UART1|ALT_INV_Add9~25_combout\ <= NOT \myVirtualToplevel|UART1|Add9~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector353~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector353~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1342~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1342~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~47_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux173~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux173~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~45_combout\;
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~2_combout\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\;
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~0_combout\ <= NOT \myVirtualToplevel|RTC_DAY_COUNTER~0_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\;
-\myVirtualToplevel|ALT_INV_process_1~5_combout\ <= NOT \myVirtualToplevel|process_1~5_combout\;
-\myVirtualToplevel|ALT_INV_Add9~1_combout\ <= NOT \myVirtualToplevel|Add9~1_combout\;
-\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER~1_combout\ <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\;
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\;
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\ <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~1_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~0_combout\ <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\;
-\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_process_1~4_combout\ <= NOT \myVirtualToplevel|process_1~4_combout\;
-\myVirtualToplevel|ALT_INV_process_1~3_combout\ <= NOT \myVirtualToplevel|process_1~3_combout\;
-\myVirtualToplevel|ALT_INV_process_1~2_combout\ <= NOT \myVirtualToplevel|process_1~2_combout\;
-\myVirtualToplevel|ALT_INV_Add9~0_combout\ <= NOT \myVirtualToplevel|Add9~0_combout\;
-\myVirtualToplevel|ALT_INV_process_1~1_combout\ <= NOT \myVirtualToplevel|process_1~1_combout\;
-\myVirtualToplevel|ALT_INV_process_1~0_combout\ <= NOT \myVirtualToplevel|process_1~0_combout\;
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(5);
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_Add7~1_combout\ <= NOT \myVirtualToplevel|Add7~1_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\;
-\myVirtualToplevel|ALT_INV_Add7~0_combout\ <= NOT \myVirtualToplevel|Add7~0_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\;
-\myVirtualToplevel|ALT_INV_Add6~1_combout\ <= NOT \myVirtualToplevel|Add6~1_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\ <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\;
-\myVirtualToplevel|ALT_INV_Add6~0_combout\ <= NOT \myVirtualToplevel|Add6~0_combout\;
-\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~2_combout\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~1_combout\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\ <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\;
-\myVirtualToplevel|ALT_INV_Equal13~1_combout\ <= NOT \myVirtualToplevel|Equal13~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal13~0_combout\ <= NOT \myVirtualToplevel|Equal13~0_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~1_combout\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~0_combout\ <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~0_combout\;
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER~0_combout\ <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\;
-\myVirtualToplevel|ALT_INV_Equal35~7_combout\ <= NOT \myVirtualToplevel|Equal35~7_combout\;
-\myVirtualToplevel|ALT_INV_Equal35~6_combout\ <= NOT \myVirtualToplevel|Equal35~6_combout\;
-\myVirtualToplevel|ALT_INV_Equal35~5_combout\ <= NOT \myVirtualToplevel|Equal35~5_combout\;
-\myVirtualToplevel|ALT_INV_Equal35~4_combout\ <= NOT \myVirtualToplevel|Equal35~4_combout\;
-\myVirtualToplevel|ALT_INV_Equal35~3_combout\ <= NOT \myVirtualToplevel|Equal35~3_combout\;
-\myVirtualToplevel|ALT_INV_Equal35~2_combout\ <= NOT \myVirtualToplevel|Equal35~2_combout\;
-\myVirtualToplevel|ALT_INV_Equal35~1_combout\ <= NOT \myVirtualToplevel|Equal35~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal35~0_combout\ <= NOT \myVirtualToplevel|Equal35~0_combout\;
-\myVirtualToplevel|ALT_INV_Equal36~1_combout\ <= NOT \myVirtualToplevel|Equal36~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal36~0_combout\ <= NOT \myVirtualToplevel|Equal36~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_INTR~4_combout\ <= NOT \myVirtualToplevel|UART0|RX_INTR~4_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_INTR~3_combout\ <= NOT \myVirtualToplevel|UART0|RX_INTR~3_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_INTR~2_combout\ <= NOT \myVirtualToplevel|UART0|RX_INTR~2_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_INTR~1_combout\ <= NOT \myVirtualToplevel|UART0|RX_INTR~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA~4_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~4_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~30_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~30_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~29_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~29_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~28_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~28_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(8) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(7) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(6) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(5) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~27_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~27_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(4) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(4);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(3) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(3);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(2) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(2);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(1) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(1);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(0) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(0);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(10) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(10);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(9) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(9);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~26_combout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~26_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(14) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(14);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(13) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(13);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(12) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(12);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(11) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(11);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(16) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(16);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(15) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(15);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~17_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~17_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~22_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~22_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(21) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(21);
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(5) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(5);
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\ <= NOT \myVirtualToplevel|UART0|RX_INTR~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~q\ <= NOT \myVirtualToplevel|UART0|RX_CLOCK~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\ <= NOT \myVirtualToplevel|UART0|RX_STATE.stop~q\;
-\myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\ <= NOT \myVirtualToplevel|UART0|RXD_SYNC~q\;
-\myVirtualToplevel|UART0|ALT_INV_Equal2~4_combout\ <= NOT \myVirtualToplevel|UART0|Equal2~4_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal2~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal2~3_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2);
-\myVirtualToplevel|UART0|ALT_INV_Equal2~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal2~2_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6);
-\myVirtualToplevel|UART0|ALT_INV_Equal2~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal2~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3);
-\myVirtualToplevel|UART0|ALT_INV_Equal2~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal2~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0);
-\myVirtualToplevel|UART1|ALT_INV_RX_INTR~4_combout\ <= NOT \myVirtualToplevel|UART1|RX_INTR~4_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_INTR~3_combout\ <= NOT \myVirtualToplevel|UART1|RX_INTR~3_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_INTR~2_combout\ <= NOT \myVirtualToplevel|UART1|RX_INTR~2_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_INTR~1_combout\ <= NOT \myVirtualToplevel|UART1|RX_INTR~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA~4_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~4_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~30_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~30_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~29_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~29_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~28_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~28_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(8) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(8);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(7) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(7);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(6) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(6);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(5) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(5);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~27_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~27_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(4) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(3) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(2) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(1) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(0) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(10) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(10);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(9) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(9);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~26_combout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~26_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(14) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(14);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(13) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(13);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(12) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(12);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(11) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(11);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(16) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(16);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(15) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(15);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~17_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~17_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~22_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~22_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(21) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(21);
-\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(5) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(5);
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\ <= NOT \myVirtualToplevel|UART1|RX_INTR~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\ <= NOT \myVirtualToplevel|UART1|RX_CLOCK~q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\ <= NOT \myVirtualToplevel|UART1|RX_STATE.stop~q\;
-\myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\ <= NOT \myVirtualToplevel|UART1|RXD_SYNC~q\;
-\myVirtualToplevel|UART1|ALT_INV_Equal2~4_combout\ <= NOT \myVirtualToplevel|UART1|Equal2~4_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal2~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal2~3_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(5) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5);
-\myVirtualToplevel|UART1|ALT_INV_Equal2~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal2~2_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2);
-\myVirtualToplevel|UART1|ALT_INV_Equal2~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal2~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3);
-\myVirtualToplevel|UART1|ALT_INV_Equal2~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal2~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(0);
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4) <= NOT \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4);
-\myVirtualToplevel|UART1|ALT_INV_Add9~24_combout\ <= NOT \myVirtualToplevel|UART1|Add9~24_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4) <= NOT \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4) <= NOT \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4);
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4) <= NOT \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4);
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(4) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector354~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector354~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1343~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1343~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux167~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux167~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1001~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1001~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux174~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux174~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~50_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[31]~50_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~49_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[31]~49_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[31]~48_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[31]~48_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(31) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(31);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(31) <= NOT \myVirtualToplevel|IO_DATA_READ\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1332~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1332~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~50_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux163~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux163~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~39_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~47_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[30]~47_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~46_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[30]~46_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~45_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[30]~45_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(30) <= NOT \myVirtualToplevel|IO_DATA_READ\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1333~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1333~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector991~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector991~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux164~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux164~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~36_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~44_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~43_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[29]~43_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[29]~42_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[29]~42_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(29) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(29);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(29) <= NOT \myVirtualToplevel|IO_DATA_READ\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1334~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1334~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector992~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector992~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux165~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux165~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[15]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[15]~1_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~41_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[28]~41_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~40_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[28]~40_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[28]~39_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[28]~39_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(28) <= NOT \myVirtualToplevel|IO_DATA_READ\(28);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0) <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1335~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1335~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux166~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux166~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector15~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Add10~43_combout\ <= NOT \myVirtualToplevel|UART1|Add10~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1328~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1328~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux152~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux152~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux180~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux180~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux159~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux159~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][5]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][5]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~27_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Add10~42_combout\ <= NOT \myVirtualToplevel|UART1|Add10~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1329~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1329~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux153~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux153~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector987~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector987~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux160~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux160~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~24_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Add10~41_combout\ <= NOT \myVirtualToplevel|UART1|Add10~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1330~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1330~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector988~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector988~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector11~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux19~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Add10~40_combout\ <= NOT \myVirtualToplevel|UART1|Add10~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector982~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector14~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Add10~39_combout\ <= NOT \myVirtualToplevel|UART1|Add10~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1327~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1327~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector985~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector985~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux151~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux151~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux158~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux158~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector12~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Add10~38_combout\ <= NOT \myVirtualToplevel|UART1|Add10~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1325~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1325~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux156~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux156~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector13~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector13~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Add10~37_combout\ <= NOT \myVirtualToplevel|UART1|Add10~37_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\ <= NOT \myVirtualToplevel|UART1|TX_STATE~q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_CLOCK~q\ <= NOT \myVirtualToplevel|UART1|TX_CLOCK~q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(8) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1326~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1326~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector984~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector984~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux157~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux157~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~9_combout\;
-\myVirtualToplevel|ALT_INV_Equal34~4_combout\ <= NOT \myVirtualToplevel|Equal34~4_combout\;
-\myVirtualToplevel|ALT_INV_Equal34~3_combout\ <= NOT \myVirtualToplevel|Equal34~3_combout\;
-\myVirtualToplevel|ALT_INV_Equal34~2_combout\ <= NOT \myVirtualToplevel|Equal34~2_combout\;
-\myVirtualToplevel|ALT_INV_Equal34~1_combout\ <= NOT \myVirtualToplevel|Equal34~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal34~0_combout\ <= NOT \myVirtualToplevel|Equal34~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~0_combout\ <= NOT \myVirtualToplevel|UART1|TX_OVERRUN~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_RESET~q\ <= NOT \myVirtualToplevel|UART1|TX_RESET~q\;
-\myVirtualToplevel|UART1|ALT_INV_Add10~32_combout\ <= NOT \myVirtualToplevel|UART1|Add10~32_combout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER~0_combout\ <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\;
-\myVirtualToplevel|ALT_INV_Equal33~3_combout\ <= NOT \myVirtualToplevel|Equal33~3_combout\;
-\myVirtualToplevel|ALT_INV_Equal33~2_combout\ <= NOT \myVirtualToplevel|Equal33~2_combout\;
-\myVirtualToplevel|ALT_INV_Equal33~1_combout\ <= NOT \myVirtualToplevel|Equal33~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal33~0_combout\ <= NOT \myVirtualToplevel|Equal33~0_combout\;
-\myVirtualToplevel|ALT_INV_Equal32~4_combout\ <= NOT \myVirtualToplevel|Equal32~4_combout\;
-\myVirtualToplevel|ALT_INV_Equal32~3_combout\ <= NOT \myVirtualToplevel|Equal32~3_combout\;
-\myVirtualToplevel|ALT_INV_Equal32~2_combout\ <= NOT \myVirtualToplevel|Equal32~2_combout\;
-\myVirtualToplevel|ALT_INV_Equal32~1_combout\ <= NOT \myVirtualToplevel|Equal32~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal32~0_combout\ <= NOT \myVirtualToplevel|Equal32~0_combout\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\;
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~0_combout\ <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\;
-\myVirtualToplevel|ALT_INV_Equal31~5_combout\ <= NOT \myVirtualToplevel|Equal31~5_combout\;
-\myVirtualToplevel|ALT_INV_Equal31~4_combout\ <= NOT \myVirtualToplevel|Equal31~4_combout\;
-\myVirtualToplevel|ALT_INV_Equal31~3_combout\ <= NOT \myVirtualToplevel|Equal31~3_combout\;
-\myVirtualToplevel|ALT_INV_Equal31~2_combout\ <= NOT \myVirtualToplevel|Equal31~2_combout\;
-\myVirtualToplevel|ALT_INV_Equal31~1_combout\ <= NOT \myVirtualToplevel|Equal31~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal31~0_combout\ <= NOT \myVirtualToplevel|Equal31~0_combout\;
-\myVirtualToplevel|ALT_INV_Equal30~1_combout\ <= NOT \myVirtualToplevel|Equal30~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal30~0_combout\ <= NOT \myVirtualToplevel|Equal30~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_MemoryFetch~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_MemoryFetch~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_0~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal154~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal154~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_0~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_0~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr128~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr128~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan3~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan3~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan2~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan2~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux155~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux155~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][6]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][6]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux162~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux162~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr162~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr162~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~8_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal0~4_combout\ <= NOT \myVirtualToplevel|UART1|Equal0~4_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal0~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal0~3_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal0~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal0~2_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal0~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal0~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal0~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_BUFFER\(9) <= NOT \myVirtualToplevel|UART1|TX_BUFFER\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~63_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~62_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~52_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy[31]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy[31]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~63_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~63_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~62_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~62_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~61_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~61_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~60_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~59_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~57_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~56_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~52_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~50_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~47_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan28~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan28~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1659~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1659~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr177~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr177~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr179~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr179~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~161_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~161_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~160_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc~160_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugLoad~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugLoad~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugOutputOnce~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugOutputOnce~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector362~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector362~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux254~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux254~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux255~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux255~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add59~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add61~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~60_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~59_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_pending\(17) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|pending\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_INT_DONE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|INT_DONE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal6~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal6~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pause\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pause\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddrPause~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddrPause~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_LatchAddr~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_LatchAddr~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector119~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector119~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector119~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux353~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux353~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux353~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector60~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector60~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux293~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux293~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux293~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux385~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux385~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux385~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux299~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux299~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux299~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux101~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux101~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux101~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux37~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux37~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux37~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux165~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux165~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux165~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux229~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux229~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux229~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux349~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux349~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux349~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector56~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector56~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux289~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux289~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux289~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux381~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux381~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux381~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux295~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux295~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux295~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux97~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux97~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux97~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux33~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux33~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux33~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux161~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux161~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux161~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux225~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux225~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux225~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[59]~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[59]~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector49~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector49~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector49~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux378~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux378~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux378~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux286~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux286~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux286~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux94~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux94~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux94~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux30~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux30~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux30~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector53~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector53~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux346~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux346~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux346~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[57]~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[57]~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector51~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector51~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector51~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux348~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux348~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux348~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector55~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector55~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux288~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux288~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux288~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux380~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux380~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux380~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux294~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DECODED_OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DECODED_OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DECODED_OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DECODED_OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux294~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux294~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DECODED_OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DECODED_OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DECODED_OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DECODED_OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux96~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux96~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux96~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux32~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux32~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux32~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux160~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux160~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux160~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux224~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux224~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux224~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[58]~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[58]~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector50~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DECODED_OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector50~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector50~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux379~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_NOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_NOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_NOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_NOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux379~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux379~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_NOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_NOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_NOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_NOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_NOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux287~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].OPCODE\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].OPCODE\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].OPCODE\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].OPCODE\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux287~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux287~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].OPCODE\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].OPCODE\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].OPCODE\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].OPCODE\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux95~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux95~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux95~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux31~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux31~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux31~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[54]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[54]~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.PC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_TOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_TOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.SP\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.SP\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.STACK_NOS\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.STACK_NOS\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector54~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector54~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA2\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA2\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA3\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC.DATA4\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC.DATA4\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux347~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].STACK_TOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].STACK_TOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].STACK_TOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].STACK_TOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux347~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux347~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].STACK_TOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].STACK_TOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].STACK_TOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].STACK_TOS\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].STACK_TOS\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~60_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~60_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~58_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~58_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE~57_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE~57_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux11~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux11~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux8~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux8~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux8~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux14~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector507~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector507~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector639~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector639~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector771~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector771~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector569~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector569~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector503~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector503~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector701~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector701~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector701~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector635~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector635~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector899~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector899~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector767~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector767~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector568~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector502~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector566~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector566~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1115~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1115~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1115~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1083~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1083~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1083~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector500~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector500~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector500~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1179~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1179~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1179~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector698~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector698~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector698~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1147~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1147~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1147~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector632~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector632~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector632~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1307~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1307~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1307~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector962~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector962~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector962~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1275~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1275~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1275~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector896~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector896~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector896~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READNOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READNOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector830~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector830~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector830~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector764~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector764~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector565~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector565~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector565~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector697~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector697~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector631~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector631~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector961~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector961~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector895~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector895~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector829~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector829~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~59_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~59_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector763~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector763~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[25]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[25]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(0);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]~25_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(2);
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][2]~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(2) <= NOT \myVirtualToplevel|UART0|RX_DATA\(2);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~76_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~76_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(2) <= NOT \myVirtualToplevel|UART1|RX_DATA\(2);
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\ <= NOT \myVirtualToplevel|UART0|RX_DATA_READY~q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~q\ <= NOT \myVirtualToplevel|UART1|RX_DATA_READY~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~75_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~75_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~74_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~74_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~73_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~73_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~72_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~72_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1145~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1145~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector596~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector596~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector662~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector662~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1177~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1177~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1113~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1113~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector530~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector530~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1081~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1081~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector926~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector926~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1305~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1305~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1273~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1273~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector860~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector860~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1241~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1241~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector794~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector794~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_addr~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|addr~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1209~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1209~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector728~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector728~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]~24_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(3);
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][3]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][3]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~70_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[0]~70_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(3) <= NOT \myVirtualToplevel|UART0|RX_DATA\(3);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~69_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~69_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_OVERRUN~q\ <= NOT \myVirtualToplevel|UART1|RX_OVERRUN~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_OVERRUN~q\ <= NOT \myVirtualToplevel|UART0|RX_OVERRUN~q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(3) <= NOT \myVirtualToplevel|UART1|RX_DATA\(3);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~68_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~68_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~67_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~67_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~66_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~66_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~65_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~65_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_MONTH_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[3]~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[3]~50_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[3]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[3]~52_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[3]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[3]~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[3]~56_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[3]~56_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~54_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~54_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[3]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[3]~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[3]~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[3]~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[3]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[3]~52_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1080~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1080~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector17~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector17~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux25~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux86~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[8]~23_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[8]~23_combout\;
-\myVirtualToplevel|ALT_INV_Mux75~0_combout\ <= NOT \myVirtualToplevel|Mux75~0_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][8]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][8]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[8]~64_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[8]~64_combout\;
-\myVirtualToplevel|ALT_INV_Mux264~0_combout\ <= NOT \myVirtualToplevel|Mux264~0_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(8) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(8);
-\myVirtualToplevel|ALT_INV_INT_ENABLE\(8) <= NOT \myVirtualToplevel|INT_ENABLE\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[8]~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[8]~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[8]~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[8]~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[8]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[8]~52_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[8]~55_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[8]~55_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[8]~53_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[8]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[8]~52_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[8]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[8]~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[8]~51_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[8]~51_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(8);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]~22_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(7);
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][7]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][7]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~62_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~62_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~61_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~61_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~60_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~60_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~59_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~59_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~58_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~58_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~57_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~57_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_RESET~q\ <= NOT \myVirtualToplevel|UART0|RX_RESET~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(7) <= NOT \myVirtualToplevel|UART0|RX_DATA\(7);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~56_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~56_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_RESET~q\ <= NOT \myVirtualToplevel|UART1|RX_RESET~q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(7) <= NOT \myVirtualToplevel|UART1|RX_DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[7]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[7]~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[7]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[7]~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[7]~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[7]~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[7]~52_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[7]~52_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[7]~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[7]~50_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[7]~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[7]~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[7]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[7]~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[7]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[7]~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1076~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1076~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(7);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]~21_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\;
-\myVirtualToplevel|ALT_INV_SD_OVERRUN~q\ <= NOT \myVirtualToplevel|SD_OVERRUN~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(6);
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][6]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][6]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~54_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~54_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~53_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~53_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~52_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~52_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~51_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~51_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~50_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~50_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~49_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[5]~49_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~48_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~48_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\ <= NOT \myVirtualToplevel|UART0|RX_ENABLE~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(6) <= NOT \myVirtualToplevel|UART0|RX_DATA\(6);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~47_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~47_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\ <= NOT \myVirtualToplevel|UART1|RX_ENABLE~q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(6) <= NOT \myVirtualToplevel|UART1|RX_DATA\(6);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[0]~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[6]~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[6]~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[6]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[6]~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[6]~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[6]~47_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[6]~50_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[6]~50_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[6]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[6]~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[6]~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[6]~47_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[6]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[6]~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[6]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[6]~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1077~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1077~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(6);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[11]~20_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[11]~20_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][11]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][11]~q\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(11) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(11);
-\myVirtualToplevel|ALT_INV_INT_ENABLE\(11) <= NOT \myVirtualToplevel|INT_ENABLE\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[11]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[11]~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[11]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[11]~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[11]~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[11]~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[11]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[11]~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[11]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[11]~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[11]~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[11]~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[11]~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[11]~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1072~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(11);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[10]~19_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[10]~19_combout\;
-\myVirtualToplevel|ALT_INV_Mux73~0_combout\ <= NOT \myVirtualToplevel|Mux73~0_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][10]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][10]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~43_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~43_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[11]~42_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[11]~42_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(10) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(10);
-\myVirtualToplevel|ALT_INV_INT_ENABLE\(10) <= NOT \myVirtualToplevel|INT_ENABLE\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[10]~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[10]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[10]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[10]~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[10]~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[10]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[10]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[10]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(10);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[9]~18_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[9]~18_combout\;
-\myVirtualToplevel|ALT_INV_Mux74~0_combout\ <= NOT \myVirtualToplevel|Mux74~0_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][9]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][9]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[9]~40_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[9]~40_combout\;
-\myVirtualToplevel|ALT_INV_Mux263~0_combout\ <= NOT \myVirtualToplevel|Mux263~0_combout\;
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(9) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(9);
-\myVirtualToplevel|ALT_INV_INT_ENABLE\(9) <= NOT \myVirtualToplevel|INT_ENABLE\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]~45_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(9);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]~17_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(5);
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][5]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][5]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~38_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[5]~38_combout\;
-\myVirtualToplevel|ALT_INV_Mux267~1_combout\ <= NOT \myVirtualToplevel|Mux267~1_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(5);
-\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(5);
-\myVirtualToplevel|ALT_INV_Mux267~0_combout\ <= NOT \myVirtualToplevel|Mux267~0_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~37_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~37_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~q\ <= NOT \myVirtualToplevel|UART0|RX_ENABLE_FIFO~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(5) <= NOT \myVirtualToplevel|UART0|RX_DATA\(5);
-\myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\ <= NOT \myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(5) <= NOT \myVirtualToplevel|UART1|RX_DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[5]~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[5]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[5]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[5]~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[5]~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[5]~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[5]~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[5]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(5);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[4]~16_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[4]~16_combout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM0_WREN~0_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(4);
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][4]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][4]~q\;
-\myVirtualToplevel|ALT_INV_Mux92~0_combout\ <= NOT \myVirtualToplevel|Mux92~0_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~35_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[4]~35_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~34_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[4]~34_combout\;
-\myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_DAY_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_HOUR_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_Mux268~1_combout\ <= NOT \myVirtualToplevel|Mux268~1_combout\;
-\myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_MINUTE_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_SECOND_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_Mux268~0_combout\ <= NOT \myVirtualToplevel|Mux268~0_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~33_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~33_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_INTR~q\ <= NOT \myVirtualToplevel|UART0|RX_INTR~q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA\(4) <= NOT \myVirtualToplevel|UART0|RX_DATA\(4);
-\myVirtualToplevel|UART1|ALT_INV_RX_INTR~q\ <= NOT \myVirtualToplevel|UART1|RX_INTR~q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA\(4) <= NOT \myVirtualToplevel|UART1|RX_DATA\(4);
-\myVirtualToplevel|INTRCTL:INTCONTROLLER|ALT_INV_status\(4) <= NOT \myVirtualToplevel|INTRCTL:INTCONTROLLER|status\(4);
-\myVirtualToplevel|ALT_INV_INT_ENABLE\(4) <= NOT \myVirtualToplevel|INT_ENABLE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[4]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[4]~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[4]~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[4]~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[4]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[4]~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[4]~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[4]~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[15]~15_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[15]~15_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][15]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][15]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~31_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[15]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[15]~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[15]~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[15]~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[15]~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[15]~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[15]~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[15]~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[15]~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[15]~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[15]~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[15]~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[15]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[15]~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1068~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1068~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(15);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[14]~14_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[14]~14_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][14]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][14]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[14]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[14]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[14]~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[14]~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[14]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[14]~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[14]~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(14);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[13]~13_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[13]~13_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][13]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~29_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~29_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~28_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[13]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[13]~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[13]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[13]~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[13]~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[13]~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[13]~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[13]~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[13]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[13]~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[13]~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[13]~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[13]~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[13]~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[13]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[13]~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1070~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(13);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[12]~12_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[12]~12_combout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM1_WREN~0_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_WREN~0_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][12]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][12]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[12]~26_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[12]~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[12]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[12]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[12]~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[12]~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[12]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[12]~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[12]~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[12]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(12);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[19]~11_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[19]~11_combout\;
-\myVirtualToplevel|ALT_INV_Mux86~0_combout\ <= NOT \myVirtualToplevel|Mux86~0_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][19]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][19]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~24_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~24_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~23_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~23_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_DATA_LOADED~q\ <= NOT \myVirtualToplevel|UART1|TX_DATA_LOADED~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[19]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[19]~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[19]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[19]~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[19]~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[19]~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[19]~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[19]~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[19]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[19]~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[19]~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[19]~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[19]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[19]~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[19]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[19]~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1064~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1064~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]~10_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][18]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][18]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~21_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~21_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~20_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~20_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_BUSY~q\ <= NOT \myVirtualToplevel|UART0|TX_BUSY~q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_BUSY~q\ <= NOT \myVirtualToplevel|UART1|TX_BUSY~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[18]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[18]~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[18]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[18]~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[18]~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[18]~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[18]~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[18]~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[18]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[18]~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[18]~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[18]~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[18]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[18]~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[18]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[18]~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1065~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1065~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18);
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][17]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][17]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~19_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~19_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal6~4_combout\ <= NOT \myVirtualToplevel|UART1|Equal6~4_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal6~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal6~3_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal6~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal6~2_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal6~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal6~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal6~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal6~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[17]~9_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[17]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[17]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[17]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[17]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[17]~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[17]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[17]~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[17]~26_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[17]~26_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[17]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[17]~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[17]~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[17]~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[17]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[17]~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[17]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[17]~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1066~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1066~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]~8_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][23]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][23]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~17_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~17_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\ <= NOT \myVirtualToplevel|UART1|TX_ENABLE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[23]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[23]~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[23]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[23]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[23]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[23]~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[23]~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[23]~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[23]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[23]~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[23]~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[23]~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[23]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[23]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1060~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1060~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[20]~7_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[20]~7_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][20]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][20]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~14_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~14_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~q\ <= NOT \myVirtualToplevel|UART0|TX_OVERRUN~q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~q\ <= NOT \myVirtualToplevel|UART1|TX_OVERRUN~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[20]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[20]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[20]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[20]~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[20]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[20]~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[20]~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[20]~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[20]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[20]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[20]~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[20]~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[20]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[20]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[20]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[20]~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1063~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1063~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(20);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]~6_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][22]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][22]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~11_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~11_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_ENABLE_FIFO~q\ <= NOT \myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[22]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[22]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[22]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[22]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[22]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[22]~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[22]~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[22]~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[22]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[22]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[22]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[22]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1061~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1061~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]~5_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\;
-\myVirtualToplevel|ALT_INV_SD_ADDR[0][21]~q\ <= NOT \myVirtualToplevel|SD_ADDR[0][21]~q\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~7_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~7_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~6_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[21]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[21]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[21]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[21]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[21]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[21]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[21]~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[21]~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[21]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[21]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[21]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[21]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[21]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[21]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[21]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[21]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1062~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1062~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[16]~4_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[16]~4_combout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\;
-\myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\ <= NOT \myVirtualToplevel|BRAM_WREN~1_combout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM2_WREN~0_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\;
-\myVirtualToplevel|ALT_INV_LessThan3~0_combout\ <= NOT \myVirtualToplevel|LessThan3~0_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~0_combout\ <= NOT \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~3_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]~3_combout\;
-\myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\ <= NOT \myVirtualToplevel|TIMER0_CS~2_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~2_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]~2_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~1_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]~1_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ[17]~0_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ[17]~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal5~4_combout\ <= NOT \myVirtualToplevel|UART1|Equal5~4_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Equal5~3_combout\ <= NOT \myVirtualToplevel|UART1|Equal5~3_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(4) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(4) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2);
-\myVirtualToplevel|UART1|ALT_INV_Equal5~2_combout\ <= NOT \myVirtualToplevel|UART1|Equal5~2_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(5) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(5) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(3) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(3) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3);
-\myVirtualToplevel|UART1|ALT_INV_Equal5~1_combout\ <= NOT \myVirtualToplevel|UART1|Equal5~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(7) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(7) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(6) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(6) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6);
-\myVirtualToplevel|UART1|ALT_INV_Equal5~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal5~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0);
-\myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal153~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal153~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal149~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal149~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal148~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal148~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugAllInfo~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugAllInfo~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan26~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan26~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_End~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_End~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_StartAddr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[16]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[16]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[16]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[16]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[16]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[16]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[16]~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[16]~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[16]~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[16]~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[16]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[16]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[16]~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[16]~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1067~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1067~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(1);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(0);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~14_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~14_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(9) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(9);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(8) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(8);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(7);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(7);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(6);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(6);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(5);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(5);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(4);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(4);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(3);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(3);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(2);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(2);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuCol\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuCol\(1);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(1);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~3_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(4);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(2);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(7);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(2);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(0);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(1);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\;
-\myVirtualToplevel|ALT_INV_SD_WR\(0) <= NOT \myVirtualToplevel|SD_WR\(0);
-\myVirtualToplevel|ALT_INV_SD_RD\(0) <= NOT \myVirtualToplevel|SD_RD\(0);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\;
-\myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0) <= NOT \myVirtualToplevel|SD_HNDSHK_IN\(0);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(4);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(2);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(0);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(6);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(5);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(3);
-\myVirtualToplevel|ALT_INV_SD_RESET\(0) <= NOT \myVirtualToplevel|SD_RESET\(0);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(47) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(47);
-\myVirtualToplevel|UART0|ALT_INV_TX_RESET~q\ <= NOT \myVirtualToplevel|UART0|TX_RESET~q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK~q\ <= NOT \myVirtualToplevel|UART0|TX_CLOCK~q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\ <= NOT \myVirtualToplevel|UART0|TX_STATE~q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\ <= NOT \myVirtualToplevel|UART0|TX_ENABLE~q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA_LOADED~q\ <= NOT \myVirtualToplevel|UART0|TX_DATA_LOADED~q\;
-\myVirtualToplevel|ALT_INV_RESET_n~q\ <= NOT \myVirtualToplevel|RESET_n~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_CLOCK~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_CLOCK~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_DATA_LOADED~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_DATA_LOADED~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQM\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM\(1);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQM\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQM\(0);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR\(10) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_cs_bo~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|cs_bo~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~q\;
-\myVirtualToplevel|UART0|ALT_INV_TXD~q\ <= NOT \myVirtualToplevel|UART0|TXD~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TXD~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TXD~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux28~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux28~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~48_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~48_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[13]~143_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[14]~139_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[15]~135_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[11]~115_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~65_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~65_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~9_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~116_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~116_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~108_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~108_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ~104_combout\ <= NOT \myVirtualToplevel|IO_DATA_READ~104_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~116_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~116_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[62]~112_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[62]~112_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~108_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~108_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~104_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~104_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr142~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr142~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr154~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr154~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr153~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr153~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr134~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr134~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr145~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr145~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr152~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr152~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector986~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector986~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector990~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector990~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1000~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1000~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector995~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector995~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector999~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector999~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~165_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~165_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector997~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector997~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~72_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|sp~72_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1002~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~15_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[44]~44_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[44]~44_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~161_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~161_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1389~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1389~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1394~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1394~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1464~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1464~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1463~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1463~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1416~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1416~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1417~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1417~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1538~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1538~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1482~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1482~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1542~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1542~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1486~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1486~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1540~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1540~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1484~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1484~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1424~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1424~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1488~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1488~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1421~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1421~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1425~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1425~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1423~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1423~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1490~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1490~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1428~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1428~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1492~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1492~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1432~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1432~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1427~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1427~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1504~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1504~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(8) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(8);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(10) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(10);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(12) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(12);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(14) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux299~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux299~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(22);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(37) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(10);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(39) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(50);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(7) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(7);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(7) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(7);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(0) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(0);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(14) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(14);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(15) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(15);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(1) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(1);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(2) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(2);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(5) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(5);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(9) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(9);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(3) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(3);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(4) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(4);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(6) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(6);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(8) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(8);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(10) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(10);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(11) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(11);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(12) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(12);
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(13) <= NOT \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a7\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a6~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.PC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.PC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA4~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA4~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.WRITE_DATA3~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.WRITE_DATA3~q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(6) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~735_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~735_sumout\;
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a1\;
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a2\;
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a3\;
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a4\;
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a5\;
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a6\;
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a7\;
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a1\;
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a2\;
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a3\;
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a4\;
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a5\;
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a6\;
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a7\;
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~731_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~731_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~727_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~727_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~723_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~723_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~719_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~719_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~715_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~715_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~711_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~711_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~61_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~61_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~57_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~57_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~49_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~49_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~45_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~45_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~41_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~41_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~37_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~37_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~33_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~33_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~29_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~29_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~25_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~25_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~21_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~21_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~17_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~17_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~13_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~13_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~9_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~9_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~5_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~5_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add1~1_sumout\ <= NOT \myVirtualToplevel|UART0|Add1~1_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~61_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~61_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~57_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~57_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~49_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~49_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~45_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~45_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~41_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~41_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~37_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~37_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~33_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~33_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~29_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~29_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~25_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~25_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~21_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~21_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~17_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~13_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~9_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~9_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~5_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add1~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add1~1_sumout\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][20]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][14]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][4]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][17]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][22]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][24]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][24]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][25]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][25]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][26]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][26]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][16]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][27]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][27]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][11]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][23]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][23]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][21]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][29]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][29]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][28]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][28]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][10]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][9]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][31]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~q\;
-\myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][30]~q\ <= NOT \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][30]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~707_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~707_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM195\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM195\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM197\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM197\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM199\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM199\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM201\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM201\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM203\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM203\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM205\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM205\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM207\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM207\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM209\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM209\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM211\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM211\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM213\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM213\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM215\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM215\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM217\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM217\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM219\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM219\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM221\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM221\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~125_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~125_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~121_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~121_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~117_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~117_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~113_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~113_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~109_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~109_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~105_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~105_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~101_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~101_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~97_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~97_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DECODED_OPCODE\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DECODED_OPCODE\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.OPCODE\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.OPCODE\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux3~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux5~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA2_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA3_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugRec.DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugRec.DATA4_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux21~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux20~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux23~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux22~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux29~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux28~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux26~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux27~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux25~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux24~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux4~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~4_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(5) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(5);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(1) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~93_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~136_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~136_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~125_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~125_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~125_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~125_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~121_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~121_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~132_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(0) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(0);
-\myVirtualToplevel|UART1|ALT_INV_Add9~36_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~36_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~117_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~117_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~128_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~128_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~117_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~117_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~113_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~113_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~124_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~124_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(24) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~120_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~109_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~109_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~105_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~105_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~105_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~116_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~116_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(27) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~65_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(26) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~61_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(25) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~101_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~101_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~101_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~112_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\;
-\myVirtualToplevel|ALT_INV_Add11~45_sumout\ <= NOT \myVirtualToplevel|Add11~45_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(14) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(14);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(13) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(13);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(0) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(0);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(12) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(12);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(11) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(11);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(6) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(6);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(5) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(5);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(4) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(4);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(3) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(3);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(2) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(2);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(1) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(1);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(10) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(10);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(9) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(9);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(8) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(8);
-\myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(7) <= NOT \myVirtualToplevel|UART0|RX_COUNTER\(7);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(14) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(14);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(13) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(13);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(0) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(0);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(12) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(12);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(11) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(11);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(6) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(6);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(5) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(5);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(4) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(4);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(3) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(3);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(2) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(2);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(1) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(1);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(10) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(10);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(9) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(9);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(8) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(8);
-\myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(7) <= NOT \myVirtualToplevel|UART1|RX_COUNTER\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~108_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~97_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~97_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(31) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~45_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(30) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~41_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(29) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~37_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(28) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~362_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~362_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~354_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~354_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~350_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~350_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~346_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~346_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(0) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(0);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(8) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(8);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(2) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(2);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(1) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(1);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(15) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(15);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(14) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(14);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(3) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(3);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(4) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(4);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(5) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(5);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(9) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(9);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(7) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(7);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(6) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(6);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(10) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(10);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(11) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(11);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(12) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(12);
-\myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(13) <= NOT \myVirtualToplevel|UART1|TX_COUNTER\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mult0~342_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~342_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(33) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(33);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(34) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(34);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(35) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(35);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(32) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(32);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(43) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(43);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(36) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(36);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(37) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(37);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(38) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(38);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(39) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(39);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(41) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(41);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(42) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(42);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(57) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(57);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(58) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(58);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(59) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(59);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divisorCopy\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divisorCopy\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add60~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add60~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM167\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM167\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[30]_OTERM169\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[30]_OTERM169\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM171\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM171\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[28]_OTERM173\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[28]_OTERM173\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM175\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM175\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[26]_OTERM177\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[26]_OTERM177\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM179\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM179\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[24]_OTERM181\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[24]_OTERM181\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM183\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM183\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[22]_OTERM185\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[22]_OTERM185\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM187\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM187\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[20]_OTERM189\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[20]_OTERM189\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM191\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM191\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[18]_OTERM193\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult[18]_OTERM193\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|multResult\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a5\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a4~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(40) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(40);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(44) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(44);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(47) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(47);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(51) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(51);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(45) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(45);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(49) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(49);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(46) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(46);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(50) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(50);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux3~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux3~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux5~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux5~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux21~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux21~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux20~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux20~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux23~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux23~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux22~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux22~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux29~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux29~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux28~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux28~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux26~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux26~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux27~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux27~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux25~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux25~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux24~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux24~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux4~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(0);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(4) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(25);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(1) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~103_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~103_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~93_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~93_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~98_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~98_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(30);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(0) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(0);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(0) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(0);
-\myVirtualToplevel|UART1|ALT_INV_Add9~31_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~31_sumout\;
-\myVirtualToplevel|ALT_INV_Add11~37_sumout\ <= NOT \myVirtualToplevel|Add11~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~94_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~85_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add2~29_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~29_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add2~25_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~25_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add2~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~17_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add2~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~13_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add2~9_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~9_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add2~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~5_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add2~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add2~1_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add2~29_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~29_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add2~25_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~25_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add2~17_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~17_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add2~13_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~13_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add2~9_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~9_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add2~5_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~5_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add2~1_sumout\ <= NOT \myVirtualToplevel|UART0|Add2~1_sumout\;
-\myVirtualToplevel|ALT_INV_Add11~33_sumout\ <= NOT \myVirtualToplevel|Add11~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~89_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(8);
-\myVirtualToplevel|ALT_INV_Add11~29_sumout\ <= NOT \myVirtualToplevel|Add11~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~77_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(24) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~77_sumout\;
-\myVirtualToplevel|ALT_INV_Add11~25_sumout\ <= NOT \myVirtualToplevel|Add11~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~80_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~80_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~73_sumout\;
-\myVirtualToplevel|ALT_INV_Add11~21_sumout\ <= NOT \myVirtualToplevel|Add11~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~75_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~75_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(11);
-\myVirtualToplevel|ALT_INV_Add11~17_sumout\ <= NOT \myVirtualToplevel|Add11~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~65_sumout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(27) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(27);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a3~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a11~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~71_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~71_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10);
-\myVirtualToplevel|ALT_INV_Add11~13_sumout\ <= NOT \myVirtualToplevel|Add11~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~61_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a2~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a10~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(26) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~66_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~66_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(9);
-\myVirtualToplevel|ALT_INV_Add11~9_sumout\ <= NOT \myVirtualToplevel|Add11~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~57_sumout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(25) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(25);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a1~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a9~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57_sumout\;
-\myVirtualToplevel|ALT_INV_Add11~5_sumout\ <= NOT \myVirtualToplevel|Add11~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~53_sumout\;
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_Add11~1_sumout\ <= NOT \myVirtualToplevel|Add11~1_sumout\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(6) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(6);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(5) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(5);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(2) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(2);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(0) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(0);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(7) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(7);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(4) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(4);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(3) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(3);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(1) <= NOT \myVirtualToplevel|RTC_MICROSEC_TICK\(1);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(1) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(0) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(6) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(6);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(7) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(7);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(25) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(25);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(27) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(27);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(0) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(0);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(1) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(1);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(2) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(2);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(3) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(3);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(4) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(4);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(5) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(5);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(8) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(8);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(9) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(9);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(22) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(22);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(23) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(23);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(24) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(24);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(26) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(26);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(12) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(12);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(13) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(13);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(14) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(14);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(15) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(15);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(16) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(16);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(18) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(18);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(20) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(20);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(21) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(21);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(10) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(10);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(11) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(11);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(17) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(17);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(19) <= NOT \myVirtualToplevel|SECOND_DOWN_TICK\(19);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(1) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(0) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(0);
-\myVirtualToplevel|UART0|ALT_INV_Add5~21_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~21_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add5~17_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~17_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add5~13_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~13_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add5~9_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~9_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add5~5_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~5_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add5~1_sumout\ <= NOT \myVirtualToplevel|UART0|Add5~1_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add5~21_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~21_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add5~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~17_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add5~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~13_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add5~9_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~9_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add5~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~5_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add5~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add5~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~52_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector245~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector245~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector241~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector241~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr123~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr123~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS_2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS_2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_NOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_NOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[63]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[63]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector114~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector114~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector121~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Selector121~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Selector121~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(56) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(56);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(60) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(60);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan3~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan3~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(63) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(63);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(61) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(61);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(62) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(62);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_POSTCRLF~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_POSTCRLF~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_PRECR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_PRECR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_FULL~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_FULL~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_WideOr18~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|WideOr18~combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_START~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_START~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_IDLE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_IDLE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_LessThan2~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|LessThan2~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEBIN~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEBIN~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_STATE.ST_WRITEHEX~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_STATE.ST_WRITEHEX~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector216~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux93~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux93~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~6_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~53_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~48_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~45_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector63~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\;
-\myVirtualToplevel|ALT_INV_SD_DATA_WRITE[7]~1_combout\ <= NOT \myVirtualToplevel|SD_DATA_WRITE[7]~1_combout\;
-\myVirtualToplevel|ALT_INV_SD_DATA_VALID~0_combout\ <= NOT \myVirtualToplevel|SD_DATA_VALID~0_combout\;
-\myVirtualToplevel|ALT_INV_Selector17~0_combout\ <= NOT \myVirtualToplevel|Selector17~0_combout\;
-\myVirtualToplevel|ALT_INV_Selector11~1_combout\ <= NOT \myVirtualToplevel|Selector11~1_combout\;
-\myVirtualToplevel|ALT_INV_Selector11~0_combout\ <= NOT \myVirtualToplevel|Selector11~0_combout\;
-\myVirtualToplevel|ALT_INV_Selector12~0_combout\ <= NOT \myVirtualToplevel|Selector12~0_combout\;
-\myVirtualToplevel|ALT_INV_Selector15~7_combout\ <= NOT \myVirtualToplevel|Selector15~7_combout\;
-\myVirtualToplevel|ALT_INV_Selector15~6_combout\ <= NOT \myVirtualToplevel|Selector15~6_combout\;
-\myVirtualToplevel|ALT_INV_Selector15~5_combout\ <= NOT \myVirtualToplevel|Selector15~5_combout\;
-\myVirtualToplevel|ALT_INV_Selector15~4_combout\ <= NOT \myVirtualToplevel|Selector15~4_combout\;
-\myVirtualToplevel|ALT_INV_Selector15~3_combout\ <= NOT \myVirtualToplevel|Selector15~3_combout\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\;
-\myVirtualToplevel|ALT_INV_Selector15~2_combout\ <= NOT \myVirtualToplevel|Selector15~2_combout\;
-\myVirtualToplevel|ALT_INV_Selector15~1_combout\ <= NOT \myVirtualToplevel|Selector15~1_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\ <= NOT \myVirtualToplevel|UART1|Mux0~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_ACMD41_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_CMD0_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~85_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[46]~6_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[46]~6_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(45) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(45);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~5_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~5_combout\;
-\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(6) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(6);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_BLK~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_BLK~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector16~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector16~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~4_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA[0]~4_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA~3_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~3_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~2_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA[0]~2_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~1_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA[0]~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~30_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~30_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~29_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~29_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~28_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~28_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(8) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(8);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(7) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(7);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(6) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(6);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(5) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(5);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~27_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~27_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(4) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(4);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(3) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(3);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(2) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(2);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(1) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(1);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(0) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(0);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(10) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(10);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(9) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(9);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~26_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~26_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(14) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(14);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(13) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(13);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(12) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(12);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(11) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(11);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(16) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(16);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(15) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(15);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~17_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~17_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~18_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~18_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(17) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(17);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(1) <= NOT \myVirtualToplevel|UART0|TX_DATA\(1);
-\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(5) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(5);
-\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(4) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(4);
-\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(0) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(0);
-\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(3) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(3);
-\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(2) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(2);
-\myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(10) <= NOT \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(10);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(9) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux88~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector18~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITETOINDADDR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITETOINDADDR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux9~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux9~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITETOINDADDR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITETOINDADDR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITETOINDADDR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READWORDTOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READWORDTOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READWORDTOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READWORDTOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux5~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux5~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READWORDTOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READWORDTOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READWORDTOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READTOSNOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOSNOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READTOSNOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READTOSNOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux3~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux3~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READTOSNOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READTOSNOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOSNOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOSNOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux2~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux2~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READNOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux1~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~0_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~37_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~36_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~35_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~34_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(2) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(2);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(2) <= NOT \myVirtualToplevel|IO_DATA_READ\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(2);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(3) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(3);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(3) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(3);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(3) <= NOT \myVirtualToplevel|IO_DATA_READ\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(3);
-\myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~1_combout\ <= NOT \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~0_combout\ <= NOT \myVirtualToplevel|UART0|TX_OVERRUN~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal6~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal6~2_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal6~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal6~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal6~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal6~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR[0]~0_combout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(8) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(8);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(8) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(8);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(8) <= NOT \myVirtualToplevel|IO_DATA_READ\(8);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(8) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~0_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(7) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(7);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(7) <= NOT \myVirtualToplevel|IO_DATA_READ\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(7);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(6) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(6);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(6) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(6);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(6) <= NOT \myVirtualToplevel|IO_DATA_READ\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(6);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(11) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(11);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(11) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(11);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(11) <= NOT \myVirtualToplevel|IO_DATA_READ\(11);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(11) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(11);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(10) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(10);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(10) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(10);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(10) <= NOT \myVirtualToplevel|IO_DATA_READ\(10);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(10) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(9) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(9);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(9) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(9);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(9) <= NOT \myVirtualToplevel|IO_DATA_READ\(9);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(9) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(5) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(5);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(5) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(5);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(5) <= NOT \myVirtualToplevel|IO_DATA_READ\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b\(0) <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(4) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(4);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(4) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(4);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(4) <= NOT \myVirtualToplevel|IO_DATA_READ\(4);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(4) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(15) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(15);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(15) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(15);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(15) <= NOT \myVirtualToplevel|IO_DATA_READ\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux34~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux34~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(15);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(14) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(14);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(14) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(14);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(14) <= NOT \myVirtualToplevel|IO_DATA_READ\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(13) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(13);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(13) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(13);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(13) <= NOT \myVirtualToplevel|IO_DATA_READ\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector203~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector203~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux36~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux36~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(13);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_address_reg_b\(0) <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|address_reg_b\(0);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(12) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(12);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(12) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(12);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(12) <= NOT \myVirtualToplevel|IO_DATA_READ\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~32_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[19]~32_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~31_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[19]~31_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(19) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(19);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(19) <= NOT \myVirtualToplevel|IO_DATA_READ\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux30~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux30~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(19);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~30_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~29_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[18]~29_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~28_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[18]~28_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(18) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(18);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(18) <= NOT \myVirtualToplevel|IO_DATA_READ\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector198~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector198~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux31~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux31~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(18);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~27_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[17]~27_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~26_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[17]~26_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~25_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[17]~25_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~24_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[17]~24_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~23_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[17]~23_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~22_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[27]~21_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[27]~21_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[30]~20_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[30]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector199~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector199~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux32~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux32~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(17);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~18_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~17_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[23]~17_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(23) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector193~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector193~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux0~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(23);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~16_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~15_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[20]~15_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~14_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[20]~14_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(20) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux29~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux29~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(20);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~13_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~12_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[22]~12_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~11_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[22]~11_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(22) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux27~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux27~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(22);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~9_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[21]~9_combout\;
-\myVirtualToplevel|ALT_INV_LessThan0~1_combout\ <= NOT \myVirtualToplevel|LessThan0~1_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~8_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[21]~8_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[18]~7_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(21) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(21);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(21) <= NOT \myVirtualToplevel|IO_DATA_READ\(21);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector195~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector195~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux28~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux28~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[14]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[14]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr116~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~3_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[16]~3_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[10]~1_combout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|ALT_INV_l1_w0_n0_mux_dataout~0_combout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|mux3|l1_w0_n0_mux_dataout~0_combout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0) <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0);
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~0_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[16]~0_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(16) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(16);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(16) <= NOT \myVirtualToplevel|IO_DATA_READ\(16);
-\myVirtualToplevel|ALT_INV_INTR0_CS~combout\ <= NOT \myVirtualToplevel|INTR0_CS~combout\;
-\myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\ <= NOT \myVirtualToplevel|INTR0_CS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector200~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector200~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux33~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux33~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr2~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux8~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux8~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~0_combout\;
-\myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\ <= NOT \myVirtualToplevel|MEM_BUSY~1_combout\;
-\myVirtualToplevel|ALT_INV_MEM_READ_ENABLE_LAST~q\ <= NOT \myVirtualToplevel|MEM_READ_ENABLE_LAST~q\;
-\myVirtualToplevel|ALT_INV_SD_CS~combout\ <= NOT \myVirtualToplevel|SD_CS~combout\;
-\myVirtualToplevel|ALT_INV_SD_CS~0_combout\ <= NOT \myVirtualToplevel|SD_CS~0_combout\;
-\myVirtualToplevel|ALT_INV_UART1_CS~combout\ <= NOT \myVirtualToplevel|UART1_CS~combout\;
-\myVirtualToplevel|ALT_INV_Equal4~0_combout\ <= NOT \myVirtualToplevel|Equal4~0_combout\;
-\myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\ <= NOT \myVirtualToplevel|TIMER0_CS~1_combout\;
-\myVirtualToplevel|ALT_INV_TIMER0_CS~0_combout\ <= NOT \myVirtualToplevel|TIMER0_CS~0_combout\;
-\myVirtualToplevel|ALT_INV_IO_SELECT~combout\ <= NOT \myVirtualToplevel|IO_SELECT~combout\;
-\myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\ <= NOT \myVirtualToplevel|SOCCFG_CS~combout\;
-\myVirtualToplevel|ALT_INV_SOCCFG_CS~0_combout\ <= NOT \myVirtualToplevel|SOCCFG_CS~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~18_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~18_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR[0]~20_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR[0]~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_WRITE_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_WRITE_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER[2]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER[2]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR[11]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR[11]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal12~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_LOAD~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_LOAD~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDoneLast~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDoneLast~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdDone~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdDone~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn[21]~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~0_q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~0_q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~14_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~14_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~12_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~10_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~10_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~9_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~9_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add3~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add3~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~0_combout\;
-\myVirtualToplevel|ALT_INV_LessThan0~0_combout\ <= NOT \myVirtualToplevel|LessThan0~0_combout\;
-\myVirtualToplevel|ALT_INV_BRAM_WREN~0_combout\ <= NOT \myVirtualToplevel|BRAM_WREN~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuLastEN~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuLastEN~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~7_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~7_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~6_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~6_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~5_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~5_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~3_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1_combout\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_READ~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~81_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~80_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~78_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~77_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~76_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD0~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~75_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal2~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD41~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~72_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD55~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~70_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WAIT_FOR_HOST_RW~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.GET_CMD8_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~67_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~66_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_WAIT~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_STD_MATCH~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o~3_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~64_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~63_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~62_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~59_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~58_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[4]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal4~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.RD_BLK~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o[3]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~54_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~52_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.START_INIT~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~51_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~48_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnData_v~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\;
-\myVirtualToplevel|ALT_INV_Selector15~0_combout\ <= NOT \myVirtualToplevel|Selector15~0_combout\;
-\myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\ <= NOT \myVirtualToplevel|SD_DATA_REQ~q\;
-\myVirtualToplevel|ALT_INV_Selector20~0_combout\ <= NOT \myVirtualToplevel|Selector20~0_combout\;
-\myVirtualToplevel|ALT_INV_SD_DATA_VALID~q\ <= NOT \myVirtualToplevel|SD_DATA_VALID~q\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~q\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(2);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector21~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\;
-\myVirtualToplevel|ALT_INV_Equal8~1_combout\ <= NOT \myVirtualToplevel|Equal8~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal8~0_combout\ <= NOT \myVirtualToplevel|Equal8~0_combout\;
-\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(1) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(1);
-\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(3) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(3);
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\;
-\myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~q\ <= NOT \myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\;
-\myVirtualToplevel|ALT_INV_SD_CHANNEL~q\ <= NOT \myVirtualToplevel|SD_CHANNEL~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~44_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~4_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~3_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector87~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector66~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector67~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~4_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector69~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~5_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~4_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~3_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~47_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~43_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~42_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_doDeselect_v~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~41_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~40_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~3_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~3_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(46) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(46);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_process_0~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|process_0~1_combout\;
-\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(7) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(7);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~2_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~2_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[47]~1_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[47]~1_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v[42]~0_combout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v[42]~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA[0]~0_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA[0]~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(0) <= NOT \myVirtualToplevel|UART0|TX_DATA\(0);
-\myVirtualToplevel|UART0|ALT_INV_Equal0~4_combout\ <= NOT \myVirtualToplevel|UART0|Equal0~4_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal0~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal0~3_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal0~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal0~2_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal0~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal0~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal0~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(8) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(8);
-\myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\ <= NOT \myVirtualToplevel|UART1|Equal7~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal5~3_combout\ <= NOT \myVirtualToplevel|UART0|Equal5~3_combout\;
-\myVirtualToplevel|UART0|ALT_INV_Equal5~2_combout\ <= NOT \myVirtualToplevel|UART0|Equal5~2_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(5) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(5);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(5) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(4) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(3) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3);
-\myVirtualToplevel|UART0|ALT_INV_Equal5~1_combout\ <= NOT \myVirtualToplevel|UART0|Equal5~1_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(2);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0);
-\myVirtualToplevel|UART0|ALT_INV_Equal5~0_combout\ <= NOT \myVirtualToplevel|UART0|Equal5~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(7) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6) <= NOT \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6);
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(6) <= NOT \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6);
-\myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\ <= NOT \myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\;
-\myVirtualToplevel|ALT_INV_UART0_CS~combout\ <= NOT \myVirtualToplevel|UART0_CS~combout\;
-\myVirtualToplevel|ALT_INV_Equal3~1_combout\ <= NOT \myVirtualToplevel|Equal3~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal3~0_combout\ <= NOT \myVirtualToplevel|Equal3~0_combout\;
-\myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\ <= NOT \myVirtualToplevel|IO_SELECT~2_combout\;
-\myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\ <= NOT \myVirtualToplevel|IO_SELECT~1_combout\;
-\myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\ <= NOT \myVirtualToplevel|IO_SELECT~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\;
-\ALT_INV_reset~combout\ <= NOT \reset~combout\;
-\myVirtualToplevel|ALT_INV_RESET_n~0_combout\ <= NOT \myVirtualToplevel|RESET_n~0_combout\;
-\myVirtualToplevel|ALT_INV_Equal12~3_combout\ <= NOT \myVirtualToplevel|Equal12~3_combout\;
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(8) <= NOT \myVirtualToplevel|RESET_COUNTER\(8);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(9) <= NOT \myVirtualToplevel|RESET_COUNTER\(9);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(12) <= NOT \myVirtualToplevel|RESET_COUNTER\(12);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(13) <= NOT \myVirtualToplevel|RESET_COUNTER\(13);
-\myVirtualToplevel|ALT_INV_Equal12~2_combout\ <= NOT \myVirtualToplevel|Equal12~2_combout\;
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(10) <= NOT \myVirtualToplevel|RESET_COUNTER\(10);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(11) <= NOT \myVirtualToplevel|RESET_COUNTER\(11);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(14) <= NOT \myVirtualToplevel|RESET_COUNTER\(14);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(15) <= NOT \myVirtualToplevel|RESET_COUNTER\(15);
-\myVirtualToplevel|ALT_INV_Equal12~1_combout\ <= NOT \myVirtualToplevel|Equal12~1_combout\;
-\myVirtualToplevel|ALT_INV_Equal12~0_combout\ <= NOT \myVirtualToplevel|Equal12~0_combout\;
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(0) <= NOT \myVirtualToplevel|RESET_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(1) <= NOT \myVirtualToplevel|RESET_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(2) <= NOT \myVirtualToplevel|RESET_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(3) <= NOT \myVirtualToplevel|RESET_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(4) <= NOT \myVirtualToplevel|RESET_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(5) <= NOT \myVirtualToplevel|RESET_COUNTER\(5);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(6) <= NOT \myVirtualToplevel|RESET_COUNTER\(6);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER\(7) <= NOT \myVirtualToplevel|RESET_COUNTER\(7);
-\myVirtualToplevel|ALT_INV_Equal11~4_combout\ <= NOT \myVirtualToplevel|Equal11~4_combout\;
-\myVirtualToplevel|ALT_INV_Equal11~3_combout\ <= NOT \myVirtualToplevel|Equal11~3_combout\;
-\myVirtualToplevel|ALT_INV_Equal11~2_combout\ <= NOT \myVirtualToplevel|Equal11~2_combout\;
-\myVirtualToplevel|ALT_INV_Equal11~1_combout\ <= NOT \myVirtualToplevel|Equal11~1_combout\;
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(10) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(10);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(12) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(12);
-\myVirtualToplevel|ALT_INV_Equal11~0_combout\ <= NOT \myVirtualToplevel|Equal11~0_combout\;
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(0) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(0);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(2) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(2);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(4) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(4);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(9) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal10~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal10~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_2~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_2~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal11~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal11~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_RD_ADDR\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_WR_ADDR\(0);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~11_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~11_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~9_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~9_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~8_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~8_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~7_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~7_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~6_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~6_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal2~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal2~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~5_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~5_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQ[0]~4_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~4_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~3_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~9_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~9_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~8_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~8_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCmd~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCmd~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~19_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~19_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(1);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(3);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(0);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDQM\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDQM\(2);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuIsWriting~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuIsWriting~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~16_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~16_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~7_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_ADDR~15_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR~15_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~5_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~5_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~4_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~4_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux8~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux8~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(10) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(10);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux9~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux9~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~3_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~3_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux11~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux11~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux12~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux12~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux7~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux7~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuRow\(11) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuRow\(11);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux10~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux10~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~1_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~1_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux13~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux13~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux14~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux14~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux15~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux15~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal6~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal6~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux16~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux16~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux17~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux17~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Mux18~0_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux18~0_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBank\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBank\(1);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~2_combout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~2_combout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveBank\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveBank\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector638~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector638~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector704~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector704~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~36_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector572~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector572~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~32_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector968~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector968~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~30_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector902~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector902~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector836~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector836~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector770~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector770~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector506~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector506~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[26]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[18]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~38_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr171~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tIdx~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|tIdx~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1352~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1243~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Equal0~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_WR_ADDR\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_intTriggered~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|intTriggered~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inInterrupt~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|inInterrupt~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][0]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][0]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][1]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][1]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][2]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][2]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][4]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][4]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][13]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][13]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][12]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][12]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][10]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][10]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][11]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][11]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][9]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][9]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][8]~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][8]~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4_combout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a7~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a15~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(31) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~47_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~47_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~41_sumout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(30) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(30);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a6~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a14~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divResult\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divResult\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~43_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~37_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a5~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a13~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(29) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~39_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~39_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add7~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add7~33_sumout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(28) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(28);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a4~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a12~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~35_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~30_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~26_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~22_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~22_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~18_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~18_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~14_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~10_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~6_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~5_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(0) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(0);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(1) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(1);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(2) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(2);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(3) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(3);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(7) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(7);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(9) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(9);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(10) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(10);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(11) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(11);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(12) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(12);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(13) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(13);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(14) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(14);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(17) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(17);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(6) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(6);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(8) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(8);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(15) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(15);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(16) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(16);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(4) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(4);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(5) <= NOT \myVirtualToplevel|MILLISEC_UP_TICK\(5);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(1) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(0) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(0) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(0);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(1) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(1);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(2) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(2);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(4) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(4);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(7) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(7);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(9) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(9);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(10) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(10);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(11) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(11);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(12) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(12);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(13) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(13);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(14) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(14);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(17) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(17);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(6) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(6);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(8) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(8);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(15) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(15);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(16) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(16);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(3) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(3);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(5) <= NOT \myVirtualToplevel|MILLISEC_DOWN_TICK\(5);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(1) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(0) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(0);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(2) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(2);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(3) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(3);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(4) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(4);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(7) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(7);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(0) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(0);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(1) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(1);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(5) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(5);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_TICK\(6) <= NOT \myVirtualToplevel|MICROSEC_DOWN_TICK\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_dividendCopy\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|dividendCopy\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add35~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add34~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add21~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add16~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~93_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~93_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~89_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a1\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a2\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a4\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a5\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a1\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a2\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a4\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a5\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a6\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a1\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a2\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a4\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a5\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a2\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a4\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a5\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a6\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\;
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~89_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~93_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~89_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~89_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add32~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add32~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux150~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux150~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux179~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux179~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add24~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add24~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add25~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add25~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add23~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add22~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(31) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(31);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(48) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(48);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(52) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(52);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(55) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(55);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(53) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(53);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN\(54) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN\(54);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add8~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add8~1_sumout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(2);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(3) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(0);
-\myVirtualToplevel|UART1|ALT_INV_Add9~21_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~21_sumout\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(2) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(2) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(2) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(2) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(2);
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(2) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~85_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add9~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~17_sumout\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(3) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(3) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(3) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(3) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3);
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(3) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(8) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(8);
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(8) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(8);
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(8) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(8);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(8) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(8);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(8) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(8);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(8) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(8);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(8) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(7) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(7);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(7) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(7);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(7) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(7);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(7) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(7);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(7) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(7) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(7);
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(7) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(7);
-\myVirtualToplevel|UART1|ALT_INV_Add9~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(6) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(6);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(6) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(6);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(6) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(6);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(6) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(6) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(6);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(6) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(6);
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(6) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(6);
-\myVirtualToplevel|UART1|ALT_INV_Add9~9_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(11) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(11);
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(11) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(11);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(11) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(11);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(11) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(11);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(11) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(10) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(10);
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(10) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(10);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(10) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(10);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(10) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(10) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(9);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(9) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(9);
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(9) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(9);
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(9) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(9);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(9) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(9);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(9) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(9);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(9) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(9);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(9) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\;
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(5);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(5);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(5) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(5);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(5) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(5);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(5) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(5) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(5);
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(5) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(5);
-\myVirtualToplevel|UART1|ALT_INV_Add9~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\;
-\myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_YEAR_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(4) <= NOT \myVirtualToplevel|RTC_MICROSEC_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(4) <= NOT \myVirtualToplevel|SECOND_DOWN_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(4) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(4) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(4) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4);
-\myVirtualToplevel|UART1|ALT_INV_Add9~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add9~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(15) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(15);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(15) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(15);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(15) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(14) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(14);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(14) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(14);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(14) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(13) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(13);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(13) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(13);
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(13) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(12) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(12) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(12);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(12) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(3);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(19) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(19);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(19) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19);
-\myVirtualToplevel|UART1|ALT_INV_Add10~29_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~29_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(2);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(18) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(18);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(18) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(18);
-\myVirtualToplevel|UART1|ALT_INV_Add10~25_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~25_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(1);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(17) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(17);
-\myVirtualToplevel|UART1|ALT_INV_Add6~29_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~29_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add6~25_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~25_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add6~21_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~21_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add6~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~17_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add6~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~13_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add6~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~5_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add6~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add6~1_sumout\;
-\myVirtualToplevel|UART1|ALT_INV_Add10~21_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~21_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(17) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(7);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(23) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(23);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(23) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(23);
-\myVirtualToplevel|UART1|ALT_INV_Add10~17_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~17_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(4);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(20) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(20);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(20) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(20);
-\myVirtualToplevel|UART1|ALT_INV_Add10~13_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~13_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(6);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(22) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(22);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(22) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(22);
-\myVirtualToplevel|UART1|ALT_INV_Add10~9_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~9_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(5);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(21) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(21);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(21) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(21);
-\myVirtualToplevel|UART1|ALT_INV_Add10~5_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~5_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_INTR~q\ <= NOT \myVirtualToplevel|UART0|TX_INTR~q\;
-\myVirtualToplevel|UART1|ALT_INV_TX_INTR~q\ <= NOT \myVirtualToplevel|UART1|TX_INTR~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~5_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(0);
-\myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(16) <= NOT \myVirtualToplevel|MILLISEC_UP_COUNTER\(16);
-\myVirtualToplevel|UART1|ALT_INV_Add10~1_sumout\ <= NOT \myVirtualToplevel|UART1|Add10~1_sumout\;
-\myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(16) <= NOT \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(16);
-\myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(16) <= NOT \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add56~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add27~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~93_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~89_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add2~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add2~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a3\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a2~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add14~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add14~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(24) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(24);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(27) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(27);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(28) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(28);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(25) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(25);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(26) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(26);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BYTECNT\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BYTECNT\(30);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(11) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(11);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(27) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(27);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(10) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(10);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(26) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(26);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(9) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(9);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(25) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(25);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(8) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(8);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(24) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(24);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(7);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(23) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(23);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(6);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(22) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(22);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(5);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(21) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(21);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(4);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(20) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(20);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(3);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(19) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(19);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(2);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(18) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(18);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(1);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(17) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(17);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(0);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(16) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(16);
-\myVirtualToplevel|ALT_INV_Add0~21_sumout\ <= NOT \myVirtualToplevel|Add0~21_sumout\;
-\myVirtualToplevel|ALT_INV_Add0~17_sumout\ <= NOT \myVirtualToplevel|Add0~17_sumout\;
-\myVirtualToplevel|ALT_INV_Add0~13_sumout\ <= NOT \myVirtualToplevel|Add0~13_sumout\;
-\myVirtualToplevel|ALT_INV_Add0~9_sumout\ <= NOT \myVirtualToplevel|Add0~9_sumout\;
-\myVirtualToplevel|ALT_INV_Add0~5_sumout\ <= NOT \myVirtualToplevel|Add0~5_sumout\;
-\myVirtualToplevel|ALT_INV_Add0~1_sumout\ <= NOT \myVirtualToplevel|Add0~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(2);
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a1\;
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a2\;
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a3\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a3\;
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a4\;
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a5\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a5\;
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a6\;
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a7\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a7\;
-\myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(2) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(0);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(2) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a3~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a11~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(3) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~81_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add6~29_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~29_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add6~25_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~25_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add6~17_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~17_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add6~13_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~13_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add6~9_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~9_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add6~5_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~5_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_Add6~1_sumout\ <= NOT \myVirtualToplevel|UART0|Add6~1_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a8~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~77_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a7~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a15~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(7) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(7);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(7) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~73_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a6~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(6) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a3~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a11~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a2~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a10~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a1~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a9~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~57_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a5~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(5) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a4~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a7~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a15~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(15) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~45_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a6~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a14~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(14) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~41_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a5~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a13~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(13) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~37_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a4~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM1_rtl_0|auto_generated|ram_block1a12~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(12) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a3~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a11~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a11~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(19) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~29_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a2~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a10~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(18) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~25_sumout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(17) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(17);
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~21_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(23) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~17_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a4~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a4~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a12~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a12~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(20) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~13_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(22) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~9_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a5~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a5~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a13~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a13~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(21) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~5_sumout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\ <= NOT \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a8~portbdataout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(16) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(16);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(16) <= NOT \myVirtualToplevel|IO_DATA_READ_INTRCTL\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~85_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~81_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~81_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~77_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~77_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~73_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~73_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~69_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~69_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~65_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~61_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~57_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~53_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~49_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~29_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~29_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add6~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(8) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(8);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxHoldCycles\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|mxHoldCycles\(4);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(15) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(15);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(31) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(31);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(14) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(14);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(30) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(30);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(13) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(13);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(29) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(29);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(12) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(12);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuDataIn\(28) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn\(28);
-\myVirtualToplevel|ALT_INV_Add2~57_sumout\ <= NOT \myVirtualToplevel|Add2~57_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~53_sumout\ <= NOT \myVirtualToplevel|Add2~53_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~49_sumout\ <= NOT \myVirtualToplevel|Add2~49_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~45_sumout\ <= NOT \myVirtualToplevel|Add2~45_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~41_sumout\ <= NOT \myVirtualToplevel|Add2~41_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~37_sumout\ <= NOT \myVirtualToplevel|Add2~37_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~33_sumout\ <= NOT \myVirtualToplevel|Add2~33_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~29_sumout\ <= NOT \myVirtualToplevel|Add2~29_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~25_sumout\ <= NOT \myVirtualToplevel|Add2~25_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~21_sumout\ <= NOT \myVirtualToplevel|Add2~21_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~17_sumout\ <= NOT \myVirtualToplevel|Add2~17_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~13_sumout\ <= NOT \myVirtualToplevel|Add2~13_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~9_sumout\ <= NOT \myVirtualToplevel|Add2~9_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~5_sumout\ <= NOT \myVirtualToplevel|Add2~5_sumout\;
-\myVirtualToplevel|ALT_INV_Add2~1_sumout\ <= NOT \myVirtualToplevel|Add2~1_sumout\;
-\myVirtualToplevel|ALT_INV_Add1~21_sumout\ <= NOT \myVirtualToplevel|Add1~21_sumout\;
-\myVirtualToplevel|ALT_INV_Add1~17_sumout\ <= NOT \myVirtualToplevel|Add1~17_sumout\;
-\myVirtualToplevel|ALT_INV_Add1~9_sumout\ <= NOT \myVirtualToplevel|Add1~9_sumout\;
-\myVirtualToplevel|ALT_INV_Add1~5_sumout\ <= NOT \myVirtualToplevel|Add1~5_sumout\;
-\myVirtualToplevel|ALT_INV_Add1~1_sumout\ <= NOT \myVirtualToplevel|Add1~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add12~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add12~1_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~45_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~45_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~41_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~41_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~37_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~37_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~33_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~33_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~25_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~25_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~21_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~21_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~17_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~17_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~13_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~13_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~9_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~9_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~5_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~5_sumout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Add13~1_sumout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Add13~1_sumout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~25_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25_sumout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~21_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21_sumout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~17_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17_sumout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~13_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13_sumout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~9_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9_sumout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~5_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5_sumout\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~1_sumout\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~25_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~21_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~17_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(0);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~9_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~5_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~1_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\;
-\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(0) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(0);
-\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(5) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(5);
-\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(2) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(2);
-\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(4) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(4);
-\myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(6) <= NOT \myVirtualToplevel|SD_RESET_TIMER\(6);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~29_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~25_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~21_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~13_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~9_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~5_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~1_sumout\ <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(1) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(1);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(14) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(14);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(13) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(13);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(5) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(5);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(4) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(4);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(12) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(12);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(11) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(11);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(0) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(0);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(7) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(7);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(3) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(3);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(2) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(2);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(1) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(1);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(8) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(8);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(10) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(10);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(9) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(9);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(15) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(15);
-\myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(6) <= NOT \myVirtualToplevel|UART0|TX_COUNTER\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(6) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(19) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(19);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(18) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(18);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(17) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(17);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(20) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(20);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(22) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(22);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(21) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(21);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(7) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(7);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(6) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(6);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(5) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(5);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(3) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(3);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(14) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(14);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(13) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(13);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(11) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(11);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(8) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(8);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(1) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(1);
-\myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(15) <= NOT \myVirtualToplevel|RESET_COUNTER_RX\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a1\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a1\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(11) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(10) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(10);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(7) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(7);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(4) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(4);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(15) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(15);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(14) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(14);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(13) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(13);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(12) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(12);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(3) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_COUNTER\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_COUNTER\(0);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(10) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(10);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(11) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(11);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(9) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(9);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(7);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(8) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(8);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(2);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(3);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(4);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(5);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(6);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][10]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][10]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][10]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][10]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][10]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][10]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][10]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][10]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][9]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][9]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][9]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][9]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][9]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][9]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][9]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][9]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][7]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][7]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][7]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][7]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][7]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][7]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][7]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][7]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][6]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][6]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][6]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][6]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][6]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][6]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][6]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][6]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][11]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][11]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][11]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][11]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][11]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][11]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][11]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][11]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][8]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][8]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][8]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][8]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][8]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][8]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][8]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][8]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][5]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][5]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][5]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][5]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][5]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][5]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][5]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][5]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][4]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][4]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][4]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][4]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][4]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][4]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][4]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][4]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][3]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][3]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][3]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][3]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][3]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][3]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][3]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][3]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][2]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][2]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][2]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][2]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][2]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][2]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][2]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][2]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][1]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][1]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][1]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][1]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][1]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][1]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][1]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][1]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[3][0]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[3][0]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[2][0]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[2][0]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[1][0]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[1][0]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdActiveRow[0][0]~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdActiveRow[0][0]~q\;
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(6) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(5) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(2) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(7) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(7);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(4) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(4);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(0) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(0);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(1) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(1);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(3) <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(3);
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\ <= NOT \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(8) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(8);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(7) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(7);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(6) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(6);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(5) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(5);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(4) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(4);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(3) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(3);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(2) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0);
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(1) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(1);
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(0) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_BUFFER\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_BUFFER\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TX_STATE~q\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|TX_STATE~q\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux14~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux14~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux17~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux17~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux17~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\(2) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(2);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux12~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux12~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux12~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux9~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux9~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux9~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux15~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux15~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux15~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux18~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux18~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux18~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux13~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA2_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA2_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA2_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA2_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux13~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux13~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA2_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA2_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA2_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA2_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA2_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux10~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux10~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux10~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux16~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA3_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA3_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA3_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA3_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux16~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux16~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA3_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA3_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA3_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA3_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA3_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux19~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].DATA4_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].DATA4_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].DATA4_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].DATA4_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux19~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux19~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].DATA4_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].DATA4_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].DATA4_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].DATA4_BYTECNT\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].DATA4_BYTECNT\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_BITCNT[0]~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_BITCNT[0]~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux1~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_DATA_PRTMODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_DATA_PRTMODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_DATA_PRTMODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_DATA_PRTMODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_Mux1~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|Mux1~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_DATA_PRTMODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_DATA_PRTMODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_DATA_PRTMODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_DATA_PRTMODE\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_DATA_PRTMODE\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_SPLIT_DATA\(0) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[2].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[2].FMT_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[3].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[3].FMT_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[0].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[0].FMT_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[1].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[1].FMT_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBGREC~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBGREC~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[7].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[7].FMT_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[6].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[6].FMT_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[5].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[5].FMT_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO[4].FMT_SPLIT_DATA\(1) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO[4].FMT_SPLIT_DATA\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_ADD_SEPERATOR~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_ADD_SEPERATOR~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_DATA_IN[39]~27_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_DATA_IN[39]~27_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_SM_WORDCNT[2]~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|SM_WORDCNT[2]~0_combout\;
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_tx_v\(43) <= NOT \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|tx_v\(43);
-\myVirtualToplevel|ALT_INV_SD_DATA_WRITE\(4) <= NOT \myVirtualToplevel|SD_DATA_WRITE\(4);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA~8_combout\ <= NOT \myVirtualToplevel|UART0|TX_DATA~8_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO~20_q\ <= NOT \myVirtualToplevel|UART0|TX_FIFO~20_q\;
-\myVirtualToplevel|UART0|ALT_INV_TX_FIFO_rtl_0_bypass\(19) <= NOT \myVirtualToplevel|UART0|TX_FIFO_rtl_0_bypass\(19);
-\myVirtualToplevel|UART0|ALT_INV_TX_DATA\(3) <= NOT \myVirtualToplevel|UART0|TX_DATA\(3);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux15~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux15~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux16~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~0_combout\;
-\myVirtualToplevel|UART0|ALT_INV_TX_BUFFER\(11) <= NOT \myVirtualToplevel|UART0|TX_BUFFER\(11);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector357~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~0_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~64_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[1]~64_combout\;
-\myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~63_combout\ <= NOT \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(1) <= NOT \myVirtualToplevel|IO_DATA_READ_SD\(1);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(1) <= NOT \myVirtualToplevel|IO_DATA_READ\(1);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1346~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~87_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~87_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~106_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~106_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~86_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~86_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~85_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~85_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~49_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~49_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~48_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~48_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~84_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~84_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~83_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~83_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1004~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1004~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux177~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux177~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector358~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~101_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Add36~101_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1347~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~47_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~47_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~46_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~46_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~41_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~41_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~25_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~25_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~24_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~24_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~23_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~23_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~22_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~22_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~21_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~21_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~20_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~20_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~19_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~19_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~40_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~40_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~39_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~39_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~18_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~18_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~17_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~17_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~16_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~16_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~15_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~15_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan23~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan23~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan24~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|LessThan24~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal142~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Equal142~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(30) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(30);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux178~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Mux178~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1005~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1005~1_combout\;
-\myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(0) <= NOT \myVirtualToplevel|IO_DATA_READ_SOCCFG\(0);
-\myVirtualToplevel|ALT_INV_IO_DATA_READ\(0) <= NOT \myVirtualToplevel|IO_DATA_READ\(0);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr160~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|WideOr160~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~38_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~38_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA~14_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA~14_combout\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO~20_q\ <= NOT \myVirtualToplevel|UART0|RX_FIFO~20_q\;
-\myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(19) <= NOT \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(19);
-\myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(3) <= NOT \myVirtualToplevel|UART0|RX_BUFFER\(3);
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA~14_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA~14_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO~20_q\ <= NOT \myVirtualToplevel|UART1|RX_FIFO~20_q\;
-\myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(19) <= NOT \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(19);
-\myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(3) <= NOT \myVirtualToplevel|UART1|RX_BUFFER\(3);
-\myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~0_combout\ <= NOT \myVirtualToplevel|UART0|RX_DATA_READY~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~0_combout\ <= NOT \myVirtualToplevel|UART1|RX_DATA_READY~0_combout\;
-\myVirtualToplevel|UART1|ALT_INV_Add9~29_combout\ <= NOT \myVirtualToplevel|UART1|Add9~29_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector356~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector356~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~1_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~1_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1345~0_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1345~0_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~14_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~14_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~13_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~13_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~82_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~82_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~12_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~12_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~11_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~11_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word\(29) <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word\(29);
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~10_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~10_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~9_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~9_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~8_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~8_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~7_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~7_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~6_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~6_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~5_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~5_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~4_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~4_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~3_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~3_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1003~2_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|Selector1003~2_combout\;
-\myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~81_combout\ <= NOT \myVirtualToplevel|ZPUEVO:ZPU0|TOS~81_combout\;
-
--- Location: IOOBUF_X38_Y0_N36
-\UART_TX_1~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_TXD~q\,
- devoe => ww_devoe,
- o => ww_UART_TX_1);
-
--- Location: IOOBUF_X25_Y0_N36
-\SDRAM_CLK~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- devoe => ww_devoe,
- o => ww_SDRAM_CLK);
-
--- Location: IOOBUF_X36_Y0_N36
-\UART_TX_0~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|UART0|ALT_INV_TXD~q\,
- devoe => ww_devoe,
- o => ww_UART_TX_0);
-
--- Location: IOOBUF_X43_Y0_N36
-\SDCARD_MOSI[0]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~q\,
- devoe => ww_devoe,
- o => ww_SDCARD_MOSI(0));
-
--- Location: IOOBUF_X44_Y0_N36
-\SDCARD_CLK[0]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\,
- devoe => ww_devoe,
- o => ww_SDCARD_CLK(0));
-
--- Location: IOOBUF_X48_Y0_N59
-\SDCARD_CS[0]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_cs_bo~q\,
- devoe => ww_devoe,
- o => ww_SDCARD_CS(0));
-
--- Location: IOOBUF_X18_Y0_N19
-\SDRAM_ADDR[0]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(0),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(0));
-
--- Location: IOOBUF_X14_Y0_N36
-\SDRAM_ADDR[1]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(1),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(1));
-
--- Location: IOOBUF_X18_Y0_N2
-\SDRAM_ADDR[2]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(2),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(2));
-
--- Location: IOOBUF_X11_Y0_N2
-\SDRAM_ADDR[3]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(3),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(3));
-
--- Location: IOOBUF_X12_Y0_N53
-\SDRAM_ADDR[4]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(4),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(4));
-
--- Location: IOOBUF_X10_Y0_N93
-\SDRAM_ADDR[5]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(5),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(5));
-
--- Location: IOOBUF_X12_Y0_N36
-\SDRAM_ADDR[6]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(6),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(6));
-
--- Location: IOOBUF_X10_Y0_N76
-\SDRAM_ADDR[7]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(7),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(7));
-
--- Location: IOOBUF_X12_Y0_N2
-\SDRAM_ADDR[8]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(8),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(8));
-
--- Location: IOOBUF_X11_Y0_N53
-\SDRAM_ADDR[9]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(9),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(9));
-
--- Location: IOOBUF_X10_Y0_N59
-\SDRAM_ADDR[10]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(10),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(10));
-
--- Location: IOOBUF_X19_Y0_N19
-\SDRAM_ADDR[11]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_ADDR\(11),
- devoe => ww_devoe,
- o => ww_SDRAM_ADDR(11));
-
--- Location: IOOBUF_X18_Y0_N36
-\SDRAM_DQM[0]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQM\(0),
- devoe => ww_devoe,
- o => ww_SDRAM_DQM(0));
-
--- Location: IOOBUF_X16_Y0_N42
-\SDRAM_DQM[1]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_SDRAM_DQM\(1),
- devoe => ww_devoe,
- o => ww_SDRAM_DQM(1));
-
--- Location: IOOBUF_X12_Y0_N19
-\SDRAM_BA[0]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA\(0),
- devoe => ww_devoe,
- o => ww_SDRAM_BA(0));
-
--- Location: IOOBUF_X29_Y0_N19
-\SDRAM_BA[1]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_BA\(1),
- devoe => ww_devoe,
- o => ww_SDRAM_BA(1));
-
--- Location: IOOBUF_X11_Y0_N36
-\SDRAM_WE~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_WE_n~q\,
- devoe => ww_devoe,
- o => ww_SDRAM_WE);
-
--- Location: IOOBUF_X16_Y0_N93
-\SDRAM_RAS~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_RAS_n~q\,
- devoe => ww_devoe,
- o => ww_SDRAM_RAS);
-
--- Location: IOOBUF_X18_Y0_N53
-\SDRAM_CAS~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_CAS_n~q\,
- devoe => ww_devoe,
- o => ww_SDRAM_CAS);
-
--- Location: IOOBUF_X50_Y45_N2
-\LEDR~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => GND,
- devoe => ww_devoe,
- o => ww_LEDR);
-
--- Location: IOOBUF_X16_Y0_N59
-\SDRAM_CKE~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => VCC,
- devoe => ww_devoe,
- o => ww_SDRAM_CKE);
-
--- Location: IOOBUF_X16_Y0_N76
-\SDRAM_CS~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => GND,
- devoe => ww_devoe,
- o => ww_SDRAM_CS);
-
--- Location: IOOBUF_X25_Y0_N2
-\SDRAM_DQ[12]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[12]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(12));
-
--- Location: IOOBUF_X24_Y0_N2
-\SDRAM_DQ[13]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[13]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(13));
-
--- Location: IOOBUF_X24_Y0_N53
-\SDRAM_DQ[14]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[14]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(14));
-
--- Location: IOOBUF_X24_Y0_N36
-\SDRAM_DQ[15]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[15]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(15));
-
--- Location: IOOBUF_X29_Y0_N36
-\SDRAM_DQ[0]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[0]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(0));
-
--- Location: IOOBUF_X29_Y0_N53
-\SDRAM_DQ[1]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[1]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(1));
-
--- Location: IOOBUF_X22_Y0_N53
-\SDRAM_DQ[2]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[2]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(2));
-
--- Location: IOOBUF_X25_Y0_N53
-\SDRAM_DQ[3]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[3]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(3));
-
--- Location: IOOBUF_X23_Y0_N93
-\SDRAM_DQ[4]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[4]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(4));
-
--- Location: IOOBUF_X22_Y0_N36
-\SDRAM_DQ[5]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[5]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(5));
-
--- Location: IOOBUF_X19_Y0_N36
-\SDRAM_DQ[6]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[6]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(6));
-
--- Location: IOOBUF_X19_Y0_N53
-\SDRAM_DQ[7]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[7]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(7));
-
--- Location: IOOBUF_X19_Y0_N2
-\SDRAM_DQ[8]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[8]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(8));
-
--- Location: IOOBUF_X23_Y0_N59
-\SDRAM_DQ[9]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[9]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(9));
-
--- Location: IOOBUF_X24_Y0_N19
-\SDRAM_DQ[10]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[10]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(10));
-
--- Location: IOOBUF_X25_Y0_N19
-\SDRAM_DQ[11]~output\ : cyclonev_io_obuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- open_drain_output => "false",
- shift_series_termination_control => "false")
--- pragma translate_on
-PORT MAP (
- i => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~reg0_q\,
- oe => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|SDRAM_DQ[11]~en_q\,
- devoe => ww_devoe,
- o => SDRAM_DQ(11));
-
--- Location: IOIBUF_X22_Y0_N1
-\CLOCK_50~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_CLOCK_50,
- o => \CLOCK_50~input_o\);
-
--- Location: PLLREFCLKSELECT_X0_Y7_N0
-\mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT\ : cyclonev_pll_refclk_select
--- pragma translate_off
-GENERIC MAP (
- pll_auto_clk_sw_en => "false",
- pll_clk_loss_edge => "both_edges",
- pll_clk_loss_sw_en => "false",
- pll_clk_sw_dly => 0,
- pll_clkin_0_src => "clk_0",
- pll_clkin_1_src => "ref_clk1",
- pll_manu_clk_sw_en => "false",
- pll_sw_refclk_src => "clk_0")
--- pragma translate_on
-PORT MAP (
- clkin => \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_CLKIN_bus\,
- clkout => \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_CLKOUT\,
- extswitchbuf => \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_EXTSWITCHBUF\);
-
--- Location: IOIBUF_X33_Y0_N92
-\KEY~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_KEY,
- o => \KEY~input_o\);
-
--- Location: FRACTIONALPLL_X0_Y1_N0
-\mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL\ : cyclonev_fractional_pll
--- pragma translate_off
-GENERIC MAP (
- dsm_accumulator_reset_value => 0,
- forcelock => "false",
- mimic_fbclk_type => "gclk_far",
- nreset_invert => "true",
- output_clock_frequency => "300.0 mhz",
- pll_atb => 0,
- pll_bwctrl => 4000,
- pll_cmp_buf_dly => "0 ps",
- pll_cp_comp => "true",
- pll_cp_current => 10,
- pll_ctrl_override_setting => "false",
- pll_dsm_dither => "disable",
- pll_dsm_out_sel => "disable",
- pll_dsm_reset => "false",
- pll_ecn_bypass => "false",
- pll_ecn_test_en => "false",
- pll_enable => "true",
- pll_fbclk_mux_1 => "glb",
- pll_fbclk_mux_2 => "fb_1",
- pll_fractional_carry_out => 32,
- pll_fractional_division => 1,
- pll_fractional_division_string => "'0'",
- pll_fractional_value_ready => "true",
- pll_lf_testen => "false",
- pll_lock_fltr_cfg => 25,
- pll_lock_fltr_test => "false",
- pll_m_cnt_bypass_en => "false",
- pll_m_cnt_coarse_dly => "0 ps",
- pll_m_cnt_fine_dly => "0 ps",
- pll_m_cnt_hi_div => 6,
- pll_m_cnt_in_src => "ph_mux_clk",
- pll_m_cnt_lo_div => 6,
- pll_m_cnt_odd_div_duty_en => "false",
- pll_m_cnt_ph_mux_prst => 0,
- pll_m_cnt_prst => 1,
- pll_n_cnt_bypass_en => "false",
- pll_n_cnt_coarse_dly => "0 ps",
- pll_n_cnt_fine_dly => "0 ps",
- pll_n_cnt_hi_div => 1,
- pll_n_cnt_lo_div => 1,
- pll_n_cnt_odd_div_duty_en => "false",
- pll_ref_buf_dly => "0 ps",
- pll_reg_boost => 0,
- pll_regulator_bypass => "false",
- pll_ripplecap_ctrl => 0,
- pll_slf_rst => "false",
- pll_tclk_mux_en => "false",
- pll_tclk_sel => "n_src",
- pll_test_enable => "false",
- pll_testdn_enable => "false",
- pll_testup_enable => "false",
- pll_unlock_fltr_cfg => 2,
- pll_vco_div => 2,
- pll_vco_ph0_en => "true",
- pll_vco_ph1_en => "true",
- pll_vco_ph2_en => "true",
- pll_vco_ph3_en => "true",
- pll_vco_ph4_en => "true",
- pll_vco_ph5_en => "true",
- pll_vco_ph6_en => "true",
- pll_vco_ph7_en => "true",
- pll_vctrl_test_voltage => 750,
- reference_clock_frequency => "50.0 mhz",
- vccd0g_atb => "disable",
- vccd0g_output => 0,
- vccd1g_atb => "disable",
- vccd1g_output => 0,
- vccm1g_tap => 2,
- vccr_pd => "false",
- vcodiv_override => "false",
- fractional_pll_index => 0)
--- pragma translate_on
-PORT MAP (
- coreclkfb => \mypll|altpll_component|auto_generated|fb_clkin\,
- ecnc1test => \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_EXTSWITCHBUF\,
- nresync => \ALT_INV_KEY~input_o\,
- refclkin => \mypll|altpll_component|auto_generated|generic_pll1~PLL_REFCLK_SELECT_O_CLKOUT\,
- shift => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\,
- shiftdonein => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\,
- shiften => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTENM\,
- up => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_UP\,
- cntnen => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_CNTNEN\,
- fbclk => \mypll|altpll_component|auto_generated|fb_clkin\,
- lock => \mypll|altpll_component|auto_generated|wire_generic_pll1_locked\,
- tclk => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_TCLK\,
- vcoph => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_VCOPH_bus\,
- mhi => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_MHI_bus\);
-
--- Location: PLLRECONFIG_X0_Y5_N0
-\mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG\ : cyclonev_pll_reconfig
--- pragma translate_off
-GENERIC MAP (
- fractional_pll_index => 0)
--- pragma translate_on
-PORT MAP (
- cntnen => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_CNTNEN\,
- mhi => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_MHI_bus\,
- shift => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\,
- shiftenm => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTENM\,
- up => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_UP\,
- shiften => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_SHIFTEN_bus\);
-
--- Location: PLLOUTPUTCOUNTER_X0_Y0_N1
-\mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER\ : cyclonev_pll_output_counter
--- pragma translate_off
-GENERIC MAP (
- c_cnt_coarse_dly => "0 ps",
- c_cnt_fine_dly => "0 ps",
- c_cnt_in_src => "ph_mux_clk",
- c_cnt_ph_mux_prst => 2,
- c_cnt_prst => 3,
- cnt_fpll_src => "fpll_0",
- dprio0_cnt_bypass_en => "false",
- dprio0_cnt_hi_div => 2,
- dprio0_cnt_lo_div => 1,
- dprio0_cnt_odd_div_even_duty_en => "true",
- duty_cycle => 50,
- output_clock_frequency => "100.0 mhz",
- phase_shift => "7500 ps",
- fractional_pll_index => 0,
- output_counter_index => 0)
--- pragma translate_on
-PORT MAP (
- nen0 => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_CNTNEN\,
- shift0 => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\,
- shiften => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFTEN0\,
- tclk0 => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_TCLK\,
- up0 => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_UP\,
- vco0ph => \mypll|altpll_component|auto_generated|generic_pll2~PLL_OUTPUT_COUNTER_VCO0PH_bus\,
- divclk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk\);
-
--- Location: CLKCTRL_G2
-\mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0\ : cyclonev_clkena
--- pragma translate_off
-GENERIC MAP (
- clock_type => "global clock",
- disable_mode => "low",
- ena_register_mode => "always enabled",
- ena_register_power_up => "high",
- test_syn => "high")
--- pragma translate_on
-PORT MAP (
- inclk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk\,
- outclk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\);
-
--- Location: PLLOUTPUTCOUNTER_X0_Y2_N1
-\mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER\ : cyclonev_pll_output_counter
--- pragma translate_off
-GENERIC MAP (
- c_cnt_coarse_dly => "0 ps",
- c_cnt_fine_dly => "0 ps",
- c_cnt_in_src => "ph_mux_clk",
- c_cnt_ph_mux_prst => 0,
- c_cnt_prst => 1,
- cnt_fpll_src => "fpll_0",
- dprio0_cnt_bypass_en => "false",
- dprio0_cnt_hi_div => 2,
- dprio0_cnt_lo_div => 1,
- dprio0_cnt_odd_div_even_duty_en => "true",
- duty_cycle => 50,
- output_clock_frequency => "100.0 mhz",
- phase_shift => "0 ps",
- fractional_pll_index => 0,
- output_counter_index => 2)
--- pragma translate_on
-PORT MAP (
- nen0 => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_CNTNEN\,
- shift0 => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_SHIFT\,
- shiften => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIGSHIFTEN2\,
- tclk0 => \mypll|altpll_component|auto_generated|generic_pll1~FRACTIONAL_PLL_O_TCLK\,
- up0 => \mypll|altpll_component|auto_generated|generic_pll1~PLL_RECONFIG_O_UP\,
- vco0ph => \mypll|altpll_component|auto_generated|generic_pll1~PLL_OUTPUT_COUNTER_VCO0PH_bus\,
- divclk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk\);
-
--- Location: CLKCTRL_G3
-\mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0\ : cyclonev_clkena
--- pragma translate_off
-GENERIC MAP (
- clock_type => "global clock",
- disable_mode => "low",
- ena_register_mode => "always enabled",
- ena_register_power_up => "high",
- test_syn => "high")
--- pragma translate_on
-PORT MAP (
- inclk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk\,
- outclk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\);
-
--- Location: IOIBUF_X36_Y0_N1
-\UART_RX_1~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_UART_RX_1,
- o => \UART_RX_1~input_o\);
-
--- Location: IOIBUF_X34_Y0_N52
-\UART_RX_0~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_UART_RX_0,
- o => \UART_RX_0~input_o\);
-
--- Location: LABCELL_X10_Y4_N45
-\myVirtualToplevel|RESET_COUNTER_RX~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER_RX~3_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|RESET_COUNTER_RX\(0) & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110111000000000111011100000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \ALT_INV_UART_RX_1~input_o\,
- datab => \ALT_INV_UART_RX_0~input_o\,
- datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(0),
- dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\,
- combout => \myVirtualToplevel|RESET_COUNTER_RX~3_combout\);
-
--- Location: MLABCELL_X13_Y4_N18
-reset : cyclonev_lcell_comb
--- Equation(s):
--- \reset~combout\ = ( \mypll|altpll_component|auto_generated|wire_generic_pll1_locked\ & ( !\KEY~input_o\ ) ) # ( !\mypll|altpll_component|auto_generated|wire_generic_pll1_locked\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \ALT_INV_KEY~input_o\,
- dataf => \mypll|altpll_component|auto_generated|ALT_INV_wire_generic_pll1_locked\,
- combout => \reset~combout\);
-
--- Location: FF_X10_Y4_N47
-\myVirtualToplevel|RESET_COUNTER_RX[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER_RX~3_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(0));
-
--- Location: MLABCELL_X9_Y4_N0
-\myVirtualToplevel|Add1~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~14\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(0),
- cin => GND,
- cout => \myVirtualToplevel|Add1~14\);
-
--- Location: MLABCELL_X9_Y4_N3
-\myVirtualToplevel|Add1~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~29_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add1~14\ ))
--- \myVirtualToplevel|Add1~30\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add1~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(1),
- cin => \myVirtualToplevel|Add1~14\,
- sumout => \myVirtualToplevel|Add1~29_sumout\,
- cout => \myVirtualToplevel|Add1~30\);
-
--- Location: MLABCELL_X9_Y4_N24
-\myVirtualToplevel|Add1~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~33_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add1~62\ ))
--- \myVirtualToplevel|Add1~34\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add1~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(8),
- cin => \myVirtualToplevel|Add1~62\,
- sumout => \myVirtualToplevel|Add1~33_sumout\,
- cout => \myVirtualToplevel|Add1~34\);
-
--- Location: MLABCELL_X9_Y4_N27
-\myVirtualToplevel|Add1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~1_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER_RX\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add1~34\ ))
--- \myVirtualToplevel|Add1~2\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add1~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(9),
- cin => \myVirtualToplevel|Add1~34\,
- sumout => \myVirtualToplevel|Add1~1_sumout\,
- cout => \myVirtualToplevel|Add1~2\);
-
--- Location: LABCELL_X10_Y4_N27
-\myVirtualToplevel|RESET_COUNTER_RX~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER_RX~0_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|Add1~1_sumout\ & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110111000000000111011100000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \ALT_INV_UART_RX_1~input_o\,
- datab => \ALT_INV_UART_RX_0~input_o\,
- datad => \myVirtualToplevel|ALT_INV_Add1~1_sumout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\,
- combout => \myVirtualToplevel|RESET_COUNTER_RX~0_combout\);
-
--- Location: FF_X10_Y4_N29
-\myVirtualToplevel|RESET_COUNTER_RX[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER_RX~0_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(9));
-
--- Location: MLABCELL_X9_Y4_N30
-\myVirtualToplevel|Add1~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~21_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER_RX\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add1~2\ ))
--- \myVirtualToplevel|Add1~22\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add1~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(10),
- cin => \myVirtualToplevel|Add1~2\,
- sumout => \myVirtualToplevel|Add1~21_sumout\,
- cout => \myVirtualToplevel|Add1~22\);
-
--- Location: LABCELL_X10_Y4_N21
-\myVirtualToplevel|RESET_COUNTER_RX~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER_RX~5_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|Add1~21_sumout\ & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110000011100000111000001110000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \ALT_INV_UART_RX_1~input_o\,
- datab => \ALT_INV_UART_RX_0~input_o\,
- datac => \myVirtualToplevel|ALT_INV_Add1~21_sumout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\,
- combout => \myVirtualToplevel|RESET_COUNTER_RX~5_combout\);
-
--- Location: FF_X10_Y4_N23
-\myVirtualToplevel|RESET_COUNTER_RX[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER_RX~5_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(10));
-
--- Location: MLABCELL_X9_Y4_N33
-\myVirtualToplevel|Add1~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~37_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add1~22\ ))
--- \myVirtualToplevel|Add1~38\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add1~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(11),
- cin => \myVirtualToplevel|Add1~22\,
- sumout => \myVirtualToplevel|Add1~37_sumout\,
- cout => \myVirtualToplevel|Add1~38\);
-
--- Location: FF_X9_Y4_N35
-\myVirtualToplevel|RESET_COUNTER_RX[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add1~37_sumout\,
- clrn => \ALT_INV_reset~combout\,
- sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(11));
-
--- Location: MLABCELL_X9_Y4_N36
-\myVirtualToplevel|Add1~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~17_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER_RX\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add1~38\ ))
--- \myVirtualToplevel|Add1~18\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add1~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(12),
- cin => \myVirtualToplevel|Add1~38\,
- sumout => \myVirtualToplevel|Add1~17_sumout\,
- cout => \myVirtualToplevel|Add1~18\);
-
--- Location: LABCELL_X10_Y4_N18
-\myVirtualToplevel|RESET_COUNTER_RX~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER_RX~4_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|Add1~17_sumout\ & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110000011100000111000001110000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \ALT_INV_UART_RX_1~input_o\,
- datab => \ALT_INV_UART_RX_0~input_o\,
- datac => \myVirtualToplevel|ALT_INV_Add1~17_sumout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\,
- combout => \myVirtualToplevel|RESET_COUNTER_RX~4_combout\);
-
--- Location: FF_X10_Y4_N20
-\myVirtualToplevel|RESET_COUNTER_RX[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER_RX~4_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(12));
-
--- Location: MLABCELL_X9_Y4_N39
-\myVirtualToplevel|Add1~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~41_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(13) ) + ( VCC ) + ( \myVirtualToplevel|Add1~18\ ))
--- \myVirtualToplevel|Add1~42\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(13) ) + ( VCC ) + ( \myVirtualToplevel|Add1~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(13),
- cin => \myVirtualToplevel|Add1~18\,
- sumout => \myVirtualToplevel|Add1~41_sumout\,
- cout => \myVirtualToplevel|Add1~42\);
-
--- Location: FF_X9_Y4_N41
-\myVirtualToplevel|RESET_COUNTER_RX[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add1~41_sumout\,
- clrn => \ALT_INV_reset~combout\,
- sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(13));
-
--- Location: MLABCELL_X9_Y4_N42
-\myVirtualToplevel|Add1~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~45_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(14) ) + ( VCC ) + ( \myVirtualToplevel|Add1~42\ ))
--- \myVirtualToplevel|Add1~46\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(14) ) + ( VCC ) + ( \myVirtualToplevel|Add1~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(14),
- cin => \myVirtualToplevel|Add1~42\,
- sumout => \myVirtualToplevel|Add1~45_sumout\,
- cout => \myVirtualToplevel|Add1~46\);
-
--- Location: FF_X9_Y4_N44
-\myVirtualToplevel|RESET_COUNTER_RX[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add1~45_sumout\,
- clrn => \ALT_INV_reset~combout\,
- sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(14));
-
--- Location: MLABCELL_X9_Y4_N45
-\myVirtualToplevel|Add1~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~25_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(15) ) + ( VCC ) + ( \myVirtualToplevel|Add1~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(15),
- cin => \myVirtualToplevel|Add1~46\,
- sumout => \myVirtualToplevel|Add1~25_sumout\);
-
--- Location: FF_X9_Y4_N47
-\myVirtualToplevel|RESET_COUNTER_RX[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add1~25_sumout\,
- clrn => \ALT_INV_reset~combout\,
- sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(15));
-
--- Location: MLABCELL_X9_Y4_N48
-\myVirtualToplevel|Equal11~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal11~1_combout\ = ( \myVirtualToplevel|RESET_COUNTER_RX\(12) & ( (\myVirtualToplevel|RESET_COUNTER_RX\(10) & (!\myVirtualToplevel|RESET_COUNTER_RX\(15) & !\myVirtualToplevel|RESET_COUNTER_RX\(1))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001000000010000000100000001000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(10),
- datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(15),
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(1),
- dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(12),
- combout => \myVirtualToplevel|Equal11~1_combout\);
-
--- Location: MLABCELL_X9_Y4_N54
-\myVirtualToplevel|Equal11~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal11~3_combout\ = ( !\myVirtualToplevel|RESET_COUNTER_RX\(3) & ( (!\myVirtualToplevel|RESET_COUNTER_RX\(5) & (!\myVirtualToplevel|RESET_COUNTER_RX\(6) & !\myVirtualToplevel|RESET_COUNTER_RX\(7))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(5),
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(6),
- datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(7),
- dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(3),
- combout => \myVirtualToplevel|Equal11~3_combout\);
-
--- Location: LABCELL_X10_Y4_N15
-\myVirtualToplevel|Equal11~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal11~0_combout\ = ( \myVirtualToplevel|RESET_COUNTER_RX\(2) & ( (\myVirtualToplevel|RESET_COUNTER_RX\(9) & (\myVirtualToplevel|RESET_COUNTER_RX\(0) & \myVirtualToplevel|RESET_COUNTER_RX\(4))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000001000000010000000100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(9),
- datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(0),
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(4),
- dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(2),
- combout => \myVirtualToplevel|Equal11~0_combout\);
-
--- Location: LABCELL_X10_Y4_N30
-\myVirtualToplevel|RESET_COUNTER_RX[0]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\ = ( \myVirtualToplevel|Equal11~2_combout\ & ( \myVirtualToplevel|Equal11~0_combout\ & ( (!\UART_RX_1~input_o\ & (\myVirtualToplevel|Equal11~1_combout\ & (\myVirtualToplevel|Equal11~3_combout\))) #
--- (\UART_RX_1~input_o\ & (((\myVirtualToplevel|Equal11~1_combout\ & \myVirtualToplevel|Equal11~3_combout\)) # (\UART_RX_0~input_o\))) ) ) ) # ( !\myVirtualToplevel|Equal11~2_combout\ & ( \myVirtualToplevel|Equal11~0_combout\ & ( (\UART_RX_1~input_o\ &
--- \UART_RX_0~input_o\) ) ) ) # ( \myVirtualToplevel|Equal11~2_combout\ & ( !\myVirtualToplevel|Equal11~0_combout\ & ( (\UART_RX_1~input_o\ & \UART_RX_0~input_o\) ) ) ) # ( !\myVirtualToplevel|Equal11~2_combout\ & ( !\myVirtualToplevel|Equal11~0_combout\ & (
--- (\UART_RX_1~input_o\ & \UART_RX_0~input_o\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010101000000000101010100000000010101010000001101010111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \ALT_INV_UART_RX_1~input_o\,
- datab => \myVirtualToplevel|ALT_INV_Equal11~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_Equal11~3_combout\,
- datad => \ALT_INV_UART_RX_0~input_o\,
- datae => \myVirtualToplevel|ALT_INV_Equal11~2_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal11~0_combout\,
- combout => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\);
-
--- Location: FF_X9_Y4_N5
-\myVirtualToplevel|RESET_COUNTER_RX[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add1~29_sumout\,
- clrn => \ALT_INV_reset~combout\,
- sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(1));
-
--- Location: MLABCELL_X9_Y4_N6
-\myVirtualToplevel|Add1~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~9_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER_RX\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add1~30\ ))
--- \myVirtualToplevel|Add1~10\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add1~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(2),
- cin => \myVirtualToplevel|Add1~30\,
- sumout => \myVirtualToplevel|Add1~9_sumout\,
- cout => \myVirtualToplevel|Add1~10\);
-
--- Location: LABCELL_X10_Y4_N24
-\myVirtualToplevel|RESET_COUNTER_RX~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER_RX~2_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|Add1~9_sumout\ & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110000011100000111000001110000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \ALT_INV_UART_RX_1~input_o\,
- datab => \ALT_INV_UART_RX_0~input_o\,
- datac => \myVirtualToplevel|ALT_INV_Add1~9_sumout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\,
- combout => \myVirtualToplevel|RESET_COUNTER_RX~2_combout\);
-
--- Location: FF_X10_Y4_N26
-\myVirtualToplevel|RESET_COUNTER_RX[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER_RX~2_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(2));
-
--- Location: MLABCELL_X9_Y4_N9
-\myVirtualToplevel|Add1~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~49_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add1~10\ ))
--- \myVirtualToplevel|Add1~50\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add1~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(3),
- cin => \myVirtualToplevel|Add1~10\,
- sumout => \myVirtualToplevel|Add1~49_sumout\,
- cout => \myVirtualToplevel|Add1~50\);
-
--- Location: FF_X9_Y4_N11
-\myVirtualToplevel|RESET_COUNTER_RX[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add1~49_sumout\,
- clrn => \ALT_INV_reset~combout\,
- sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(3));
-
--- Location: MLABCELL_X9_Y4_N12
-\myVirtualToplevel|Add1~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~5_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER_RX\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add1~50\ ))
--- \myVirtualToplevel|Add1~6\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER_RX\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add1~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(4),
- cin => \myVirtualToplevel|Add1~50\,
- sumout => \myVirtualToplevel|Add1~5_sumout\,
- cout => \myVirtualToplevel|Add1~6\);
-
--- Location: LABCELL_X10_Y4_N42
-\myVirtualToplevel|RESET_COUNTER_RX~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER_RX~1_combout\ = ( !\myVirtualToplevel|Equal11~4_combout\ & ( (!\myVirtualToplevel|Add1~5_sumout\ & ((!\UART_RX_1~input_o\) # (!\UART_RX_0~input_o\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110000011100000111000001110000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \ALT_INV_UART_RX_1~input_o\,
- datab => \ALT_INV_UART_RX_0~input_o\,
- datac => \myVirtualToplevel|ALT_INV_Add1~5_sumout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal11~4_combout\,
- combout => \myVirtualToplevel|RESET_COUNTER_RX~1_combout\);
-
--- Location: FF_X10_Y4_N44
-\myVirtualToplevel|RESET_COUNTER_RX[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER_RX~1_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(4));
-
--- Location: MLABCELL_X9_Y4_N15
-\myVirtualToplevel|Add1~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~53_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add1~6\ ))
--- \myVirtualToplevel|Add1~54\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add1~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(5),
- cin => \myVirtualToplevel|Add1~6\,
- sumout => \myVirtualToplevel|Add1~53_sumout\,
- cout => \myVirtualToplevel|Add1~54\);
-
--- Location: FF_X9_Y4_N17
-\myVirtualToplevel|RESET_COUNTER_RX[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add1~53_sumout\,
- clrn => \ALT_INV_reset~combout\,
- sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(5));
-
--- Location: MLABCELL_X9_Y4_N18
-\myVirtualToplevel|Add1~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~57_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add1~54\ ))
--- \myVirtualToplevel|Add1~58\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add1~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(6),
- cin => \myVirtualToplevel|Add1~54\,
- sumout => \myVirtualToplevel|Add1~57_sumout\,
- cout => \myVirtualToplevel|Add1~58\);
-
--- Location: FF_X9_Y4_N20
-\myVirtualToplevel|RESET_COUNTER_RX[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add1~57_sumout\,
- clrn => \ALT_INV_reset~combout\,
- sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(6));
-
--- Location: MLABCELL_X9_Y4_N21
-\myVirtualToplevel|Add1~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add1~61_sumout\ = SUM(( \myVirtualToplevel|RESET_COUNTER_RX\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add1~58\ ))
--- \myVirtualToplevel|Add1~62\ = CARRY(( \myVirtualToplevel|RESET_COUNTER_RX\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add1~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(7),
- cin => \myVirtualToplevel|Add1~58\,
- sumout => \myVirtualToplevel|Add1~61_sumout\,
- cout => \myVirtualToplevel|Add1~62\);
-
--- Location: FF_X9_Y4_N23
-\myVirtualToplevel|RESET_COUNTER_RX[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add1~61_sumout\,
- clrn => \ALT_INV_reset~combout\,
- sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(7));
-
--- Location: FF_X9_Y4_N26
-\myVirtualToplevel|RESET_COUNTER_RX[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add1~33_sumout\,
- clrn => \ALT_INV_reset~combout\,
- sclr => \myVirtualToplevel|RESET_COUNTER_RX[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER_RX\(8));
-
--- Location: MLABCELL_X9_Y4_N57
-\myVirtualToplevel|Equal11~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal11~2_combout\ = ( !\myVirtualToplevel|RESET_COUNTER_RX\(14) & ( (!\myVirtualToplevel|RESET_COUNTER_RX\(8) & (!\myVirtualToplevel|RESET_COUNTER_RX\(13) & !\myVirtualToplevel|RESET_COUNTER_RX\(11))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(8),
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(13),
- datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(11),
- dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER_RX\(14),
- combout => \myVirtualToplevel|Equal11~2_combout\);
-
--- Location: LABCELL_X10_Y4_N0
-\myVirtualToplevel|Equal11~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal11~4_combout\ = ( \myVirtualToplevel|Equal11~0_combout\ & ( (\myVirtualToplevel|Equal11~2_combout\ & (\myVirtualToplevel|Equal11~3_combout\ & \myVirtualToplevel|Equal11~1_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_Equal11~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_Equal11~3_combout\,
- datad => \myVirtualToplevel|ALT_INV_Equal11~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal11~0_combout\,
- combout => \myVirtualToplevel|Equal11~4_combout\);
-
--- Location: MLABCELL_X9_Y4_N51
-\myVirtualToplevel|RESET_COUNTER[0]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[0]~7_combout\ = !\myVirtualToplevel|RESET_COUNTER\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(0),
- combout => \myVirtualToplevel|RESET_COUNTER[0]~7_combout\);
-
--- Location: FF_X9_Y4_N52
-\myVirtualToplevel|RESET_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[0]~7_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(0));
-
--- Location: LABCELL_X12_Y4_N0
-\myVirtualToplevel|Add2~62\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~62_cout\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(0),
- cin => GND,
- cout => \myVirtualToplevel|Add2~62_cout\);
-
--- Location: LABCELL_X12_Y4_N3
-\myVirtualToplevel|Add2~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~25_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add2~62_cout\ ))
--- \myVirtualToplevel|Add2~26\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add2~62_cout\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(1),
- cin => \myVirtualToplevel|Add2~62_cout\,
- sumout => \myVirtualToplevel|Add2~25_sumout\,
- cout => \myVirtualToplevel|Add2~26\);
-
--- Location: LABCELL_X12_Y4_N51
-\myVirtualToplevel|RESET_COUNTER[1]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[1]~6_combout\ = !\myVirtualToplevel|Add2~25_sumout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Add2~25_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[1]~6_combout\);
-
--- Location: FF_X12_Y4_N53
-\myVirtualToplevel|RESET_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[1]~6_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(1));
-
--- Location: LABCELL_X12_Y4_N6
-\myVirtualToplevel|Add2~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~21_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add2~26\ ))
--- \myVirtualToplevel|Add2~22\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add2~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(2),
- cin => \myVirtualToplevel|Add2~26\,
- sumout => \myVirtualToplevel|Add2~21_sumout\,
- cout => \myVirtualToplevel|Add2~22\);
-
--- Location: LABCELL_X12_Y4_N54
-\myVirtualToplevel|RESET_COUNTER[2]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[2]~5_combout\ = ( !\myVirtualToplevel|Add2~21_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Add2~21_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[2]~5_combout\);
-
--- Location: FF_X12_Y4_N56
-\myVirtualToplevel|RESET_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[2]~5_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(2));
-
--- Location: LABCELL_X12_Y4_N9
-\myVirtualToplevel|Add2~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~17_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add2~22\ ))
--- \myVirtualToplevel|Add2~18\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add2~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(3),
- cin => \myVirtualToplevel|Add2~22\,
- sumout => \myVirtualToplevel|Add2~17_sumout\,
- cout => \myVirtualToplevel|Add2~18\);
-
--- Location: LABCELL_X12_Y4_N48
-\myVirtualToplevel|RESET_COUNTER[3]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[3]~4_combout\ = ( !\myVirtualToplevel|Add2~17_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Add2~17_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[3]~4_combout\);
-
--- Location: FF_X12_Y4_N50
-\myVirtualToplevel|RESET_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[3]~4_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(3));
-
--- Location: LABCELL_X12_Y4_N12
-\myVirtualToplevel|Add2~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~13_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add2~18\ ))
--- \myVirtualToplevel|Add2~14\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add2~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(4),
- cin => \myVirtualToplevel|Add2~18\,
- sumout => \myVirtualToplevel|Add2~13_sumout\,
- cout => \myVirtualToplevel|Add2~14\);
-
--- Location: MLABCELL_X13_Y4_N39
-\myVirtualToplevel|RESET_COUNTER[4]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[4]~3_combout\ = !\myVirtualToplevel|Add2~13_sumout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Add2~13_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[4]~3_combout\);
-
--- Location: FF_X13_Y4_N41
-\myVirtualToplevel|RESET_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[4]~3_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(4));
-
--- Location: LABCELL_X12_Y4_N15
-\myVirtualToplevel|Add2~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~9_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add2~14\ ))
--- \myVirtualToplevel|Add2~10\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add2~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(5),
- cin => \myVirtualToplevel|Add2~14\,
- sumout => \myVirtualToplevel|Add2~9_sumout\,
- cout => \myVirtualToplevel|Add2~10\);
-
--- Location: MLABCELL_X13_Y4_N36
-\myVirtualToplevel|RESET_COUNTER[5]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[5]~2_combout\ = ( !\myVirtualToplevel|Add2~9_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Add2~9_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[5]~2_combout\);
-
--- Location: FF_X13_Y4_N38
-\myVirtualToplevel|RESET_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[5]~2_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(5));
-
--- Location: LABCELL_X12_Y4_N18
-\myVirtualToplevel|Add2~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~5_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add2~10\ ))
--- \myVirtualToplevel|Add2~6\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add2~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(6),
- cin => \myVirtualToplevel|Add2~10\,
- sumout => \myVirtualToplevel|Add2~5_sumout\,
- cout => \myVirtualToplevel|Add2~6\);
-
--- Location: MLABCELL_X13_Y4_N6
-\myVirtualToplevel|RESET_COUNTER[6]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[6]~1_combout\ = ( !\myVirtualToplevel|Add2~5_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Add2~5_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[6]~1_combout\);
-
--- Location: FF_X13_Y4_N8
-\myVirtualToplevel|RESET_COUNTER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[6]~1_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(6));
-
--- Location: LABCELL_X12_Y4_N57
-\myVirtualToplevel|Equal12~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal12~0_combout\ = ( \myVirtualToplevel|RESET_COUNTER\(1) & ( (\myVirtualToplevel|RESET_COUNTER\(3) & (\myVirtualToplevel|RESET_COUNTER\(0) & \myVirtualToplevel|RESET_COUNTER\(2))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(3),
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(0),
- datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(2),
- dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(1),
- combout => \myVirtualToplevel|Equal12~0_combout\);
-
--- Location: LABCELL_X12_Y4_N21
-\myVirtualToplevel|Add2~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~1_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add2~6\ ))
--- \myVirtualToplevel|Add2~2\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add2~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(7),
- cin => \myVirtualToplevel|Add2~6\,
- sumout => \myVirtualToplevel|Add2~1_sumout\,
- cout => \myVirtualToplevel|Add2~2\);
-
--- Location: MLABCELL_X13_Y4_N12
-\myVirtualToplevel|RESET_COUNTER[7]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[7]~0_combout\ = !\myVirtualToplevel|Add2~1_sumout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_Add2~1_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[7]~0_combout\);
-
--- Location: FF_X13_Y4_N14
-\myVirtualToplevel|RESET_COUNTER[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[7]~0_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(7));
-
--- Location: MLABCELL_X13_Y4_N15
-\myVirtualToplevel|Equal12~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal12~1_combout\ = ( \myVirtualToplevel|RESET_COUNTER\(7) & ( (\myVirtualToplevel|RESET_COUNTER\(5) & (\myVirtualToplevel|RESET_COUNTER\(6) & (\myVirtualToplevel|RESET_COUNTER\(4) & \myVirtualToplevel|Equal12~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000010000000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(5),
- datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(6),
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(4),
- datad => \myVirtualToplevel|ALT_INV_Equal12~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(7),
- combout => \myVirtualToplevel|Equal12~1_combout\);
-
--- Location: LABCELL_X12_Y4_N24
-\myVirtualToplevel|Add2~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~57_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add2~2\ ))
--- \myVirtualToplevel|Add2~58\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add2~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(8),
- cin => \myVirtualToplevel|Add2~2\,
- sumout => \myVirtualToplevel|Add2~57_sumout\,
- cout => \myVirtualToplevel|Add2~58\);
-
--- Location: MLABCELL_X13_Y4_N33
-\myVirtualToplevel|RESET_COUNTER[8]~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[8]~15_combout\ = ( !\myVirtualToplevel|Add2~57_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Add2~57_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[8]~15_combout\);
-
--- Location: FF_X13_Y4_N35
-\myVirtualToplevel|RESET_COUNTER[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[8]~15_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(8));
-
--- Location: LABCELL_X12_Y4_N27
-\myVirtualToplevel|Add2~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~53_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add2~58\ ))
--- \myVirtualToplevel|Add2~54\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add2~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(9),
- cin => \myVirtualToplevel|Add2~58\,
- sumout => \myVirtualToplevel|Add2~53_sumout\,
- cout => \myVirtualToplevel|Add2~54\);
-
--- Location: MLABCELL_X13_Y4_N0
-\myVirtualToplevel|RESET_COUNTER[9]~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[9]~14_combout\ = !\myVirtualToplevel|Add2~53_sumout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_Add2~53_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[9]~14_combout\);
-
--- Location: FF_X13_Y4_N2
-\myVirtualToplevel|RESET_COUNTER[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[9]~14_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(9));
-
--- Location: LABCELL_X12_Y4_N30
-\myVirtualToplevel|Add2~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~41_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add2~54\ ))
--- \myVirtualToplevel|Add2~42\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add2~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(10),
- cin => \myVirtualToplevel|Add2~54\,
- sumout => \myVirtualToplevel|Add2~41_sumout\,
- cout => \myVirtualToplevel|Add2~42\);
-
--- Location: MLABCELL_X13_Y4_N54
-\myVirtualToplevel|RESET_COUNTER[10]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[10]~11_combout\ = ( !\myVirtualToplevel|Add2~41_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Add2~41_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[10]~11_combout\);
-
--- Location: FF_X13_Y4_N56
-\myVirtualToplevel|RESET_COUNTER[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[10]~11_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(10));
-
--- Location: LABCELL_X12_Y4_N33
-\myVirtualToplevel|Add2~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~37_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add2~42\ ))
--- \myVirtualToplevel|Add2~38\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add2~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(11),
- cin => \myVirtualToplevel|Add2~42\,
- sumout => \myVirtualToplevel|Add2~37_sumout\,
- cout => \myVirtualToplevel|Add2~38\);
-
--- Location: MLABCELL_X13_Y4_N45
-\myVirtualToplevel|RESET_COUNTER[11]~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[11]~10_combout\ = !\myVirtualToplevel|Add2~37_sumout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_Add2~37_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[11]~10_combout\);
-
--- Location: FF_X13_Y4_N46
-\myVirtualToplevel|RESET_COUNTER[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[11]~10_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(11));
-
--- Location: LABCELL_X12_Y4_N36
-\myVirtualToplevel|Add2~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~49_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add2~38\ ))
--- \myVirtualToplevel|Add2~50\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add2~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(12),
- cin => \myVirtualToplevel|Add2~38\,
- sumout => \myVirtualToplevel|Add2~49_sumout\,
- cout => \myVirtualToplevel|Add2~50\);
-
--- Location: MLABCELL_X13_Y4_N30
-\myVirtualToplevel|RESET_COUNTER[12]~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[12]~13_combout\ = ( !\myVirtualToplevel|Add2~49_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Add2~49_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[12]~13_combout\);
-
--- Location: FF_X13_Y4_N32
-\myVirtualToplevel|RESET_COUNTER[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[12]~13_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(12));
-
--- Location: LABCELL_X12_Y4_N39
-\myVirtualToplevel|Add2~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~45_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|Add2~50\ ))
--- \myVirtualToplevel|Add2~46\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|Add2~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(13),
- cin => \myVirtualToplevel|Add2~50\,
- sumout => \myVirtualToplevel|Add2~45_sumout\,
- cout => \myVirtualToplevel|Add2~46\);
-
--- Location: MLABCELL_X13_Y4_N48
-\myVirtualToplevel|RESET_COUNTER[13]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[13]~12_combout\ = ( !\myVirtualToplevel|Add2~45_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Add2~45_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[13]~12_combout\);
-
--- Location: FF_X13_Y4_N50
-\myVirtualToplevel|RESET_COUNTER[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[13]~12_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(13));
-
--- Location: MLABCELL_X13_Y4_N3
-\myVirtualToplevel|Equal12~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal12~3_combout\ = ( \myVirtualToplevel|RESET_COUNTER\(8) & ( (\myVirtualToplevel|RESET_COUNTER\(13) & (\myVirtualToplevel|RESET_COUNTER\(12) & \myVirtualToplevel|RESET_COUNTER\(9))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(13),
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(12),
- datad => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(9),
- dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(8),
- combout => \myVirtualToplevel|Equal12~3_combout\);
-
--- Location: LABCELL_X12_Y4_N42
-\myVirtualToplevel|Add2~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~33_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|Add2~46\ ))
--- \myVirtualToplevel|Add2~34\ = CARRY(( !\myVirtualToplevel|RESET_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|Add2~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(14),
- cin => \myVirtualToplevel|Add2~46\,
- sumout => \myVirtualToplevel|Add2~33_sumout\,
- cout => \myVirtualToplevel|Add2~34\);
-
--- Location: MLABCELL_X13_Y4_N27
-\myVirtualToplevel|RESET_COUNTER[14]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[14]~9_combout\ = !\myVirtualToplevel|Add2~33_sumout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_Add2~33_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[14]~9_combout\);
-
--- Location: FF_X13_Y4_N29
-\myVirtualToplevel|RESET_COUNTER[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[14]~9_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(14));
-
--- Location: LABCELL_X12_Y4_N45
-\myVirtualToplevel|Add2~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add2~29_sumout\ = SUM(( !\myVirtualToplevel|RESET_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|Add2~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(15),
- cin => \myVirtualToplevel|Add2~34\,
- sumout => \myVirtualToplevel|Add2~29_sumout\);
-
--- Location: MLABCELL_X13_Y4_N57
-\myVirtualToplevel|RESET_COUNTER[15]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_COUNTER[15]~8_combout\ = ( !\myVirtualToplevel|Add2~29_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Add2~29_sumout\,
- combout => \myVirtualToplevel|RESET_COUNTER[15]~8_combout\);
-
--- Location: FF_X13_Y4_N58
-\myVirtualToplevel|RESET_COUNTER[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_COUNTER[15]~8_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_COUNTER\(15));
-
--- Location: MLABCELL_X13_Y4_N42
-\myVirtualToplevel|Equal12~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal12~2_combout\ = ( \myVirtualToplevel|RESET_COUNTER\(15) & ( (\myVirtualToplevel|RESET_COUNTER\(10) & (\myVirtualToplevel|RESET_COUNTER\(11) & \myVirtualToplevel|RESET_COUNTER\(14))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000001000000010000000100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(10),
- datab => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(11),
- datac => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(14),
- dataf => \myVirtualToplevel|ALT_INV_RESET_COUNTER\(15),
- combout => \myVirtualToplevel|Equal12~2_combout\);
-
--- Location: MLABCELL_X13_Y4_N24
-\myVirtualToplevel|RESET_n~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_n~0_combout\ = ( \myVirtualToplevel|Equal12~2_combout\ & ( (!\myVirtualToplevel|Equal11~4_combout\ & (((\myVirtualToplevel|Equal12~1_combout\ & \myVirtualToplevel|Equal12~3_combout\)) # (\myVirtualToplevel|RESET_n~q\))) #
--- (\myVirtualToplevel|Equal11~4_combout\ & (\myVirtualToplevel|Equal12~1_combout\ & (\myVirtualToplevel|Equal12~3_combout\))) ) ) # ( !\myVirtualToplevel|Equal12~2_combout\ & ( (!\myVirtualToplevel|Equal11~4_combout\ & \myVirtualToplevel|RESET_n~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010101010000000001010101000000011101010110000001110101011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal11~4_combout\,
- datab => \myVirtualToplevel|ALT_INV_Equal12~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_Equal12~3_combout\,
- datad => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- dataf => \myVirtualToplevel|ALT_INV_Equal12~2_combout\,
- combout => \myVirtualToplevel|RESET_n~0_combout\);
-
--- Location: LABCELL_X25_Y14_N12
-\myVirtualToplevel|RESET_n~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RESET_n~feeder_combout\ = ( \myVirtualToplevel|RESET_n~0_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_RESET_n~0_combout\,
- combout => \myVirtualToplevel|RESET_n~feeder_combout\);
-
--- Location: FF_X25_Y14_N14
-\myVirtualToplevel|RESET_n\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RESET_n~feeder_combout\,
- clrn => \ALT_INV_reset~combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RESET_n~q\);
-
--- Location: FF_X42_Y18_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0));
-
--- Location: MLABCELL_X42_Y18_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|process_0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111111111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_DBG_FIFO_RD_ADDR\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_process_0~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0_combout\);
-
--- Location: FF_X42_Y18_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_RD_ADDR[0]~DUPLICATE_q\);
-
--- Location: FF_X42_Y18_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|DBG_FIFO_WR_ADDR[1]~DUPLICATE_q\);
-
--- Location: LABCELL_X36_Y24_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|debugState~54\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|debugState~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001100000000001100110000110011111111110011001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_0~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~54_combout\);
-
--- Location: FF_X36_Y24_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|debugState~54_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_0~q\);
-
--- Location: LABCELL_X19_Y6_N0
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(0),
- cin => GND,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\);
-
--- Location: LABCELL_X19_Y6_N42
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\ = (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6) &
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001000000000000000100000000000000010000000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(5),
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(6),
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(2),
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\);
-
--- Location: FF_X19_Y6_N2
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~9_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(0));
-
--- Location: LABCELL_X19_Y6_N3
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(1) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(1) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(1),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~10\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\);
-
--- Location: FF_X19_Y6_N5
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~5_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(1));
-
--- Location: LABCELL_X19_Y6_N6
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(2),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~6\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\);
-
--- Location: FF_X19_Y6_N7
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~21_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2));
-
--- Location: LABCELL_X19_Y6_N9
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(3),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~22\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\);
-
--- Location: FF_X19_Y6_N11
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~1_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(3));
-
--- Location: LABCELL_X19_Y6_N12
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(4),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~2\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\);
-
--- Location: FF_X19_Y6_N14
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~13_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(4));
-
--- Location: LABCELL_X19_Y6_N15
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(5),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~14\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\);
-
--- Location: FF_X19_Y6_N17
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~25_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5));
-
--- Location: LABCELL_X19_Y6_N18
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~30\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(6),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~26\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~30\);
-
--- Location: FF_X19_Y6_N20
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~29_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6));
-
--- Location: LABCELL_X19_Y6_N21
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(7),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~30\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17_sumout\);
-
--- Location: FF_X19_Y6_N23
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add0~17_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~1_combout\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(7));
-
--- Location: LABCELL_X19_Y6_N48
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(3) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(7) & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(4) &
--- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(0) & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000100000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(7),
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(4),
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(0),
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(1),
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(3),
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\);
-
--- Location: LABCELL_X19_Y6_N51
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5) & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(5),
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(2),
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(6),
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\);
-
--- Location: LABCELL_X20_Y6_N15
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5_combout\ = !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0),
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5_combout\);
-
--- Location: LABCELL_X19_Y6_N45
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(6) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(5)
--- & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdResetTimer\(2)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000100000000000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(5),
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(2),
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdResetTimer\(6),
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\);
-
--- Location: FF_X20_Y6_N17
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0));
-
--- Location: LABCELL_X20_Y6_N30
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0),
- cin => GND,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\);
-
--- Location: LABCELL_X20_Y6_N33
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(1),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~30_cout\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\);
-
--- Location: LABCELL_X20_Y6_N18
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~13_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~13_sumout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4_combout\);
-
--- Location: FF_X20_Y6_N20
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[1]~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1));
-
--- Location: LABCELL_X20_Y6_N36
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter[2]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~14\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\);
-
--- Location: LABCELL_X20_Y6_N21
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7_combout\ = !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~21_sumout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~21_sumout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7_combout\);
-
--- Location: FF_X20_Y6_N22
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~DUPLICATE_q\);
-
--- Location: LABCELL_X20_Y6_N39
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(3),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~22\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\);
-
--- Location: LABCELL_X20_Y6_N12
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~17_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~17_sumout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6_combout\);
-
--- Location: FF_X20_Y6_N14
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[3]~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3));
-
--- Location: LABCELL_X20_Y6_N42
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~18\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\);
-
--- Location: LABCELL_X20_Y6_N27
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~25_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~25_sumout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8_combout\);
-
--- Location: FF_X20_Y6_N28
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[4]~8_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4));
-
--- Location: LABCELL_X20_Y6_N45
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(5),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~26\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\);
-
--- Location: LABCELL_X20_Y6_N24
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1_combout\ = !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~1_sumout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~1_sumout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1_combout\);
-
--- Location: FF_X20_Y6_N26
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[5]~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5));
-
--- Location: LABCELL_X20_Y6_N9
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(5) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(1) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(0)
--- & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(4))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000010000000100000001000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(1),
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(0),
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(4),
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(5),
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0_combout\);
-
--- Location: LABCELL_X20_Y6_N48
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\ ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~10\ = CARRY(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(6),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~2\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~10\);
-
--- Location: LABCELL_X20_Y6_N54
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~9_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~9_sumout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3_combout\);
-
--- Location: FF_X20_Y6_N56
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[6]~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6));
-
--- Location: LABCELL_X20_Y6_N51
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(7) ) + ( VCC ) + ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(7),
- cin => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~10\,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5_sumout\);
-
--- Location: LABCELL_X20_Y6_N57
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add1~5_sumout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Add1~5_sumout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2_combout\);
-
--- Location: FF_X20_Y6_N59
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[7]~2_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(7));
-
--- Location: FF_X20_Y6_N23
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[2]~7_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(2));
-
--- Location: LABCELL_X20_Y6_N0
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(3) & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(6) & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(7) &
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdInResetCounter\(2))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000010000000100000001000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(6),
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(7),
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(2),
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdInResetCounter\(3),
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1_combout\);
-
--- Location: LABCELL_X19_Y6_N24
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal0~0_combout\ &
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal1~0_combout\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~0_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal3~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001000000000000000111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal0~0_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal1~0_combout\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~0_combout\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal3~1_combout\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1_combout\);
-
--- Location: MLABCELL_X23_Y14_N51
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~1_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~1_combout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder_combout\);
-
--- Location: FF_X23_Y14_N53
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~feeder_combout\,
- asdata => VCC,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\);
-
--- Location: MLABCELL_X23_Y14_N12
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( \myVirtualToplevel|RESET_n~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\);
-
--- Location: MLABCELL_X23_Y14_N33
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ & ( \myVirtualToplevel|RESET_n~q\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~3_combout\ & \myVirtualToplevel|RESET_n~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~3_combout\,
- datad => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~1_combout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~1_combout\);
-
--- Location: LABCELL_X20_Y4_N0
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~45_sumout\ = SUM(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~46\ = CARRY(( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(0),
- cin => GND,
- sumout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~45_sumout\,
- cout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~46\);
-
--- Location: LABCELL_X21_Y8_N24
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder_combout\);
-
--- Location: MLABCELL_X23_Y11_N15
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\);
-
--- Location: FF_X21_Y8_N25
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~feeder_combout\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuDataIn[21]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\);
-
--- Location: FF_X18_Y6_N50
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~13_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(4));
-
--- Location: MLABCELL_X18_Y6_N33
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(4) & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(4),
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~12_combout\);
-
--- Location: FF_X20_Y4_N10
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Add2~13_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~7_combout\,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(3));
-
--- Location: LABCELL_X20_Y4_N36
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(4) & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(6) & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(3)) #
--- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(5)) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(2))))) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(4) & (
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(6) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111000001111000011100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(3),
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(5),
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(6),
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(2),
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(4),
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\);
-
--- Location: LABCELL_X20_Y4_N42
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(8) & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdRefreshCount\(7) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(7),
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdRefreshCount\(8),
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\);
-
--- Location: LABCELL_X19_Y4_N54
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ &
--- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111010100011111111101010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~0_combout\);
-
--- Location: FF_X18_Y6_N56
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~15_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3));
-
--- Location: FF_X18_Y6_N14
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y6_N42
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[0]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(3)) # ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101111000000001111111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(3),
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\);
-
--- Location: LABCELL_X20_Y4_N45
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\ = (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~5_combout\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~4_combout\) #
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~3_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110100001101000011010000110100001101000011010000110100001101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~3_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~4_combout\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~5_combout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\);
-
--- Location: MLABCELL_X18_Y9_N36
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\) #
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001111111111001100111111111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~0_combout\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1_combout\);
-
--- Location: FF_X20_Y8_N26
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\);
-
--- Location: LABCELL_X20_Y8_N24
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000000000001010000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~16_combout\);
-
--- Location: FF_X21_Y18_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_NEW_REG989\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write_OTERM990\);
-
--- Location: LABCELL_X10_Y32_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5_combout\);
-
--- Location: LABCELL_X24_Y31_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~18\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\);
-
--- Location: LABCELL_X24_Y31_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\);
-
--- Location: MLABCELL_X23_Y15_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|l1State~20\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|l1State~20_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|l1State~20_combout\);
-
--- Location: FF_X25_Y19_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]_OTERM3317\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y31_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- cin => GND,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~14\);
-
--- Location: FF_X10_Y37_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|state~31_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\);
-
--- Location: FF_X10_Y37_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|state~25_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\);
-
--- Location: LABCELL_X10_Y37_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|state~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|state~25_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010111111111010101011111111101010101111111110101010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~25_combout\);
-
--- Location: FF_X10_Y37_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|state~25_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\);
-
--- Location: LABCELL_X10_Y37_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|state~31\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|state~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010111111111010101011111111100000000101010100000000010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~31_combout\);
-
--- Location: FF_X10_Y37_N34
-\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|state~31_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\);
-
--- Location: MLABCELL_X34_Y20_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\
--- & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001011111111001000100000000000000000111111110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\);
-
--- Location: LABCELL_X20_Y23_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\);
-
--- Location: MLABCELL_X34_Y20_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010101000000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\);
-
--- Location: FF_X34_Y19_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(14));
-
--- Location: LABCELL_X35_Y19_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\);
-
--- Location: LABCELL_X35_Y19_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(13),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\);
-
--- Location: FF_X34_Y19_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\);
-
--- Location: LABCELL_X35_Y21_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\);
-
--- Location: LABCELL_X35_Y21_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(11),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\);
-
--- Location: LABCELL_X35_Y20_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\);
-
--- Location: LABCELL_X35_Y20_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[13]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\);
-
--- Location: MLABCELL_X34_Y19_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~37_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add56~37_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111110000111111111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~37_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~37_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0_combout\);
-
--- Location: FF_X34_Y19_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1685~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(13));
-
--- Location: LABCELL_X35_Y19_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(14),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\);
-
--- Location: LABCELL_X35_Y20_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\);
-
--- Location: MLABCELL_X34_Y19_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~41_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~41_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010111111111111111110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~41_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~41_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0_combout\);
-
--- Location: FF_X34_Y19_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1684~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[14]~DUPLICATE_q\);
-
--- Location: LABCELL_X35_Y20_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(15),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\);
-
--- Location: LABCELL_X35_Y19_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(15),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\);
-
--- Location: LABCELL_X35_Y20_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add44~45_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010000010100000101001011111010111110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~45_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~45_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0_combout\);
-
--- Location: FF_X35_Y20_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1683~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(15));
-
--- Location: LABCELL_X35_Y20_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\);
-
--- Location: MLABCELL_X34_Y20_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxMemVal.valid~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem_1~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~1_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL2_1~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100000011000011110000001100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxMemVal.valid~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~1_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL2_1~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem_1~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0_combout\);
-
--- Location: LABCELL_X35_Y19_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\);
-
--- Location: MLABCELL_X34_Y20_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder_combout\ = VCC
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder_combout\);
-
--- Location: MLABCELL_X34_Y19_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder_combout\ = VCC
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder_combout\);
-
--- Location: FF_X34_Y19_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[16]~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(16));
-
--- Location: MLABCELL_X34_Y19_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder_combout\ = VCC
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder_combout\);
-
--- Location: FF_X34_Y19_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr[11]~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(11));
-
--- Location: MLABCELL_X34_Y19_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_EndAddr\(16) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\(16),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_EndAddr\(11),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\);
-
--- Location: FF_X34_Y20_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr[16]~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|Equal137~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr\(16));
-
--- Location: MLABCELL_X34_Y20_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC_StartAddr\(16)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpMem~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100110011001111110011001100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC_StartAddr\(16),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(16),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpMem~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\);
-
--- Location: MLABCELL_X34_Y20_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Add56~1_sumout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101011111010101010101111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~1_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1682~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3_combout\);
-
--- Location: FF_X34_Y20_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1682~3_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(16));
-
--- Location: LABCELL_X35_Y20_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(17),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\);
-
--- Location: FF_X35_Y20_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\);
-
--- Location: LABCELL_X35_Y19_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[17]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\);
-
--- Location: LABCELL_X35_Y20_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add44~21_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010000010100000101001011111010111110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~21_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0_combout\);
-
--- Location: FF_X35_Y20_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1681~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(17));
-
--- Location: LABCELL_X35_Y20_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[18]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\);
-
--- Location: FF_X35_Y20_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18));
-
--- Location: LABCELL_X35_Y19_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(18),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\);
-
--- Location: LABCELL_X35_Y20_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add44~25_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010000010100000101001011111010111110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~25_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~25_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0_combout\);
-
--- Location: FF_X35_Y20_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1680~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[18]~DUPLICATE_q\);
-
--- Location: LABCELL_X35_Y20_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(19),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\);
-
--- Location: LABCELL_X35_Y19_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(19),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\);
-
--- Location: MLABCELL_X34_Y19_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~29_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~29_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010001000100010001000100010001110111011101110111011101110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~29_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~29_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0_combout\);
-
--- Location: FF_X34_Y19_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1679~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(19));
-
--- Location: FF_X17_Y17_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~58_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~q\);
-
--- Location: LABCELL_X17_Y17_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxState~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~57_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) #
--- (\myVirtualToplevel|MEM_BUSY~1_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011011111111111111101111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~57_combout\);
-
--- Location: FF_X25_Y19_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_OTERM3311\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23));
-
--- Location: MLABCELL_X28_Y19_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~10\);
-
--- Location: MLABCELL_X28_Y19_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(23),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~10\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\);
-
--- Location: LABCELL_X25_Y19_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_NEW3310\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_OTERM3311\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(23) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010000110111001101110000010011000100111101111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(23),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_OTERM3311\);
-
--- Location: FF_X25_Y19_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]_OTERM3311\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y30_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~90\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~90\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~90\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\);
-
--- Location: LABCELL_X24_Y30_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~62\);
-
--- Location: LABCELL_X21_Y28_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|pc~104\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc~104_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000010100000101000000000000000000101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~61_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~104_combout\);
-
--- Location: LABCELL_X25_Y22_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|pc~105\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc~105_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001010000000000000101000000000010111110000000001011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~61_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~105_combout\);
-
--- Location: FF_X17_Y18_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\);
-
--- Location: FF_X16_Y13_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]_OTERM3345\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23));
-
--- Location: MLABCELL_X18_Y14_N33
-\myVirtualToplevel|MEM_DATA_READ[2]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) & !\myVirtualToplevel|LessThan0~0_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23),
- datad => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\);
-
--- Location: FF_X28_Y26_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~34_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9));
-
--- Location: FF_X25_Y26_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~61_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y31_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~10\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\);
-
--- Location: LABCELL_X24_Y31_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~42\);
-
--- Location: LABCELL_X29_Y26_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|pc~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\);
-
--- Location: LABCELL_X25_Y26_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~41_sumout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000011101000000000001110111111111000111011111111100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~165_combout\);
-
--- Location: FF_X25_Y24_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]_OTERM3278\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\);
-
--- Location: FF_X26_Y26_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]_OTERM3281\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(9));
-
--- Location: FF_X26_Y26_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_OTERM3263\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(3));
-
--- Location: LABCELL_X17_Y17_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ &
--- !\myVirtualToplevel|MEM_BUSY~1_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000100000001000000000000000000000001000000010000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\);
-
--- Location: FF_X16_Y15_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\);
-
--- Location: LABCELL_X16_Y15_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\);
-
--- Location: LABCELL_X16_Y15_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000001110000001100110111011100000000000000000011001101110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1_combout\);
-
--- Location: FF_X16_Y15_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\);
-
--- Location: LABCELL_X26_Y26_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_NEW3259\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_OTERM3260\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2)))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011011111000000101101111100010011110011100001001111001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_OTERM3260\);
-
--- Location: FF_X26_Y26_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_OTERM3260\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2));
-
--- Location: MLABCELL_X28_Y20_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~q\ ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2),
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\);
-
--- Location: MLABCELL_X28_Y20_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\);
-
--- Location: LABCELL_X26_Y26_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_NEW3262\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_OTERM3263\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(3))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~81_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(3)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(3),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~81_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_OTERM3263\);
-
--- Location: FF_X26_Y26_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]_OTERM3263\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y20_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\);
-
--- Location: FF_X26_Y26_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_OTERM3287\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4));
-
--- Location: LABCELL_X26_Y26_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_NEW3286\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_OTERM3287\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add3~49_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~49_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_OTERM3287\);
-
--- Location: FF_X26_Y26_N22
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]_OTERM3287\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y20_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\);
-
--- Location: FF_X25_Y22_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_OTERM3284\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5));
-
--- Location: LABCELL_X25_Y22_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_NEW3283\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_OTERM3284\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~53_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101010101000011110101010100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~53_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_OTERM3284\);
-
--- Location: FF_X25_Y22_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]_OTERM3284\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y20_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\);
-
--- Location: LABCELL_X26_Y26_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_NEW3271\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_OTERM3272\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~69_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~69_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_OTERM3272\);
-
--- Location: FF_X26_Y26_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_OTERM3272\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6));
-
--- Location: MLABCELL_X28_Y20_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\);
-
--- Location: LABCELL_X26_Y26_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_NEW3268\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_OTERM3269\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add3~73_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111110001000000011111000100001011111110110000101111111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~73_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_OTERM3269\);
-
--- Location: FF_X26_Y26_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_OTERM3269\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7));
-
--- Location: MLABCELL_X28_Y20_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\);
-
--- Location: LABCELL_X26_Y26_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_NEW3265\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_OTERM3266\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add3~77_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~77_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_OTERM3266\);
-
--- Location: FF_X26_Y26_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_OTERM3266\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8));
-
--- Location: FF_X26_Y26_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]_OTERM3269\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\);
-
--- Location: FF_X26_Y26_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]_OTERM3272\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\);
-
--- Location: FF_X25_Y26_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~82_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5));
-
--- Location: FF_X26_Y26_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]_OTERM3260\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y26_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\);
-
--- Location: LABCELL_X26_Y26_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\);
-
--- Location: LABCELL_X26_Y26_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\);
-
--- Location: LABCELL_X26_Y26_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\);
-
--- Location: LABCELL_X26_Y26_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\);
-
--- Location: LABCELL_X26_Y26_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(5),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\);
-
--- Location: LABCELL_X26_Y26_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\);
-
--- Location: LABCELL_X26_Y26_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~93\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[7]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[7]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~90\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\);
-
--- Location: LABCELL_X26_Y26_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~94\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\);
-
--- Location: LABCELL_X26_Y26_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(9) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(9) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[9]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[9]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(9),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\);
-
--- Location: LABCELL_X26_Y25_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[10]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\);
-
--- Location: FF_X25_Y24_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]_OTERM3275\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y20_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\);
-
--- Location: MLABCELL_X28_Y20_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\);
-
--- Location: MLABCELL_X28_Y20_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\);
-
--- Location: LABCELL_X21_Y26_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\);
-
--- Location: MLABCELL_X18_Y28_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111011111111111111111111111111111111111011111101111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\);
-
--- Location: MLABCELL_X18_Y27_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000100100000000000000000000000001000000001010010000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\);
-
--- Location: LABCELL_X21_Y26_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100001100111111111111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\);
-
--- Location: LABCELL_X21_Y26_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr159~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~21_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_RESYN8923_BDD8924\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000110000001100110011000000110001001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~24_RESYN8923_BDD8924\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr159~combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~21_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\);
-
--- Location: FF_X23_Y25_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~102_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11));
-
--- Location: LABCELL_X24_Y31_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\);
-
--- Location: LABCELL_X24_Y30_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\);
-
--- Location: FF_X23_Y23_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~87_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~45_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10));
-
--- Location: LABCELL_X24_Y30_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\);
-
--- Location: MLABCELL_X23_Y25_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|pc~100\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc~100_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\)))
--- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~6_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000000100000001000000010000000111000001110000011100000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~57_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~100_combout\);
-
--- Location: MLABCELL_X23_Y25_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|pc~99\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc~99_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~57_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~4_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000001010000010100001111000011110000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~57_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc~99_combout\);
-
--- Location: LABCELL_X17_Y27_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100000000000000000000000000000000000000000000000000001000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\);
-
--- Location: LABCELL_X20_Y18_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[11]~feeder_combout\);
-
--- Location: LABCELL_X7_Y18_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100100010001100110010001000110011001000100011001100100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~1_combout\);
-
--- Location: FF_X12_Y35_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1152\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1153\);
-
--- Location: LABCELL_X16_Y28_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\);
-
--- Location: LABCELL_X16_Y29_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000000000000000000000000000000000000000000000000000000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\);
-
--- Location: MLABCELL_X4_Y33_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111111111111111111111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\);
-
--- Location: FF_X4_Y33_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1));
-
--- Location: FF_X4_Y33_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(3));
-
--- Location: LABCELL_X19_Y37_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\);
-
--- Location: LABCELL_X16_Y29_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|divStart~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|divStart~1_combout\);
-
--- Location: LABCELL_X14_Y10_N0
-\~GND\ : cyclonev_lcell_comb
--- Equation(s):
--- \~GND~combout\ = GND
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- combout => \~GND~combout\);
-
--- Location: FF_X16_Y29_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|divStart\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|divStart~1_combout\,
- asdata => \~GND~combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\);
-
--- Location: LABCELL_X2_Y29_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\);
-
--- Location: FF_X4_Y33_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2));
-
--- Location: MLABCELL_X4_Y33_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000111111000000000011111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(1),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(3),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(2),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\);
-
--- Location: FF_X14_Y32_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|divComplete\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\);
-
--- Location: MLABCELL_X4_Y33_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\ & \myVirtualToplevel|RESET_n~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000010100000101000000000000011110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\);
-
--- Location: FF_X4_Y33_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(0));
-
--- Location: MLABCELL_X4_Y33_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(0) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101011110000000010101111000000001111111101010000111111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5_combout\);
-
--- Location: FF_X4_Y33_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0));
-
--- Location: FF_X4_Y33_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\);
-
--- Location: MLABCELL_X4_Y33_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1))))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110111110111000011011111011100001000111100100000100011110010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4_combout\);
-
--- Location: FF_X4_Y33_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[1]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1));
-
--- Location: MLABCELL_X4_Y33_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\);
-
--- Location: MLABCELL_X4_Y33_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010001010100111111101010111000000001010100011111101110101011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(1),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(2),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7_combout\);
-
--- Location: FF_X4_Y33_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[2]~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2));
-
--- Location: MLABCELL_X4_Y33_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add59~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divQuotientFractional\(2)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111011101110111011101110111011110001000100010001000100010001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divQuotientFractional\(3),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\);
-
--- Location: MLABCELL_X4_Y33_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add59~0_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000011100000010111111011111100000000101000000001111111111111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add59~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6_combout\);
-
--- Location: FF_X4_Y33_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[3]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3));
-
--- Location: MLABCELL_X4_Y33_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(2) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(3),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\);
-
--- Location: MLABCELL_X4_Y33_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000000111111111111000000000111000000001111110111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3_combout\);
-
--- Location: FF_X4_Y33_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4));
-
--- Location: MLABCELL_X4_Y33_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add61~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000110000001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\);
-
--- Location: MLABCELL_X4_Y33_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add61~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5))) # (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[4]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5)
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|process_0~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101011101010011010101110101001101011011010100110101101101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(5),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[4]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_process_0~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add61~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2_combout\);
-
--- Location: FF_X4_Y33_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[5]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5));
-
--- Location: MLABCELL_X4_Y33_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(5) & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~1_combout\))
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001010000000000000101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(5),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(4),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\);
-
--- Location: LABCELL_X14_Y32_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal157~2_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110011000000001111001111111111111100111111111111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal157~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1_combout\);
-
--- Location: FF_X14_Y32_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y32_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|divComplete~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divStart~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\);
-
--- Location: LABCELL_X10_Y33_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000000000000000000000000000000000000000000000000000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\);
-
--- Location: LABCELL_X10_Y33_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|state~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000010000000100000000000100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~27_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\);
-
--- Location: LABCELL_X10_Y33_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|state~27\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|state~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|state~26_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111101011111010100110011001100111111011111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~26_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~27_combout\);
-
--- Location: FF_X10_Y33_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|state~27_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\);
-
--- Location: FF_X25_Y29_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~76_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4));
-
--- Location: FF_X26_Y23_N22
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]_OTERM3314\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y30_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\);
-
--- Location: LABCELL_X24_Y30_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\);
-
--- Location: FF_X26_Y21_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~117_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~69_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\);
-
--- Location: FF_X24_Y21_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~92_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~49_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13));
-
--- Location: MLABCELL_X28_Y19_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\);
-
--- Location: FF_X25_Y24_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_OTERM3299\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12));
-
--- Location: LABCELL_X25_Y24_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_NEW3298\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_OTERM3299\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~33_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101000111010001110100011101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~33_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_OTERM3299\);
-
--- Location: FF_X25_Y24_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]_OTERM3299\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y19_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\);
-
--- Location: LABCELL_X25_Y24_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_NEW3295\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_OTERM3296\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~37_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~37_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_OTERM3296\);
-
--- Location: FF_X25_Y24_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_OTERM3296\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13));
-
--- Location: MLABCELL_X28_Y19_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\);
-
--- Location: MLABCELL_X28_Y19_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\);
-
--- Location: LABCELL_X26_Y24_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_NEW3289\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_OTERM3290\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~45_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~45_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_OTERM3290\);
-
--- Location: FF_X26_Y24_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[15]_OTERM3290\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15));
-
--- Location: MLABCELL_X28_Y19_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\);
-
--- Location: LABCELL_X26_Y21_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_NEW3322\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_OTERM3323\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~1_sumout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111101010101010101010000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~1_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_OTERM3323\);
-
--- Location: FF_X26_Y24_N22
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[16]_OTERM3323\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16));
-
--- Location: MLABCELL_X28_Y19_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\);
-
--- Location: FF_X26_Y23_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_OTERM3308\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17));
-
--- Location: LABCELL_X26_Y23_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_NEW3307\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_OTERM3308\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add3~21_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(17) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100110011000011110011001100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~21_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(17),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_OTERM3308\);
-
--- Location: FF_X26_Y23_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]_OTERM3308\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y19_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add3~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add3~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add3~26\);
-
--- Location: FF_X26_Y23_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_OTERM3305\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18));
-
--- Location: FF_X25_Y20_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~142_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~89_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y23_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_NEW3304\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_OTERM3305\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add3~25_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000111111001100000011111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add3~25_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(18),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_OTERM3305\);
-
--- Location: FF_X26_Y23_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]_OTERM3305\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y30_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~66\);
-
--- Location: FF_X25_Y21_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~112_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~65_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\);
-
--- Location: FF_X28_Y23_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_OTERM1879\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15));
-
--- Location: FF_X29_Y24_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_OTERM1897\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6));
-
--- Location: FF_X29_Y24_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_OTERM1901\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4));
-
--- Location: MLABCELL_X28_Y20_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110011111100111111111111111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\);
-
--- Location: LABCELL_X29_Y24_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_OTERM1905\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100011000100000010001100010000110011111111110011001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]_NEW1904_RESYN12812_BDD12813\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_OTERM1905\);
-
--- Location: FF_X29_Y24_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_OTERM1905\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2));
-
--- Location: MLABCELL_X28_Y24_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(2),
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\);
-
--- Location: MLABCELL_X28_Y24_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~18\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\);
-
--- Location: FF_X29_Y24_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_OTERM1903\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3));
-
--- Location: LABCELL_X29_Y24_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_NEW1902\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_OTERM1903\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~21_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010101110000001001010111000010101101111110001010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~21_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_OTERM1903\);
-
--- Location: FF_X29_Y24_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]_OTERM1903\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y24_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\);
-
--- Location: LABCELL_X29_Y24_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_NEW1900\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_OTERM1901\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~25_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~25_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_OTERM1901\);
-
--- Location: FF_X29_Y24_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]_OTERM1901\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y24_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\);
-
--- Location: FF_X29_Y25_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_OTERM1899\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5));
-
--- Location: LABCELL_X29_Y25_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_NEW1898\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_OTERM1899\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~29_sumout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100100111001001110010011100100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~29_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_OTERM1899\);
-
--- Location: FF_X29_Y25_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]_OTERM1899\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y24_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\);
-
--- Location: LABCELL_X29_Y24_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_NEW1896\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_OTERM1897\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~1_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(6),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~1_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_OTERM1897\);
-
--- Location: FF_X29_Y24_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]_OTERM1897\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y24_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\);
-
--- Location: LABCELL_X29_Y24_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_NEW1894\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_OTERM1895\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~5_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_OTERM1895\);
-
--- Location: FF_X29_Y24_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[7]_OTERM1895\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7));
-
--- Location: MLABCELL_X28_Y24_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\);
-
--- Location: MLABCELL_X28_Y24_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_NEW1892\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_OTERM1893\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~9_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_OTERM1893\);
-
--- Location: FF_X28_Y24_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[8]_OTERM1893\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8));
-
--- Location: MLABCELL_X28_Y24_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~10\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\);
-
--- Location: LABCELL_X29_Y24_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_NEW1890\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_OTERM1891\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~13_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_OTERM1891\);
-
--- Location: FF_X29_Y24_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_OTERM1891\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9));
-
--- Location: MLABCELL_X28_Y24_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\);
-
--- Location: LABCELL_X29_Y24_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_NEW1888\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_OTERM1889\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~33_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~33_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_OTERM1889\);
-
--- Location: FF_X29_Y24_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_OTERM1889\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10));
-
--- Location: MLABCELL_X28_Y24_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(11),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\);
-
--- Location: LABCELL_X29_Y24_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_NEW1886\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_OTERM1887\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~37_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~37_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_OTERM1887\);
-
--- Location: FF_X29_Y24_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_OTERM1887\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11));
-
--- Location: MLABCELL_X28_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(12),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\);
-
--- Location: LABCELL_X29_Y24_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_NEW1884\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_OTERM1885\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~53_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010101110000001001010111000010101101111110001010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~53_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_OTERM1885\);
-
--- Location: FF_X29_Y24_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_OTERM1885\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12));
-
--- Location: MLABCELL_X28_Y23_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\);
-
--- Location: MLABCELL_X28_Y23_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_NEW1882\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_OTERM1883\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~57_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010101110000001001010111000010101101111110001010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~57_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_OTERM1883\);
-
--- Location: FF_X28_Y23_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[13]_OTERM1883\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13));
-
--- Location: MLABCELL_X28_Y23_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\);
-
--- Location: MLABCELL_X28_Y23_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_NEW1880\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_OTERM1881\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~41_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~41_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_OTERM1881\);
-
--- Location: FF_X28_Y23_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_OTERM1881\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14));
-
--- Location: MLABCELL_X28_Y23_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\);
-
--- Location: MLABCELL_X28_Y23_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_NEW1878\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_OTERM1879\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~45_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~45_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_OTERM1879\);
-
--- Location: FF_X28_Y23_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]_OTERM1879\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y23_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\);
-
--- Location: MLABCELL_X28_Y23_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_NEW1876\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_OTERM1877\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~49_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~49_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_OTERM1877\);
-
--- Location: FF_X28_Y23_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_OTERM1877\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16));
-
--- Location: FF_X28_Y23_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]_OTERM1881\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\);
-
--- Location: FF_X29_Y24_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]_OTERM1885\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y30_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add37~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~54\);
-
--- Location: FF_X24_Y21_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~97_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~53_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\);
-
--- Location: FF_X29_Y24_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]_OTERM1887\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\);
-
--- Location: FF_X29_Y24_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]_OTERM1889\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\);
-
--- Location: FF_X29_Y24_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]_OTERM1891\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\);
-
--- Location: FF_X28_Y26_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~42_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(8));
-
--- Location: FF_X31_Y26_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~50_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7));
-
--- Location: MLABCELL_X28_Y26_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~93\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~93_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- cin => GND,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~93_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\);
-
--- Location: MLABCELL_X28_Y26_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~94\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\);
-
--- Location: MLABCELL_X28_Y26_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~90\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\);
-
--- Location: MLABCELL_X28_Y26_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\);
-
--- Location: MLABCELL_X28_Y26_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\);
-
--- Location: MLABCELL_X28_Y26_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(5),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\);
-
--- Location: MLABCELL_X28_Y26_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\);
-
--- Location: MLABCELL_X28_Y26_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100110011001100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\);
-
--- Location: MLABCELL_X28_Y26_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(8) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(8) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\);
-
--- Location: MLABCELL_X28_Y26_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\);
-
--- Location: MLABCELL_X28_Y25_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\);
-
--- Location: MLABCELL_X28_Y25_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\);
-
--- Location: MLABCELL_X28_Y25_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\);
-
--- Location: MLABCELL_X28_Y25_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\);
-
--- Location: MLABCELL_X28_Y25_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110011001100110000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\);
-
--- Location: MLABCELL_X28_Y25_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\);
-
--- Location: MLABCELL_X28_Y25_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\);
-
--- Location: FF_X25_Y24_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~147_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~93_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\);
-
--- Location: FF_X28_Y23_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_OTERM1875\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y25_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\);
-
--- Location: FF_X28_Y24_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_OTERM1873\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y25_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\);
-
--- Location: MLABCELL_X28_Y25_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~49_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~65_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~61_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~69_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~53_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~57_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\);
-
--- Location: FF_X25_Y23_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_OTERM1867\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21));
-
--- Location: FF_X28_Y24_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]_OTERM1869\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y23_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(18),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\);
-
--- Location: MLABCELL_X28_Y23_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\);
-
--- Location: LABCELL_X29_Y21_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_NEW1870\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_OTERM1871\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~85_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101010101000011110101010100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~85_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_OTERM1871\);
-
--- Location: FF_X29_Y21_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[19]_OTERM1871\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19));
-
--- Location: MLABCELL_X28_Y23_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\);
-
--- Location: MLABCELL_X28_Y23_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\);
-
--- Location: LABCELL_X25_Y23_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_NEW1866\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_OTERM1867\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~69_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(21),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~69_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_OTERM1867\);
-
--- Location: FF_X25_Y23_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]_OTERM1867\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y23_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(22),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~74\);
-
--- Location: MLABCELL_X28_Y23_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_NEW1864\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_OTERM1865\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~73_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~73_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_OTERM1865\);
-
--- Location: FF_X28_Y23_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_OTERM1865\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22));
-
--- Location: MLABCELL_X28_Y23_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\);
-
--- Location: FF_X25_Y23_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_OTERM1863\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23));
-
--- Location: LABCELL_X25_Y23_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_NEW1862\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_OTERM1863\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add15~77_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~77_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(23),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_OTERM1863\);
-
--- Location: FF_X25_Y23_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]_OTERM1863\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y25_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\);
-
--- Location: MLABCELL_X28_Y25_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\);
-
--- Location: MLABCELL_X28_Y25_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~10\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\);
-
--- Location: MLABCELL_X28_Y25_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(22),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~18\);
-
--- Location: MLABCELL_X28_Y25_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~18\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\);
-
--- Location: MLABCELL_X28_Y26_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~85_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~81_sumout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~77_sumout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~85_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~81_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~77_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~73_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\);
-
--- Location: LABCELL_X29_Y25_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0_combout\);
-
--- Location: LABCELL_X29_Y25_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2_combout\);
-
--- Location: LABCELL_X29_Y25_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3_combout\);
-
--- Location: LABCELL_X29_Y25_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000000000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\);
-
--- Location: FF_X28_Y23_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]_OTERM1865\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\);
-
--- Location: FF_X28_Y21_N34
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_OTERM1923\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15));
-
--- Location: FF_X29_Y22_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_OTERM1947\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3));
-
--- Location: LABCELL_X29_Y22_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_NEW1946\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_OTERM1947\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111111110101111101010000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_OTERM1947\);
-
--- Location: FF_X29_Y22_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]_OTERM1947\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\);
-
--- Location: LABCELL_X31_Y21_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\,
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\);
-
--- Location: LABCELL_X31_Y21_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~18\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\);
-
--- Location: LABCELL_X26_Y22_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_NEW1944\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_OTERM1945\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~21_sumout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~21_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_OTERM1945\);
-
--- Location: FF_X26_Y22_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[4]_OTERM1945\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4));
-
--- Location: LABCELL_X31_Y21_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\);
-
--- Location: LABCELL_X26_Y21_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_NEW1942\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_OTERM1943\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~25_sumout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~25_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_OTERM1943\);
-
--- Location: FF_X26_Y21_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[5]_OTERM1943\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5));
-
--- Location: LABCELL_X31_Y21_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\);
-
--- Location: LABCELL_X31_Y21_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\);
-
--- Location: FF_X26_Y20_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_OTERM1939\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7));
-
--- Location: LABCELL_X26_Y20_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_NEW1938\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_OTERM1939\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100110011000011110011001100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~5_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_OTERM1939\);
-
--- Location: FF_X26_Y20_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]_OTERM1939\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\);
-
--- Location: LABCELL_X31_Y21_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\);
-
--- Location: LABCELL_X26_Y22_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_NEW1936\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_OTERM1937\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add16~9_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_OTERM1937\);
-
--- Location: FF_X26_Y22_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[8]_OTERM1937\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8));
-
--- Location: LABCELL_X31_Y21_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~10\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\);
-
--- Location: LABCELL_X26_Y22_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_NEW1934\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_OTERM1935\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~13_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~13_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_OTERM1935\);
-
--- Location: FF_X26_Y22_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_OTERM1935\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9));
-
--- Location: LABCELL_X31_Y21_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\);
-
--- Location: FF_X28_Y21_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_OTERM1933\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10));
-
--- Location: MLABCELL_X28_Y21_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_NEW1932\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_OTERM1933\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~29_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010101110000001001010111000010101101111110001010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~29_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_OTERM1933\);
-
--- Location: FF_X28_Y21_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]_OTERM1933\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\);
-
--- Location: LABCELL_X31_Y21_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\);
-
--- Location: FF_X28_Y21_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_OTERM1931\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11));
-
--- Location: MLABCELL_X28_Y21_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_NEW1930\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_OTERM1931\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(11))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~33_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010101110000001001010111000010101101111110001010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~33_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_OTERM1931\);
-
--- Location: FF_X28_Y21_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]_OTERM1931\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\);
-
--- Location: LABCELL_X31_Y21_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\);
-
--- Location: FF_X28_Y21_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_OTERM1929\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12));
-
--- Location: MLABCELL_X28_Y21_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_NEW1928\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_OTERM1929\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~49_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010101110000001001010111000010101101111110001010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~49_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_OTERM1929\);
-
--- Location: FF_X28_Y21_N22
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]_OTERM1929\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\);
-
--- Location: LABCELL_X31_Y20_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\);
-
--- Location: MLABCELL_X28_Y21_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_NEW1926\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_OTERM1927\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add16~53_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~53_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_OTERM1927\);
-
--- Location: FF_X28_Y21_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_OTERM1927\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13));
-
--- Location: LABCELL_X31_Y20_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\);
-
--- Location: FF_X25_Y21_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~122_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~73_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14));
-
--- Location: MLABCELL_X28_Y21_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_NEW1924\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_OTERM1925\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~37_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010101110000001001010111000010101101111110001010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~37_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_OTERM1925\);
-
--- Location: FF_X28_Y21_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[14]_OTERM1925\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14));
-
--- Location: LABCELL_X31_Y20_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\);
-
--- Location: MLABCELL_X28_Y21_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_NEW1922\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_OTERM1923\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add16~41_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~41_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_OTERM1923\);
-
--- Location: FF_X28_Y21_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]_OTERM1923\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\);
-
--- Location: LABCELL_X31_Y20_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[16]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\);
-
--- Location: FF_X28_Y21_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_OTERM1921\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16));
-
--- Location: MLABCELL_X28_Y21_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_NEW1920\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_OTERM1921\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~45_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101010101000011110101010100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~45_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_OTERM1921\);
-
--- Location: FF_X28_Y21_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]_OTERM1921\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\);
-
--- Location: LABCELL_X31_Y20_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\);
-
--- Location: MLABCELL_X28_Y22_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_NEW1918\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_OTERM1919\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add16~57_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~57_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_OTERM1919\);
-
--- Location: FF_X28_Y22_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[17]_OTERM1919\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17));
-
--- Location: LABCELL_X31_Y20_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(18),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\);
-
--- Location: MLABCELL_X28_Y22_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_NEW1916\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_OTERM1917\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~61_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101111101011111010100000011000000111111001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~61_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_OTERM1917\);
-
--- Location: FF_X28_Y22_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_OTERM1917\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18));
-
--- Location: LABCELL_X31_Y20_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\);
-
--- Location: MLABCELL_X28_Y22_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_NEW1914\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_OTERM1915\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~77_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010101110000001001010111000010101101111110001010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~77_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_OTERM1915\);
-
--- Location: FF_X28_Y22_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_OTERM1915\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19));
-
--- Location: LABCELL_X31_Y20_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\);
-
--- Location: LABCELL_X29_Y21_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_NEW1912\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_OTERM1913\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~81_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011111100111111001100000101000001011111010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~81_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_OTERM1913\);
-
--- Location: FF_X29_Y21_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[20]_OTERM1913\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20));
-
--- Location: LABCELL_X31_Y20_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(21),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\);
-
--- Location: LABCELL_X29_Y21_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_NEW1910\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_OTERM1911\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~65_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~65_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(21),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_OTERM1911\);
-
--- Location: FF_X29_Y21_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_OTERM1911\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21));
-
--- Location: LABCELL_X31_Y20_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~70\);
-
--- Location: MLABCELL_X28_Y22_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_NEW1908\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_OTERM1909\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~69_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010101110000001001010111000010101101111110001010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~69_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_OTERM1909\);
-
--- Location: FF_X28_Y22_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_OTERM1909\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22));
-
--- Location: FF_X29_Y21_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]_OTERM1911\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\);
-
--- Location: FF_X28_Y21_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]_OTERM1927\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\);
-
--- Location: FF_X29_Y24_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]_OTERM1905\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y24_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1_combout\);
-
--- Location: FF_X26_Y24_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[2]~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2));
-
--- Location: LABCELL_X31_Y24_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) ) + ( !VCC ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) ) + ( !VCC ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111110011001100000000000000000011001111001100",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2),
- cin => GND,
- sharein => GND,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\);
-
--- Location: LABCELL_X31_Y24_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~38\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~39\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\);
-
--- Location: LABCELL_X31_Y24_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(4) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~42\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~43\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\);
-
--- Location: LABCELL_X31_Y24_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~46\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~47\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\);
-
--- Location: LABCELL_X31_Y24_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(6),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~50\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~51\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\);
-
--- Location: LABCELL_X31_Y24_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~54\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~55\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\);
-
--- Location: LABCELL_X31_Y24_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~58\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~59\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\);
-
--- Location: LABCELL_X31_Y24_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010000000000000000000000001010101001010101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~82\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~83\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\);
-
--- Location: LABCELL_X31_Y24_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[10]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[10]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~86\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~87\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\);
-
--- Location: LABCELL_X31_Y24_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~62\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~63\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\);
-
--- Location: LABCELL_X31_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(12),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~66\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~67\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\);
-
--- Location: LABCELL_X31_Y23_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[13]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~70\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~71\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\);
-
--- Location: LABCELL_X31_Y23_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~18\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~19\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\);
-
--- Location: LABCELL_X31_Y23_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(15),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~22\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~23\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\);
-
--- Location: LABCELL_X31_Y23_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[16]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010000000000000000000000001010101001010101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[16]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~26\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~27\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\);
-
--- Location: LABCELL_X31_Y23_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~30\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~31\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\);
-
--- Location: LABCELL_X31_Y23_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(18)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(18),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~74\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~75\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\);
-
--- Location: LABCELL_X31_Y23_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~34\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~35\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\);
-
--- Location: LABCELL_X31_Y23_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(20) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(20),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~78\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~79\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\);
-
--- Location: LABCELL_X31_Y23_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010100000101000000000000000000001010010110100101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~2\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~3\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\);
-
--- Location: LABCELL_X31_Y23_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~11\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~6\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~7\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~10\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~11\);
-
--- Location: LABCELL_X31_Y23_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add18~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add18~11\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add18~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~10\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~11\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\);
-
--- Location: LABCELL_X29_Y21_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\);
-
--- Location: LABCELL_X31_Y24_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~81_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~85_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2_combout\);
-
--- Location: LABCELL_X31_Y23_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~77_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~65_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~73_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~69_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~61_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\);
-
--- Location: LABCELL_X31_Y24_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~37_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~37_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~45_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~49_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~57_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~53_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0_combout\);
-
--- Location: LABCELL_X31_Y23_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000100000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~33_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~29_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~17_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~21_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~25_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\);
-
--- Location: LABCELL_X29_Y21_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_RESYN8619_BDD8620\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000001100000000000000000000000100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_RESYN8619_BDD8620\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\);
-
--- Location: LABCELL_X31_Y20_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add16~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add16~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\);
-
--- Location: FF_X28_Y22_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_OTERM1907\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23));
-
--- Location: MLABCELL_X28_Y22_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_NEW1906\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_OTERM1907\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add16~73_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010101110000001001010111000010101101111110001010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add16~73_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(23),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_OTERM1907\);
-
--- Location: FF_X28_Y22_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]_OTERM1907\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\);
-
--- Location: FF_X25_Y22_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~107_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~61_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20));
-
--- Location: FF_X25_Y20_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_OTERM2668\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18));
-
--- Location: FF_X25_Y20_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]_OTERM2665\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\);
-
--- Location: FF_X25_Y21_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_OTERM2656\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14));
-
--- Location: FF_X26_Y20_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_OTERM2632\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6));
-
--- Location: LABCELL_X24_Y23_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_NEW2625\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_OTERM2626\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100111111001100000011111100110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_OTERM2626\);
-
--- Location: FF_X24_Y23_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[4]_OTERM2626\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4));
-
--- Location: LABCELL_X26_Y18_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4),
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\);
-
--- Location: LABCELL_X26_Y18_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(5),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\);
-
--- Location: LABCELL_X25_Y18_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_NEW2628\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_OTERM2629\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~25_sumout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100000001111100011111000100001011000010111111101111111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~25_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_OTERM2629\);
-
--- Location: FF_X25_Y18_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_OTERM2629\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5));
-
--- Location: LABCELL_X26_Y18_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\);
-
--- Location: LABCELL_X26_Y20_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_NEW2631\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_OTERM2632\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(6) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001100111111110000110000000000001111111111111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(6),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_OTERM2632\);
-
--- Location: FF_X26_Y20_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]_OTERM2632\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y18_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~18\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\);
-
--- Location: FF_X26_Y20_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_OTERM2635\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7));
-
--- Location: LABCELL_X26_Y20_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_NEW2634\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_OTERM2635\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000101111100001111010100001111000001011111111111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~13_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_OTERM2635\);
-
--- Location: FF_X26_Y20_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]_OTERM2635\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y18_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\);
-
--- Location: FF_X25_Y18_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_OTERM2638\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8));
-
--- Location: LABCELL_X25_Y18_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_NEW2637\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_OTERM2638\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~9_sumout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111111100001111111100000011000000111111001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~9_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(8),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_OTERM2638\);
-
--- Location: FF_X25_Y18_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]_OTERM2638\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y18_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~10\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\);
-
--- Location: FF_X25_Y18_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_OTERM2641\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9));
-
--- Location: LABCELL_X25_Y18_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_NEW2640\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_OTERM2641\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100000001111100011111000100001101000011011111110111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~5_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(9),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_OTERM2641\);
-
--- Location: FF_X25_Y18_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]_OTERM2641\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y18_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\);
-
--- Location: LABCELL_X24_Y23_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_NEW2643\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_OTERM2644\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~29_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100100111001001110010011100100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~29_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_OTERM2644\);
-
--- Location: FF_X24_Y23_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[10]_OTERM2644\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10));
-
--- Location: LABCELL_X26_Y18_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\);
-
--- Location: FF_X24_Y21_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_OTERM2647\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11));
-
--- Location: LABCELL_X24_Y21_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_NEW2646\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_OTERM2647\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~41_sumout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001111001100110000111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~41_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_OTERM2647\);
-
--- Location: FF_X24_Y21_N22
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]_OTERM2647\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y18_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\);
-
--- Location: FF_X24_Y21_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_OTERM2650\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12));
-
--- Location: LABCELL_X24_Y21_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_NEW2649\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_OTERM2650\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~37_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101000111010001110100011101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~37_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_OTERM2650\);
-
--- Location: FF_X24_Y21_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]_OTERM2650\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y18_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\);
-
--- Location: LABCELL_X24_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_NEW2652\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_OTERM2653\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~33_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011011000110110001101100011011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~33_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_OTERM2653\);
-
--- Location: FF_X24_Y23_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[13]_OTERM2653\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13));
-
--- Location: LABCELL_X26_Y18_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\);
-
--- Location: LABCELL_X25_Y21_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_NEW2655\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_OTERM2656\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~57_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~57_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_OTERM2656\);
-
--- Location: FF_X25_Y21_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]_OTERM2656\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y18_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\);
-
--- Location: FF_X25_Y21_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_OTERM2659\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15));
-
--- Location: LABCELL_X25_Y21_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_NEW2658\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_OTERM2659\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~53_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~53_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_OTERM2659\);
-
--- Location: FF_X25_Y21_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]_OTERM2659\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y18_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\);
-
--- Location: FF_X25_Y21_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_OTERM2662\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16));
-
--- Location: LABCELL_X25_Y21_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_NEW2661\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_OTERM2662\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~49_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~49_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(16),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_OTERM2662\);
-
--- Location: FF_X25_Y21_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]_OTERM2662\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y18_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\);
-
--- Location: LABCELL_X26_Y18_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\);
-
--- Location: LABCELL_X25_Y20_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_NEW2667\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_OTERM2668\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~73_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~73_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_OTERM2668\);
-
--- Location: FF_X25_Y20_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]_OTERM2668\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y18_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\);
-
--- Location: LABCELL_X25_Y20_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_NEW2670\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_OTERM2671\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~69_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101000111010001110100011101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~69_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_OTERM2671\);
-
--- Location: FF_X25_Y20_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_OTERM2671\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19));
-
--- Location: LABCELL_X26_Y18_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\);
-
--- Location: LABCELL_X25_Y20_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_NEW2673\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_OTERM2674\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~45_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~45_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_OTERM2674\);
-
--- Location: FF_X25_Y20_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_OTERM2674\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20));
-
--- Location: LABCELL_X26_Y18_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\);
-
--- Location: LABCELL_X25_Y23_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_NEW2676\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_OTERM2677\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~65_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011110010000000101111001000000111111101110000011111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~65_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_OTERM2677\);
-
--- Location: FF_X25_Y23_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[21]_OTERM2677\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21));
-
--- Location: FF_X25_Y18_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]_OTERM2629\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\);
-
--- Location: FF_X25_Y18_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\);
-
--- Location: FF_X25_Y18_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2));
-
--- Location: LABCELL_X24_Y19_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~94\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94_cout\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( !VCC ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~95\ = SHARE(VCC)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- cin => GND,
- sharein => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94_cout\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~95\);
-
--- Location: LABCELL_X24_Y19_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~90\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~95\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94_cout\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\ = SHARE(\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111111100000000000000001111111100000000",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~94_cout\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~95\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\);
-
--- Location: LABCELL_X24_Y19_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~90_cout\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~91\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\);
-
--- Location: LABCELL_X24_Y19_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~50\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~51\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\);
-
--- Location: LABCELL_X24_Y19_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~38\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~39\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\);
-
--- Location: LABCELL_X24_Y19_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011000000110000000000000000001100001111000011",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~54\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~55\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\);
-
--- Location: LABCELL_X24_Y19_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001100110000000000000000001100110000110011",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~42\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~43\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\);
-
--- Location: LABCELL_X24_Y19_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~46\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~47\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\);
-
--- Location: LABCELL_X24_Y19_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~26\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~27\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\);
-
--- Location: LABCELL_X24_Y19_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(9),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~30\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~31\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\);
-
--- Location: LABCELL_X24_Y18_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~34\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~35\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\);
-
--- Location: LABCELL_X24_Y18_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010100000101000000000000000000001010010110100101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~10\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~11\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\);
-
--- Location: LABCELL_X24_Y18_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100000011000000000000000000001100001111000011",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~14\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~15\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\);
-
--- Location: LABCELL_X24_Y18_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~58\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~59\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\);
-
--- Location: LABCELL_X24_Y18_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100110000000000000000000000001100110000110011",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~62\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~63\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\);
-
--- Location: LABCELL_X24_Y18_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~2\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~3\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\);
-
--- Location: LABCELL_X24_Y18_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~66\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~67\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\);
-
--- Location: LABCELL_X24_Y18_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17) & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000010100000101000000000000000001010010110100101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~6\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~7\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\);
-
--- Location: LABCELL_X24_Y18_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~70\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~71\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~17_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\);
-
--- Location: LABCELL_X24_Y18_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010000000000000000000000001010101001010101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~18\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~19\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\);
-
--- Location: LABCELL_X24_Y18_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100000011000000000000000000001100001111000011",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~22\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~23\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\);
-
--- Location: LABCELL_X24_Y18_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~74\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~75\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\);
-
--- Location: FF_X25_Y23_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_OTERM2680\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22));
-
--- Location: LABCELL_X26_Y18_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~62\);
-
--- Location: LABCELL_X25_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_NEW2679\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_OTERM2680\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add9~61_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~61_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_OTERM2680\);
-
--- Location: FF_X25_Y23_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]_OTERM2680\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y18_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~83\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~78\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~79\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~82\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~83\);
-
--- Location: LABCELL_X24_Y18_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add8~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add8~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~83\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~82\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~83\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add8~85_sumout\);
-
--- Location: LABCELL_X24_Y18_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~81_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~77_sumout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~85_sumout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~77_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~85_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~81_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~73_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11_combout\);
-
--- Location: LABCELL_X24_Y19_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~37_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~53_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~49_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~53_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~49_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~41_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~37_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14_combout\);
-
--- Location: LABCELL_X24_Y19_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~25_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~33_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~45_sumout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010100000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~25_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~33_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~45_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~29_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~14_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15_combout\);
-
--- Location: LABCELL_X24_Y18_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~13_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~15_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~1_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~61_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~57_sumout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110000000000100011000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~13_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~61_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~15_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~57_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~1_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13_combout\);
-
--- Location: LABCELL_X24_Y18_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~21_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add8~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~5_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~65_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add8~69_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~13_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~5_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~65_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~69_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~13_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~21_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add8~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0_combout\);
-
--- Location: MLABCELL_X23_Y18_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010101011111010111100000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9_combout\);
-
--- Location: MLABCELL_X28_Y18_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000000000000010100000000000011110101111100001111010111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9_combout\);
-
--- Location: FF_X25_Y20_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]_OTERM2671\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\);
-
--- Location: FF_X25_Y20_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]_OTERM2674\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\);
-
--- Location: LABCELL_X25_Y20_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010010100000000101001010000000000000000101001010000000010100101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[19]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1_combout\);
-
--- Location: LABCELL_X25_Y19_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000000000001111000000001111000000000000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\);
-
--- Location: LABCELL_X25_Y19_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\);
-
--- Location: LABCELL_X26_Y19_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010111100000000101011110000000000000000101011110000000010101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3_combout\);
-
--- Location: MLABCELL_X28_Y18_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001010000001010000101000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\);
-
--- Location: LABCELL_X29_Y21_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110000000000000000001100110000110011000000000000000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\);
-
--- Location: MLABCELL_X28_Y18_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000000000001100000000000011110011111100001111001111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\);
-
--- Location: MLABCELL_X28_Y18_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011000100000000001111110100000000010000000000000011011100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\);
-
--- Location: LABCELL_X32_Y24_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\)))) ) ) )
--- # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000011001100111100001111111101000000010001001101000011011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\);
-
--- Location: MLABCELL_X28_Y18_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000011001111000011001100111100001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\);
-
--- Location: MLABCELL_X28_Y18_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000001010000101000000101000000001010000001010000101000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10_combout\);
-
--- Location: LABCELL_X24_Y21_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010100000000010101010000000011110101111100001111010111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\);
-
--- Location: MLABCELL_X28_Y18_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~13_combout\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111001111111111000000001111001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\);
-
--- Location: FF_X25_Y18_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y18_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001100000000001100110011000000111111001100000011111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\);
-
--- Location: MLABCELL_X28_Y18_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5)) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(5) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000001000000110111001101110011000100110001001111110111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(5),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~15_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\);
-
--- Location: LABCELL_X24_Y19_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(9) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000001010101000000000101001010000000001010101000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(9),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\);
-
--- Location: MLABCELL_X28_Y18_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~14_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001010000010100000100000001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~11_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~10_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~14_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~16_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\);
-
--- Location: MLABCELL_X28_Y18_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~4_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000000000000111100001111000011110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~8_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~17_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18_combout\);
-
--- Location: LABCELL_X25_Y19_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101111100001111010111110000111100000101000000000000010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\);
-
--- Location: LABCELL_X26_Y20_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010101100101011001010110010101100100010001000100010001000100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\);
-
--- Location: LABCELL_X25_Y19_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~0_combout\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~6_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000010101111000000000000101000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\);
-
--- Location: LABCELL_X31_Y22_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010001000000000001000100010101010111011101010101011101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\);
-
--- Location: LABCELL_X31_Y22_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1001000000000000000000001001000010011001000000000000000010011001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2_combout\);
-
--- Location: LABCELL_X26_Y23_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100001100000000110000110000000000000000110000110000000011000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0_combout\);
-
--- Location: LABCELL_X25_Y19_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000000011110000000000000000111100000000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\);
-
--- Location: LABCELL_X32_Y22_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001010101001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\);
-
--- Location: LABCELL_X26_Y21_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111101010101001111110001010100110011000100010000001100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\);
-
--- Location: LABCELL_X29_Y21_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14)) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000111111111100111100111111111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4_combout\);
-
--- Location: FF_X26_Y26_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]_OTERM3266\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\);
-
--- Location: LABCELL_X32_Y24_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111011111110111010101010111010100010001010100010000000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9_combout\);
-
--- Location: LABCELL_X29_Y21_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))) ) )
--- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010111111110010001010111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\);
-
--- Location: LABCELL_X25_Y24_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))) )
--- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000001010000010100000101000001001000001010000010100000101000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(12),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\);
-
--- Location: LABCELL_X31_Y22_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011010000000011011101000000001101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10_combout\);
-
--- Location: LABCELL_X25_Y22_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001111110011001100111111001100000000001100000000000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\);
-
--- Location: LABCELL_X25_Y22_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010010100000000101001010000000000000000101001010000000010100101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\);
-
--- Location: LABCELL_X32_Y24_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(6) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[6]~DUPLICATE_q\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111001101010001111100110101000101010001000000001111001101010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[6]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(6),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(5),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\);
-
--- Location: LABCELL_X32_Y24_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111000011110101111100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\);
-
--- Location: LABCELL_X31_Y22_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111000111010001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\);
-
--- Location: LABCELL_X31_Y22_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001010100011100000101010001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\);
-
--- Location: LABCELL_X31_Y22_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~10_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~9_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000100110001001100110011001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~9_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~10_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\);
-
--- Location: FF_X26_Y23_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]_OTERM3302\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19));
-
--- Location: LABCELL_X26_Y23_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(19) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110011001111000011001100111100000000110011000000000011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(19),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\);
-
--- Location: LABCELL_X25_Y19_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111011100110011011101110011001100010001000000000001000100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(22),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\);
-
--- Location: LABCELL_X26_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(21) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~2_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan1~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011010100000000001101010000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(21),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan1~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\);
-
--- Location: LABCELL_X31_Y22_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~3_combout\ &
--- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan6~4_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111000111110101111101011111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan6~13_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\);
-
--- Location: MLABCELL_X28_Y18_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan7~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~8_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~5_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111000011110011111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~18_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan7~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\);
-
--- Location: FF_X25_Y18_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(3));
-
--- Location: LABCELL_X25_Y18_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) ) + ( !VCC ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) ) + ( !VCC ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(2)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111110000111100000000000000000000111111110000",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\,
- cin => GND,
- sharein => GND,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\);
-
--- Location: LABCELL_X25_Y18_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(3) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(3) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001010101000000000000000001010101001010101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(3),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~34\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~35\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\);
-
--- Location: LABCELL_X25_Y18_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~38\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~39\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\);
-
--- Location: LABCELL_X25_Y18_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010001000100010000000000000000001001100110011001",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~22\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~23\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\);
-
--- Location: LABCELL_X25_Y18_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~42\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~43\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\);
-
--- Location: LABCELL_X25_Y18_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000010100000101000000000000000001010010110100101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(7),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~26\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~27\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\);
-
--- Location: LABCELL_X25_Y18_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(8)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000010100000101000000000000000001010010110100101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(8),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~46\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~47\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\);
-
--- Location: LABCELL_X25_Y18_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~70\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~71\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\);
-
--- Location: LABCELL_X25_Y18_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000010100000101000000000000000001010010110100101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~74\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~75\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\);
-
--- Location: LABCELL_X25_Y18_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[11]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[11]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~78\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~79\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\);
-
--- Location: LABCELL_X25_Y17_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[12]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000010100000101000000000000000001010010110100101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[12]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~82\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~83\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\);
-
--- Location: LABCELL_X25_Y17_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\
--- ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(13)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(13),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~86\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~87\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\);
-
--- Location: LABCELL_X25_Y17_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001010101000000000000000001010101001010101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~6\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~7\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\);
-
--- Location: LABCELL_X25_Y17_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~30\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~31\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\);
-
--- Location: LABCELL_X25_Y17_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010100000101000000000000000000001010010110100101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~10\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~11\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\);
-
--- Location: LABCELL_X25_Y17_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~14\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~15\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\);
-
--- Location: LABCELL_X25_Y17_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~50\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~51\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~17_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\);
-
--- Location: LABCELL_X25_Y17_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010000000000000000000000001010101001010101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~18\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~19\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\);
-
--- Location: LABCELL_X25_Y17_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~54\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~55\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\);
-
--- Location: LABCELL_X25_Y17_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011000000110000000000000000001100001111000011",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~58\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~59\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\);
-
--- Location: LABCELL_X25_Y17_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~67\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(22) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(22),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~62\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~63\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~66\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~67\);
-
--- Location: LABCELL_X25_Y17_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~67\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add0~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001010010110100101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~66\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~67\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\);
-
--- Location: LABCELL_X25_Y18_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~77_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add0~85_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~73_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~81_sumout\
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~69_sumout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010100000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~73_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~81_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~69_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~77_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~85_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\);
-
--- Location: LABCELL_X26_Y17_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370_BDD12371\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~29_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~41_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~45_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~37_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~21_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~45_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~37_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~29_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370_BDD12371\);
-
--- Location: LABCELL_X25_Y17_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_RESYN12370_BDD12371\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~17_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~9_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~33_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~13_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~17_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~9_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~33_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~13_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~25_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_RESYN12370_BDD12371\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\);
-
--- Location: LABCELL_X25_Y17_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000100000000000100010000000000010001000000000001000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~49_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5_combout\);
-
--- Location: LABCELL_X25_Y17_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~53_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~65_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~57_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~61_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\);
-
--- Location: LABCELL_X25_Y18_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010101010101111111111111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\);
-
--- Location: LABCELL_X26_Y18_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add9~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add9~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\);
-
--- Location: LABCELL_X25_Y23_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_NEW2682\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_OTERM2683\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add9~1_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add9~1_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_OTERM2683\);
-
--- Location: FF_X25_Y23_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_OTERM2683\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23));
-
--- Location: LABCELL_X25_Y20_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111111110000000011111111000000001111111100000000111111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\);
-
--- Location: FF_X28_Y22_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]_OTERM1917\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y20_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000001000000000010000000010000100000000100000000001000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(18),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\);
-
--- Location: LABCELL_X26_Y20_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18)))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(19) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(19)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(18))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(20)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100110111111111000000000100110101000100111111110000000001000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(19),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(19),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(18),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(20),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2_combout\);
-
--- Location: LABCELL_X25_Y20_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111110101111111111111010111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\);
-
--- Location: LABCELL_X24_Y20_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111001111110011011100010111000101110001011100010011000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(21),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\);
-
--- Location: LABCELL_X24_Y20_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470_BDD12471\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100111111111111110011111111111100000000110011110000000011001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(8),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470_BDD12471\);
-
--- Location: LABCELL_X24_Y20_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000001100110000000000110000110000000000110011000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\);
-
--- Location: LABCELL_X24_Y20_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_RESYN12470_BDD12471\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001000001001000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_RESYN12470_BDD12471\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\);
-
--- Location: LABCELL_X25_Y20_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(23)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011111111111100001111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(23),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\);
-
--- Location: LABCELL_X24_Y20_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[12]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010100000000000001010000011110000111110101111000011111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[12]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\);
-
--- Location: LABCELL_X24_Y20_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\);
-
--- Location: LABCELL_X29_Y21_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15)) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15)) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000000000000111111110100000011011100000000001111111111011100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(15),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\);
-
--- Location: LABCELL_X24_Y20_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~9_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~11_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~10_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010000000000000000010000000101010000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~10_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\);
-
--- Location: LABCELL_X26_Y20_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7)
--- $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010010110100101000000000000000000000000000000001010010110100101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(7),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(7),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\);
-
--- Location: LABCELL_X26_Y20_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]~DUPLICATE_q\ &
--- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(7)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1101110111011101010001000100010011111111111111110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(7),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\);
-
--- Location: LABCELL_X26_Y20_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_RESYN12688_BDD12689\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(9)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110111111101110101000101010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(9),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(8),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_RESYN12688_BDD12689\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\);
-
--- Location: LABCELL_X26_Y20_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4)) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) &
--- ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[2]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[3]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111000100000000111111110111000100110000000000001111111100110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[2]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\);
-
--- Location: LABCELL_X25_Y20_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~13_combout\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111001100000000000000001111001111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~14_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~16_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\);
-
--- Location: LABCELL_X24_Y20_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(22)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000110000110000000011000000001100000000110000110000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(21),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5_combout\);
-
--- Location: LABCELL_X29_Y21_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[16]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & (
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(15)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011101111111111000000000011101100000010111111110000000000000010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[14]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(15),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[16]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6_combout\);
-
--- Location: LABCELL_X24_Y20_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001010010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\);
-
--- Location: LABCELL_X24_Y20_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690_BDD12691\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~19_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~17_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100000011001000110000001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~19_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~17_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690_BDD12691\);
-
--- Location: LABCELL_X24_Y20_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_RESYN12690_BDD12691\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & (
--- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (!\myVirtualToplevel|MEM_BUSY~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan11~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110100000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan11~4_combout\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_RESYN12690_BDD12691\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\);
-
--- Location: MLABCELL_X28_Y23_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000010000111111111111111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\);
-
--- Location: MLABCELL_X28_Y23_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add15~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(17),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add15~62\);
-
--- Location: MLABCELL_X28_Y23_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_NEW1874\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_OTERM1875\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add15~61_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(17),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~61_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_OTERM1875\);
-
--- Location: FF_X28_Y23_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]_OTERM1875\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(17));
-
--- Location: MLABCELL_X28_Y24_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_NEW1872\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_OTERM1873\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add15~81_sumout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011011000110110001101100011011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add15~81_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_OTERM1873\);
-
--- Location: FF_X28_Y24_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]_OTERM1873\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18));
-
--- Location: FF_X28_Y23_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]_OTERM1877\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\);
-
--- Location: LABCELL_X29_Y24_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110011001100110000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\);
-
--- Location: LABCELL_X29_Y24_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\);
-
--- Location: LABCELL_X29_Y24_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\);
-
--- Location: LABCELL_X29_Y24_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(6) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(6),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\);
-
--- Location: LABCELL_X29_Y24_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\);
-
--- Location: LABCELL_X29_Y24_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\);
-
--- Location: LABCELL_X29_Y24_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\);
-
--- Location: LABCELL_X29_Y24_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\);
-
--- Location: LABCELL_X29_Y24_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(11),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\);
-
--- Location: LABCELL_X29_Y24_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(12) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(12),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\);
-
--- Location: LABCELL_X29_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\);
-
--- Location: LABCELL_X29_Y23_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\);
-
--- Location: LABCELL_X29_Y23_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(15),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\);
-
--- Location: LABCELL_X29_Y23_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[16]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\);
-
--- Location: LABCELL_X29_Y23_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\);
-
--- Location: LABCELL_X29_Y23_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(18) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(18),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\);
-
--- Location: LABCELL_X29_Y23_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\);
-
--- Location: LABCELL_X29_Y23_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~18\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\);
-
--- Location: LABCELL_X29_Y23_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111111101110111000100110001000100110111001100110000000100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~21_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~13_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\);
-
--- Location: LABCELL_X29_Y23_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & \myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010001010100010001000001010001011110011111100110011000011110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~73_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~77_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~25_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\);
-
--- Location: LABCELL_X29_Y23_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~73_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~77_sumout\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000110000110000000011000000001100000000110000110000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~77_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~73_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\);
-
--- Location: LABCELL_X29_Y23_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000111101010000000011110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~81_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~18_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\);
-
--- Location: LABCELL_X29_Y23_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[21]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\);
-
--- Location: LABCELL_X29_Y23_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(22),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~10\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~6\);
-
--- Location: LABCELL_X29_Y23_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add11~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\);
-
--- Location: LABCELL_X29_Y23_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111001111111111001100110111001100010000001100110000000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~9_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~1_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\);
-
--- Location: LABCELL_X29_Y22_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\
--- $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[20]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~21_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010010100000000101001010000000000000000101001010000000010100101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~21_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[20]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\);
-
--- Location: LABCELL_X29_Y22_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_RESYN12704_BDD12705\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~25_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000010100000000111100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~25_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~17_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_RESYN12704_BDD12705\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\);
-
--- Location: LABCELL_X29_Y22_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111111111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\);
-
--- Location: LABCELL_X29_Y22_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[22]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[23]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000011000000000011000000110000110000001100000000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[22]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[23]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~1_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\);
-
--- Location: LABCELL_X29_Y22_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\);
-
--- Location: FF_X25_Y24_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]_OTERM3296\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y28_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011111100110011001111110011001100000011000000000000001100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~69_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~65_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\);
-
--- Location: MLABCELL_X28_Y28_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\
--- & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111010100010000011101010001000011110111010100011111011101010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~33_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~29_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\);
-
--- Location: MLABCELL_X28_Y28_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111010111111111000100001111111100000000011101010000000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~61_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~57_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~53_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\);
-
--- Location: MLABCELL_X28_Y24_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~45_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(2) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100011111100111111101111100000000000000010000100100001101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~45_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\);
-
--- Location: MLABCELL_X28_Y28_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~57_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~61_sumout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000001000000000010000010000000000000000100000100000000001000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[8]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~61_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~57_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~53_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\);
-
--- Location: MLABCELL_X28_Y28_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[6]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~8_combout\ &
--- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~37_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~41_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000101011000000001111111100101011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~37_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[6]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\);
-
--- Location: MLABCELL_X28_Y28_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706_BDD12707\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~69_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000001100110000000000110000110000000000110011000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~69_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~65_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706_BDD12707\);
-
--- Location: MLABCELL_X28_Y28_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_RESYN12706_BDD12707\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~29_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Add11~33_sumout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000010010000011000001001000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~33_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~29_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_RESYN12706_BDD12707\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\);
-
--- Location: LABCELL_X29_Y22_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111111111111111111110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~81_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\);
-
--- Location: MLABCELL_X28_Y28_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~23_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~16_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~24_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100010001000101010101010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~24_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~10_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~23_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~16_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\);
-
--- Location: LABCELL_X29_Y27_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~19_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~2_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000101000000010000011110000111100001010000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~19_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~25_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\);
-
--- Location: LABCELL_X29_Y25_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000000000011001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\);
-
--- Location: LABCELL_X31_Y24_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000001111111100000000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~41_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5_combout\);
-
--- Location: LABCELL_X31_Y24_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~5_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~49_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~45_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~53_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~49_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~45_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~53_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~57_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6_combout\);
-
--- Location: LABCELL_X31_Y24_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~25_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~21_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011000000110000001100000011000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~25_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~21_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5_combout\);
-
--- Location: LABCELL_X31_Y24_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~69_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~85_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~81_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~61_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~65_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000100000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~85_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~81_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~61_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~65_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~69_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7_combout\);
-
--- Location: LABCELL_X31_Y23_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add18~77_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~73_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~77_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~73_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\);
-
--- Location: LABCELL_X26_Y26_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~49_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~45_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\);
-
--- Location: LABCELL_X26_Y25_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(11) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(11),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\);
-
--- Location: LABCELL_X26_Y25_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\);
-
--- Location: LABCELL_X26_Y25_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010101000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[13]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\);
-
--- Location: LABCELL_X26_Y25_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~18\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\);
-
--- Location: LABCELL_X26_Y25_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(15) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(15),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\);
-
--- Location: LABCELL_X26_Y25_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(16) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(16),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\);
-
--- Location: LABCELL_X26_Y25_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\);
-
--- Location: LABCELL_X24_Y25_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_RESYN8423_BDD8424\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~9_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010001100000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_RESYN8423_BDD8424\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\);
-
--- Location: LABCELL_X25_Y31_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010101000000000101010100000000010100000000000001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\);
-
--- Location: LABCELL_X25_Y31_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~5_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~33_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~29_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~8_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111011111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~29_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~33_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\);
-
--- Location: LABCELL_X19_Y37_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010101010100000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\);
-
--- Location: MLABCELL_X18_Y33_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100000000111100000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~0_combout\);
-
--- Location: MLABCELL_X18_Y29_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010011100000101001001110000010100100010000000000010001000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\);
-
--- Location: LABCELL_X16_Y29_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000100000000000000010000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\);
-
--- Location: MLABCELL_X18_Y33_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|state~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|state~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ &
--- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000000001111100010000000111110001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~30_combout\);
-
--- Location: FF_X18_Y33_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|state~30_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\);
-
--- Location: LABCELL_X12_Y35_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\);
-
--- Location: LABCELL_X14_Y32_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ &
--- ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\);
-
--- Location: MLABCELL_X18_Y33_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101001011111000010100101111100001010000010100000101000001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1331~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1352~2_combout\);
-
--- Location: MLABCELL_X18_Y36_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010100000000000001010000010100000101000001010000010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~0_combout\);
-
--- Location: LABCELL_X17_Y29_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000001000000000000000100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\);
-
--- Location: LABCELL_X12_Y35_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ ((((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1001100101011001010000111101011010011000001000000010110000011100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\);
-
--- Location: LABCELL_X31_Y28_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000000000001111000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\);
-
--- Location: MLABCELL_X9_Y15_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\);
-
--- Location: LABCELL_X12_Y16_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\);
-
--- Location: LABCELL_X12_Y16_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~0_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[11]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder_combout\);
-
--- Location: FF_X12_Y16_N34
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\);
-
--- Location: FF_X35_Y21_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2));
-
--- Location: LABCELL_X35_Y21_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr195~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~3_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100111111001100001100000011001111001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr195~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5_combout\);
-
--- Location: FF_X35_Y21_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y29_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000100000000000000010000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\);
-
--- Location: LABCELL_X14_Y29_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111110101111111111111010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\);
-
--- Location: LABCELL_X10_Y16_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder_combout\);
-
--- Location: FF_X10_Y16_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_NEW_REG755\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]_OTERM756\);
-
--- Location: FF_X10_Y32_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Add5~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2));
-
--- Location: FF_X5_Y34_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_NEW_REG1486\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READNOS_OTERM1487\);
-
--- Location: LABCELL_X5_Y35_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~1_combout\);
-
--- Location: LABCELL_X5_Y35_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~2_combout\);
-
--- Location: LABCELL_X19_Y29_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~4_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~4_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001100000000000000110000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\);
-
--- Location: MLABCELL_X13_Y31_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~9_combout\))) )
--- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_RESYN12622_BDD12623\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010100001000000000000101110101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_RESYN12622_BDD12623\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\);
-
--- Location: LABCELL_X17_Y29_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000001100000000000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\);
-
--- Location: MLABCELL_X23_Y35_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263_combout\);
-
--- Location: FF_X23_Y35_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~q\);
-
--- Location: LABCELL_X25_Y17_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~53_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~65_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add0~61_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~57_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~53_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~65_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~61_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~57_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~49_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\);
-
--- Location: LABCELL_X17_Y15_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~2_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add0~1_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal1~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2IncAddr~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010001000100010001010100010001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add0~1_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal1~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2IncAddr~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1_combout\);
-
--- Location: FF_X17_Y15_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_NEW_REG686\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[11]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]_OTERM687\);
-
--- Location: FF_X20_Y39_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1430\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1431\);
-
--- Location: LABCELL_X29_Y31_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add23~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\);
-
--- Location: LABCELL_X29_Y31_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~18\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\);
-
--- Location: LABCELL_X29_Y31_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[2]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[2]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\);
-
--- Location: LABCELL_X29_Y31_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~10\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\);
-
--- Location: LABCELL_X29_Y31_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(4),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add23~6\);
-
--- Location: LABCELL_X29_Y27_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\);
-
--- Location: FF_X24_Y34_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~324_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][0]~q\);
-
--- Location: FF_X10_Y32_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Add5~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y22_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\);
-
--- Location: MLABCELL_X13_Y29_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000100000000001000000000001000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\);
-
--- Location: FF_X31_Y26_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\);
-
--- Location: LABCELL_X16_Y30_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\);
-
--- Location: LABCELL_X16_Y30_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000001000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\);
-
--- Location: MLABCELL_X13_Y25_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110111111111111111111111111111111111111111111111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\);
-
--- Location: MLABCELL_X13_Y29_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001100000000000000000000000000111011000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\);
-
--- Location: MLABCELL_X9_Y36_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010000000000000000010101010101010100000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\);
-
--- Location: LABCELL_X12_Y25_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000100000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\);
-
--- Location: LABCELL_X10_Y22_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489_BDD8490\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011000000111100000000000000001100110011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_RESYN8489_BDD8490\);
-
--- Location: FF_X16_Y30_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]_OTERM2688\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\);
-
--- Location: LABCELL_X16_Y29_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000000100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\);
-
--- Location: LABCELL_X10_Y16_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder_combout\);
-
--- Location: FF_X10_Y16_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y24_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~0_combout\);
-
--- Location: LABCELL_X19_Y24_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000010000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\);
-
--- Location: FF_X26_Y21_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[6]_OTERM1941\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6));
-
--- Location: FF_X26_Y22_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]_OTERM1935\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y22_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000101000001000100010101000101011101111101011101110111111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\);
-
--- Location: LABCELL_X26_Y22_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101011111111000010101111111100001010000010100000101000001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\);
-
--- Location: LABCELL_X26_Y22_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\ ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8775_BDD8776\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_RESYN8777_BDD8778\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110111111101110100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(6),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8775_BDD8776\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_RESYN8777_BDD8778\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_combout\);
-
--- Location: LABCELL_X26_Y22_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(8) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000001000000000000000001000001001000001000000000000000001000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[9]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(8),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\);
-
--- Location: LABCELL_X26_Y22_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000001100110000000000110000110000000000110011000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2_combout\);
-
--- Location: LABCELL_X25_Y22_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(3)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101111101011111010101010101010100000101000001010000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(3),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(2),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\);
-
--- Location: LABCELL_X26_Y22_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(5) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(4))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(5)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111111001111000011111100111100000000000011000000000000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(5),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(5),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\);
-
--- Location: LABCELL_X26_Y22_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(6))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000100100001001000010010000100100001001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(6),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4_combout\);
-
--- Location: LABCELL_X26_Y22_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000010000000000000000001000010000100001000000000000000000100001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\);
-
--- Location: FF_X28_Y22_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]_OTERM1915\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\);
-
--- Location: FF_X28_Y22_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]_OTERM1909\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y22_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\
--- $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000001010101000000000101001010000000001010101000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[22]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\);
-
--- Location: LABCELL_X26_Y22_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9147_BDD9148\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_RESYN9145_BDD9146\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001001000000000000000000001001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9145_BDD9146\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(23),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_RESYN9147_BDD9148\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\);
-
--- Location: MLABCELL_X28_Y21_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(13) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000010100000010100000101000000001010000010100000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(13),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(12),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\);
-
--- Location: MLABCELL_X28_Y21_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000100000000010000000001001000000000100000000010000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\);
-
--- Location: LABCELL_X26_Y21_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001001000000001001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9_combout\);
-
--- Location: FF_X25_Y22_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|pc~137_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add37~85_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~13_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~18_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|pc\(19));
-
--- Location: MLABCELL_X28_Y22_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111011100110011011101110011001100010001000000000001000100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1_combout\);
-
--- Location: MLABCELL_X28_Y22_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\ ) )
--- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[17]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[18]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(17)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101111101011111000011110000111100000101000001010000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(17),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[18]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[17]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2_combout\);
-
--- Location: MLABCELL_X28_Y22_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(20) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[19]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010010100000000101001010000000000000000101001010000000010100101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[19]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15_combout\);
-
--- Location: MLABCELL_X28_Y22_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\))))) ) )
--- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111111100011111010111110000111100000111000000010000010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[22]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\);
-
--- Location: MLABCELL_X28_Y22_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\
--- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(23) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[22]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000001000000001000000001000000001000000001000000001000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[22]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[21]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[23]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(23),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\);
-
--- Location: MLABCELL_X28_Y22_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~1_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~15_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~14_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111000000000000000011001100110000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~15_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~14_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\);
-
--- Location: MLABCELL_X28_Y21_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(12) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[13]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101111100000101010111110000010100001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(12),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[13]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\);
-
--- Location: MLABCELL_X28_Y21_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16) & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[15]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(16)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111010111111111010101010111010100010000010101010000000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(16),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(14),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[15]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\);
-
--- Location: MLABCELL_X28_Y21_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1StartAddr[11]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000011111111001100001111111100000000001100000000000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr\(10),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1StartAddr[11]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\);
-
--- Location: MLABCELL_X28_Y21_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~12_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~11_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111110000000000000000000011111010111100000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~11_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\);
-
--- Location: LABCELL_X26_Y22_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~3_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan14~16_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111111110100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan14~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\);
-
--- Location: LABCELL_X25_Y20_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111001101110011011100110111001100010000000100000001000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[19]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5_combout\);
-
--- Location: LABCELL_X25_Y23_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000001100110000000000110000110000000000110011000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\);
-
--- Location: LABCELL_X25_Y21_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))
--- # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[15]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101111100000101000011110000000011011111000011010100111100000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[15]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(16),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(14),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\);
-
--- Location: LABCELL_X25_Y20_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[17]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[18]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(18) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[19]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000001001000001100000100100000100000000000000001000001001000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[18]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[19]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(18),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[17]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\);
-
--- Location: LABCELL_X25_Y20_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(17)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~13_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111101010101111111110101010111011111010001010101010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(17),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~13_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\);
-
--- Location: FF_X25_Y23_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]_OTERM2683\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\);
-
--- Location: LABCELL_X25_Y23_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[23]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[22]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(21)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010001011111011000000000000000010100010111110111010001011111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[22]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(21),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[23]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\);
-
--- Location: LABCELL_X25_Y20_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8413_BDD8414\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_RESYN8411_BDD8412\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc\(20))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111111001111101011111110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(20),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8413_BDD8414\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_RESYN8411_BDD8412\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\);
-
--- Location: LABCELL_X25_Y23_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000100000010000000001000000001000000000100000010000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(21),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(23),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\);
-
--- Location: LABCELL_X25_Y23_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22)) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(22) & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(23)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111010101010101111101111111010100010000000000000101000101010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(23),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(21),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(22),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\);
-
--- Location: LABCELL_X24_Y24_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19)) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17)))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000000100000101000100010000010111010101110101111101110111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\);
-
--- Location: LABCELL_X24_Y24_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~18_combout\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111110101000000000000000011110101111100000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~14_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~17_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~18_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\);
-
--- Location: LABCELL_X25_Y24_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000001010000101000000101000000001010000001010000101000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\);
-
--- Location: LABCELL_X24_Y24_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[14]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[15]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[16]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000010000000000001000010000000000000000100001000000000000100001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[16]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[15]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[14]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\);
-
--- Location: LABCELL_X24_Y24_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001000010000100001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\);
-
--- Location: LABCELL_X24_Y24_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[20]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[17]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[18]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000001001000001000000000000000000000000000000001000001001000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[18]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[17]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[20]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\);
-
--- Location: LABCELL_X25_Y23_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[22]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[22]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(21)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100001100000000110000110000000000000000110000110000000011000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(21),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[22]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[22]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\);
-
--- Location: LABCELL_X24_Y24_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[23]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8773_BDD8774\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_RESYN8771_BDD8772\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[23]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(19) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(19))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001000001000000000000000001000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8771_BDD8772\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(19),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(19),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[23]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[23]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_RESYN8773_BDD8774\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\);
-
--- Location: LABCELL_X24_Y24_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011111100000011001111110000001100001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(10),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12_combout\);
-
--- Location: LABCELL_X25_Y24_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[12]~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100000001000000010000000100011001110110011101100111011001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[12]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(13),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\);
-
--- Location: LABCELL_X25_Y21_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[14]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(16) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[15]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000000000110011111100110010001100000010001110111111001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[14]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[15]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(16),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(14),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\);
-
--- Location: LABCELL_X24_Y24_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~8_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~12_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111010101010101010101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\);
-
--- Location: MLABCELL_X28_Y24_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9)) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101000001010001010100000001011111111101011111011111110101011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(9),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\);
-
--- Location: LABCELL_X31_Y24_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000010101010111110101010101011111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\);
-
--- Location: MLABCELL_X28_Y24_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8769_BDD8770\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_RESYN8767_BDD8768\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & \myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001110000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8767_BDD8768\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_RESYN8769_BDD8770\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\);
-
--- Location: LABCELL_X29_Y25_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(5) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000001100110000000000110000110000000000110011000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(5),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2_combout\);
-
--- Location: LABCELL_X29_Y25_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000001000001000000000001001000000000001000001000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[7]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\);
-
--- Location: LABCELL_X29_Y25_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010111111111000000001111111100000000010101010000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\);
-
--- Location: LABCELL_X29_Y25_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011111100000011001111110000001100001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\);
-
--- Location: LABCELL_X29_Y25_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000100100000000100110010000000010011001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\);
-
--- Location: LABCELL_X24_Y24_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~4_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~19_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~16_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~13_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010100010100000101010101010000010101000101000001010100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~19_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~13_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\);
-
--- Location: LABCELL_X24_Y21_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100010001100110011101110111100000000100010001100110011101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(11),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\);
-
--- Location: LABCELL_X24_Y21_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(11) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[13]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(12))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000001000001000000000001001000000000001000001000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(11),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[13]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(12),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[11]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\);
-
--- Location: LABCELL_X24_Y23_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~9_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000001100001111000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\);
-
--- Location: MLABCELL_X23_Y23_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[11]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(13) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(11)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101000000000010101010000000000000000101010100000000001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(11),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[11]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\);
-
--- Location: LABCELL_X24_Y23_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_RESYN12618_BDD12619\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(12) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(10) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[10]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011000000001100000000110000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(10),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(12),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[10]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_RESYN12618_BDD12619\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\);
-
--- Location: LABCELL_X24_Y23_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001100000000001100110011110000111111001111000011111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4_combout\);
-
--- Location: LABCELL_X24_Y23_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\
--- & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000100000010000000001000000001000000000100000010000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\);
-
--- Location: LABCELL_X24_Y23_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (((\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(2) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(4) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000000011100011000010001100000000000000000000100000000010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(4),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3_combout\);
-
--- Location: LABCELL_X24_Y23_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[9]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[8]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[8]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100010001010000000001000100010101110111011111010101011101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(9),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[8]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[8]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[9]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\);
-
--- Location: LABCELL_X24_Y23_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\);
-
--- Location: LABCELL_X25_Y26_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[5]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(6) $ (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[6]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000001100110000000000110011110000000011111111000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[5]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(6),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[6]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[5]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\);
-
--- Location: LABCELL_X24_Y23_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~2_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000110011000000000011101100000000001100110000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\);
-
--- Location: LABCELL_X25_Y21_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(14) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(14) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(15) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr\(16) $ (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(16))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000001000001000000000001001000000000001000001000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(14),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(15),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr\(16),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(16),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(14),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\);
-
--- Location: LABCELL_X25_Y23_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~11_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2StartAddr[20]~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000011000000000000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2StartAddr[20]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\);
-
--- Location: LABCELL_X24_Y23_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~8_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan0~6_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010111010101110101011101010111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~10_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan0~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\);
-
--- Location: MLABCELL_X23_Y26_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_BDD8960\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_RESYN13462_BDD13463\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110101011111111111011101111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector993~0_RESYN8959_RESYN13462_BDD13463\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector993~0_RESYN8959_BDD8960\);
-
--- Location: FF_X35_Y21_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y26_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|inBreak~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\);
-
--- Location: MLABCELL_X4_Y26_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2),
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\);
-
--- Location: MLABCELL_X4_Y26_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\);
-
--- Location: LABCELL_X6_Y26_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(2) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(2),
- cin => GND,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~85_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\);
-
--- Location: LABCELL_X6_Y26_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~81_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\);
-
--- Location: FF_X9_Y25_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~38_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(14));
-
--- Location: FF_X9_Y32_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG939\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\);
-
--- Location: FF_X7_Y35_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1001\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\);
-
--- Location: LABCELL_X12_Y31_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010101010000000001010101000000000101010100000000010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\);
-
--- Location: LABCELL_X12_Y31_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\);
-
--- Location: LABCELL_X12_Y31_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\);
-
--- Location: LABCELL_X7_Y33_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011110000000000001111000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\);
-
--- Location: MLABCELL_X13_Y29_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010100000010100101000100010000100011101110110011001101110111001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\);
-
--- Location: MLABCELL_X9_Y33_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\);
-
--- Location: MLABCELL_X9_Y33_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010000010100000101000001010000000000000101000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\);
-
--- Location: LABCELL_X10_Y33_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001010000000000101000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\);
-
--- Location: LABCELL_X12_Y33_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100001000000000001000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\);
-
--- Location: LABCELL_X12_Y31_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000000000000000000011000000110000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\);
-
--- Location: MLABCELL_X9_Y33_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~2_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001010101010100000101000001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\);
-
--- Location: LABCELL_X16_Y33_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $
--- ((((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1001001111000011100000000000000000100001000101000000000111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\);
-
--- Location: LABCELL_X16_Y33_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000100010000000000010001000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\);
-
--- Location: LABCELL_X6_Y33_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\);
-
--- Location: LABCELL_X7_Y33_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0_combout\);
-
--- Location: LABCELL_X12_Y33_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\);
-
--- Location: LABCELL_X7_Y34_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100111111001100110011111100110000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\);
-
--- Location: LABCELL_X7_Y33_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector706~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100011101000111000000000000001101010111010101110101010001010111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19_combout\);
-
--- Location: LABCELL_X6_Y33_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100001111111111110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\);
-
--- Location: LABCELL_X6_Y33_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\);
-
--- Location: LABCELL_X6_Y33_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010000000000000101000000110011010100000011001101010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20_combout\);
-
--- Location: LABCELL_X10_Y26_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000000000000000010000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\);
-
--- Location: LABCELL_X7_Y33_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector706~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~20_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~19_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100100000000000110010000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector706~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~19_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~20_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\);
-
--- Location: LABCELL_X7_Y33_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~18_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001000110010001100100011001000110011001101110011001100110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~18_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~21_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22_combout\);
-
--- Location: FF_X7_Y33_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1005\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~22_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\);
-
--- Location: LABCELL_X6_Y35_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111001100111111111100110001010101000000000101010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\);
-
--- Location: FF_X7_Y35_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1007\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\);
-
--- Location: FF_X7_Y35_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG999\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\);
-
--- Location: FF_X7_Y35_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\);
-
--- Location: LABCELL_X7_Y35_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010000111111111111111100010000000100001011101011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1006\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1008\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1000\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\);
-
--- Location: LABCELL_X14_Y30_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\);
-
--- Location: LABCELL_X6_Y33_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010000000001010101000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\);
-
--- Location: LABCELL_X16_Y32_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001100000000001100110000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\);
-
--- Location: LABCELL_X6_Y33_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111010000000001111101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\);
-
--- Location: LABCELL_X6_Y33_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010000000100000001000000011111000100000001111100010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\);
-
--- Location: LABCELL_X16_Y32_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000000000001100000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\);
-
--- Location: LABCELL_X16_Y32_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\);
-
--- Location: LABCELL_X7_Y33_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000011111111101000001111111110100000101000001010000010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\);
-
--- Location: LABCELL_X6_Y33_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\
--- & \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010101110111000001010000010001000101011101110000010100110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~6_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\);
-
--- Location: LABCELL_X6_Y33_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~14_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011100000111100001110000011000000110000001100000011000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~14_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\);
-
--- Location: LABCELL_X6_Y33_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~13_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001000110010001100110011001000110010001100100011011100110010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~13_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~15_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16_combout\);
-
--- Location: FF_X6_Y33_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1023\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~16_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\);
-
--- Location: LABCELL_X6_Y35_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111100010100001111110001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0_combout\);
-
--- Location: FF_X6_Y35_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1025\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\);
-
--- Location: FF_X7_Y35_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_NEW_REG1021\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\);
-
--- Location: LABCELL_X7_Y35_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000001010101111111111111111100010000010101011011101011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1024\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1026\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE_OTERM1022\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\);
-
--- Location: FF_X9_Y32_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y36_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111100000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\);
-
--- Location: LABCELL_X12_Y35_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\);
-
--- Location: LABCELL_X16_Y34_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\);
-
--- Location: LABCELL_X7_Y34_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000000000000010000000000000001010101000000000101010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0_combout\);
-
--- Location: LABCELL_X7_Y34_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000110111000001000011011100000100000001000000010000000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\);
-
--- Location: LABCELL_X12_Y31_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010000000000000000000000000000000010000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\);
-
--- Location: LABCELL_X7_Y34_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010011001111010001001100111100000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\);
-
--- Location: LABCELL_X7_Y34_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector640~1_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector640~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110000000000000000000000000011110000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector640~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\);
-
--- Location: LABCELL_X7_Y34_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100000010000000000000001000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5_combout\);
-
--- Location: FF_X7_Y34_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1128\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\);
-
--- Location: LABCELL_X6_Y35_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110011111100111111001111110000000000111100000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\);
-
--- Location: FF_X7_Y34_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1126\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\);
-
--- Location: FF_X7_Y34_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1122\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\);
-
--- Location: MLABCELL_X9_Y33_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\
--- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101000000010001000100000101010101010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1_combout\);
-
--- Location: FF_X9_Y33_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_NEW_REG1124\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\);
-
--- Location: LABCELL_X7_Y34_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100010001111111111011111101010101010101011111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1129\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1127\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1123\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE_OTERM1125\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\);
-
--- Location: LABCELL_X12_Y32_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\);
-
--- Location: LABCELL_X5_Y33_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111110000111111111111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4_combout\);
-
--- Location: FF_X5_Y33_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG959\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\);
-
--- Location: MLABCELL_X9_Y36_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111111111111111011111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\);
-
--- Location: LABCELL_X5_Y33_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\);
-
--- Location: LABCELL_X5_Y33_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111110101111111111111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8_combout\);
-
--- Location: FF_X5_Y33_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG963\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\);
-
--- Location: LABCELL_X14_Y32_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\);
-
--- Location: LABCELL_X7_Y33_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010101000000000001010100000000000101111000011110010111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7_combout\);
-
--- Location: MLABCELL_X13_Y30_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000100001000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\);
-
--- Location: LABCELL_X7_Y33_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001101010101000000110101010100000011000000000000001100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\);
-
--- Location: LABCELL_X7_Y33_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000000000000001000000000000000110000001100000011000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\);
-
--- Location: LABCELL_X7_Y33_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~5_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~7_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101000000000000000000000000010101010000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6_combout\);
-
--- Location: LABCELL_X7_Y33_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011001111111111111100111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7_combout\);
-
--- Location: FF_X7_Y33_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG961\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\);
-
--- Location: FF_X9_Y33_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG955\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\);
-
--- Location: LABCELL_X7_Y33_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3_combout\);
-
--- Location: FF_X7_Y33_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG957\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\);
-
--- Location: LABCELL_X5_Y33_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000001010000010111111111111111011111111111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967_combout\);
-
--- Location: FF_X5_Y33_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_NEW_REG965\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~3_RTM0967_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\);
-
--- Location: LABCELL_X5_Y33_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010111011101110111111101111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM960\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM964\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM962\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM966\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\);
-
--- Location: LABCELL_X7_Y35_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)))
--- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~6_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITE~1_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100100011010001010110011110001001101010111100110111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITE~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\);
-
--- Location: LABCELL_X17_Y35_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\);
-
--- Location: LABCELL_X5_Y33_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101011111010101010101111101010100000111100001010000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\);
-
--- Location: LABCELL_X5_Y33_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010000010101010101000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7_combout\);
-
--- Location: FF_X5_Y33_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1045\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\);
-
--- Location: LABCELL_X10_Y36_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\);
-
--- Location: LABCELL_X5_Y33_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111110000111111111111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2_combout\);
-
--- Location: FF_X5_Y33_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1041\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\);
-
--- Location: LABCELL_X14_Y32_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\);
-
--- Location: LABCELL_X5_Y33_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000000000000010000000000000001000100010001000100010001000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0_combout\);
-
--- Location: LABCELL_X16_Y32_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000000010000100000000001000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\);
-
--- Location: MLABCELL_X13_Y32_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\);
-
--- Location: LABCELL_X5_Y33_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000000000001010000000000100111001000100010011100100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\);
-
--- Location: LABCELL_X5_Y33_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001111000000000000111110101010101011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\);
-
--- Location: LABCELL_X5_Y33_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector904~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector904~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110000000000000111000000000000011000000000000001100000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector904~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5_combout\);
-
--- Location: LABCELL_X5_Y33_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011001111111111111100111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6_combout\);
-
--- Location: FF_X5_Y33_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1043\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\);
-
--- Location: LABCELL_X5_Y33_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000001010000010111111111101111111111111110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049_combout\);
-
--- Location: FF_X5_Y33_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_NEW_REG1047\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~1_RTM01049_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\);
-
--- Location: LABCELL_X5_Y33_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011011101110111011111110111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1046\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1042\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1044\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM956\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE_OTERM958\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE_OTERM1048\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\);
-
--- Location: LABCELL_X16_Y31_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\);
-
--- Location: LABCELL_X16_Y31_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\);
-
--- Location: LABCELL_X6_Y35_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\)
--- # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100111011101110111010001000100010001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\);
-
--- Location: FF_X6_Y35_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1150\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\);
-
--- Location: LABCELL_X14_Y32_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\);
-
--- Location: LABCELL_X6_Y33_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010000000001010101000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\);
-
--- Location: LABCELL_X6_Y33_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\);
-
--- Location: LABCELL_X12_Y29_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000010000000000000000000000000000000010000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\);
-
--- Location: LABCELL_X6_Y33_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000000000000110000000001010011010100000101001101010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\);
-
--- Location: LABCELL_X6_Y33_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100111111001100110011111100110000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\);
-
--- Location: LABCELL_X6_Y33_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011111100000100000001000000010000111111001101110011011100110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\);
-
--- Location: LABCELL_X6_Y33_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector772~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~3_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000010000000000000001000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector772~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[18]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\);
-
--- Location: LABCELL_X6_Y33_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~2_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001010000011110000101000001111000111110000111100011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6_combout\);
-
--- Location: FF_X6_Y33_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1148\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\);
-
--- Location: FF_X7_Y35_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_NEW_REG1003\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\);
-
--- Location: FF_X7_Y35_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_NEW_REG1146\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\);
-
--- Location: LABCELL_X7_Y35_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111101110100110000001100001111111111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1151\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1149\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE_OTERM1147\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1002\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\);
-
--- Location: LABCELL_X14_Y32_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\);
-
--- Location: LABCELL_X7_Y34_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011000000000000001100000000000000111011100000000011101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0_combout\);
-
--- Location: LABCELL_X7_Y34_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001101010101000000110101010100000011000000000000001100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\);
-
--- Location: LABCELL_X7_Y34_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000011010000000100001101000000010001110100010001000111010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\);
-
--- Location: LABCELL_X12_Y26_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001000000000000000000000000000000000100000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\);
-
--- Location: LABCELL_X7_Y34_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector838~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector838~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101000000000101010100000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector838~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[26]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\);
-
--- Location: LABCELL_X7_Y34_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100000000001000000000000000100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4_combout\);
-
--- Location: FF_X7_Y34_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1166\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\);
-
--- Location: MLABCELL_X9_Y33_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\)
--- # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101000000010001000100000101010101010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0_combout\);
-
--- Location: FF_X9_Y33_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1162\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\);
-
--- Location: LABCELL_X6_Y35_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000000000011001111110000111111111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\);
-
--- Location: FF_X7_Y34_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1164\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\);
-
--- Location: FF_X7_Y34_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_NEW_REG1160\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\);
-
--- Location: LABCELL_X7_Y34_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & (
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000011100000111111111111111111100000111000001111111111111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1167\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1163\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1165\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE_OTERM1161\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE_OTERM1004~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\);
-
--- Location: LABCELL_X14_Y30_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\);
-
--- Location: LABCELL_X10_Y37_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\
--- & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITE~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111001100111111111100110100000000000000000000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITE~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2_combout\);
-
--- Location: FF_X10_Y37_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1031\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\);
-
--- Location: LABCELL_X5_Y35_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101011111010111110101111101000000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\);
-
--- Location: LABCELL_X10_Y37_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100010001000100010001000111111011111110111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039_combout\);
-
--- Location: FF_X10_Y37_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1037\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~1_RTM01039_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\);
-
--- Location: FF_X10_Y37_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1027\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\);
-
--- Location: LABCELL_X7_Y33_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~5_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010000000100000001000000010000110111000001000011011100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4_combout\);
-
--- Location: LABCELL_X14_Y30_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000010000000000000000000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\);
-
--- Location: LABCELL_X7_Y33_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector574~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))))) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010000000000010101000000000001010111000000000101011100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector574~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1_combout\);
-
--- Location: LABCELL_X7_Y33_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010000000000000001000000000000000110011000000000011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\);
-
--- Location: LABCELL_X7_Y33_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector970~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector508~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector970~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000101010101000000010101010101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector970~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3_combout\);
-
--- Location: LABCELL_X7_Y33_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~3_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector508~4_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1011000011110000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector508~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5_combout\);
-
--- Location: FF_X7_Y33_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1033\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\);
-
--- Location: LABCELL_X10_Y37_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~q\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111100111111001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6_combout\);
-
--- Location: FF_X10_Y37_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1035\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\);
-
--- Location: FF_X19_Y39_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_NEW_REG1029\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\);
-
--- Location: LABCELL_X10_Y37_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000100010001100110011001100100011001000100011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1032\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1038\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1028\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1034\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1036\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE_OTERM1030\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\);
-
--- Location: LABCELL_X7_Y35_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~5_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~8_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110001000100001111110100010000001100011101110011111101110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~8_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\);
-
--- Location: MLABCELL_X9_Y15_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000001111000011111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\);
-
--- Location: FF_X10_Y35_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG941\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\);
-
--- Location: MLABCELL_X18_Y38_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Init~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Init~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\);
-
--- Location: LABCELL_X14_Y36_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111010000000000000000000000000011111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_RESYN8779_BDD8780\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\);
-
--- Location: FF_X12_Y35_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG943\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\);
-
--- Location: LABCELL_X6_Y35_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110111000000000111011100000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\);
-
--- Location: FF_X6_Y35_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1095\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\);
-
--- Location: FF_X9_Y35_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1093\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\);
-
--- Location: LABCELL_X16_Y32_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100000000000000001000100000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\);
-
--- Location: LABCELL_X16_Y32_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\);
-
--- Location: LABCELL_X14_Y33_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101000110010111110100011001000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\);
-
--- Location: LABCELL_X12_Y31_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\);
-
--- Location: MLABCELL_X13_Y33_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111101010101010100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\);
-
--- Location: LABCELL_X14_Y35_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\);
-
--- Location: LABCELL_X10_Y33_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\);
-
--- Location: MLABCELL_X13_Y35_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000111100110000000011110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\);
-
--- Location: LABCELL_X14_Y35_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\))))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\)))) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010001001111010001000100111100000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2_combout\);
-
--- Location: LABCELL_X14_Y35_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111110101111111111111010111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\);
-
--- Location: LABCELL_X16_Y32_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\);
-
--- Location: LABCELL_X16_Y32_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~24_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010000000100000001000000110011000100000011001100010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~24_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\);
-
--- Location: LABCELL_X16_Y33_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\);
-
--- Location: LABCELL_X10_Y35_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000111100000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\);
-
--- Location: LABCELL_X14_Y35_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector769~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001101000000001100110100000000110011110000000011001101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\);
-
--- Location: FF_X14_Y35_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1097\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\);
-
--- Location: MLABCELL_X9_Y35_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\))) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\) ) )
--- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001100000000001100110001010101111111010000000011111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1096\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1094\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1098\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\);
-
--- Location: LABCELL_X14_Y32_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000001100110000000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\);
-
--- Location: MLABCELL_X9_Y35_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101011111000000000000111100000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2_combout\);
-
--- Location: MLABCELL_X9_Y35_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111110101111111111111010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\);
-
--- Location: MLABCELL_X13_Y37_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011100000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\);
-
--- Location: LABCELL_X10_Y35_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\);
-
--- Location: MLABCELL_X13_Y34_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\);
-
--- Location: LABCELL_X14_Y32_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000000000000100000000000000000001000000000000000100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\);
-
--- Location: MLABCELL_X13_Y34_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010101000101000001010100010100000000010001000000000001000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~30_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\);
-
--- Location: LABCELL_X10_Y35_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector967~3_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000001110000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\);
-
--- Location: FF_X10_Y35_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG951\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\);
-
--- Location: LABCELL_X10_Y35_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010100010101000101010001010100010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\);
-
--- Location: FF_X9_Y35_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG953\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\);
-
--- Location: FF_X9_Y35_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG949\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\);
-
--- Location: MLABCELL_X9_Y35_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110011001100110000001010000010101111111111001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM952\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM954\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR_OTERM950\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\);
-
--- Location: FF_X9_Y35_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1057\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\);
-
--- Location: MLABCELL_X13_Y32_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\);
-
--- Location: MLABCELL_X9_Y35_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\))))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001110011010100000111001100000000001100110000000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2_combout\);
-
--- Location: MLABCELL_X9_Y35_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101011111111111110101111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\);
-
--- Location: MLABCELL_X13_Y32_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\);
-
--- Location: LABCELL_X16_Y35_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001001100010001000100110001000100000011000000000000001100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\);
-
--- Location: LABCELL_X14_Y37_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010101000000000101010100000000010001010000000001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\);
-
--- Location: MLABCELL_X9_Y35_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\);
-
--- Location: MLABCELL_X9_Y35_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector901~3_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010000010100000101000001011000011110000101100001011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\);
-
--- Location: FF_X9_Y35_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1061\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\);
-
--- Location: MLABCELL_X9_Y35_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110111111101111111011111110111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\);
-
--- Location: FF_X9_Y35_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1059\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\);
-
--- Location: MLABCELL_X9_Y35_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\) ) ) )
--- # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010001000100010001000100010001010101111101010100010011110100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1058\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1062\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1060\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\);
-
--- Location: MLABCELL_X9_Y35_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111100111111111111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\);
-
--- Location: FF_X9_Y35_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1017\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\);
-
--- Location: LABCELL_X14_Y37_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000001010000010100000100000001010000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\);
-
--- Location: LABCELL_X10_Y35_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1_combout\);
-
--- Location: LABCELL_X16_Y32_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000000000000001000000000000000000000001000000000000000100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\);
-
--- Location: MLABCELL_X13_Y37_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000101000000000100010101010101010101010000000001000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\);
-
--- Location: LABCELL_X16_Y31_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\);
-
--- Location: MLABCELL_X13_Y35_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000000000000010100000000000111011001100110011101100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2_combout\);
-
--- Location: LABCELL_X10_Y35_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111001111111111111100111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\);
-
--- Location: LABCELL_X10_Y35_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~1_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111110001001100010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4_combout\);
-
--- Location: FF_X10_Y35_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1019\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector835~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\);
-
--- Location: FF_X9_Y35_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1015\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\);
-
--- Location: MLABCELL_X9_Y35_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\)) ) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)))) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010101000000000000000011001100111111011100110011111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1018\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1020\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1016\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\);
-
--- Location: LABCELL_X7_Y35_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)
--- & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)
--- & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010000000011010001001100111101110111000000110111011111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~0_combout\);
-
--- Location: LABCELL_X10_Y35_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000010100001111000001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\);
-
--- Location: FF_X10_Y35_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG973\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\);
-
--- Location: FF_X10_Y35_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG971\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\);
-
--- Location: MLABCELL_X13_Y31_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\);
-
--- Location: LABCELL_X14_Y35_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011011100000101001101110000010100000101000001010000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2_combout\);
-
--- Location: LABCELL_X14_Y35_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111001111111111111100111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\);
-
--- Location: LABCELL_X16_Y32_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111101100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\);
-
--- Location: LABCELL_X14_Y35_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\);
-
--- Location: LABCELL_X16_Y32_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) $ (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100000000100000010000000010000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\);
-
--- Location: LABCELL_X17_Y34_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\);
-
--- Location: LABCELL_X17_Y34_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001100000000000000110000001010000011100000101000001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~36_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\);
-
--- Location: LABCELL_X14_Y35_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\
--- & \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector703~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100000001001100110000000100110011000000110011001100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\);
-
--- Location: FF_X14_Y35_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG975\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\);
-
--- Location: LABCELL_X10_Y35_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\)
--- ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011101010101111101100000000000000001010101011111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM974\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM972\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR_OTERM976\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\);
-
--- Location: LABCELL_X6_Y35_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000110000001110101111101011111010111110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\);
-
--- Location: LABCELL_X6_Y35_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001100000011110000110000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\);
-
--- Location: FF_X10_Y35_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1011\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~2_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\);
-
--- Location: FF_X10_Y35_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1009\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\);
-
--- Location: MLABCELL_X13_Y30_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\);
-
--- Location: LABCELL_X14_Y32_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100000001000000000000000010000000100000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\);
-
--- Location: MLABCELL_X13_Y34_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010100000101000001010101000000000101010101010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~32_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\);
-
--- Location: MLABCELL_X9_Y32_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\);
-
--- Location: LABCELL_X10_Y35_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000111110001000100011111000100010001000100010001000100010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7_combout\);
-
--- Location: LABCELL_X10_Y35_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101011111111111110101111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\);
-
--- Location: LABCELL_X12_Y33_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\);
-
--- Location: LABCELL_X10_Y35_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\);
-
--- Location: LABCELL_X10_Y35_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~8_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000001000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3_combout\);
-
--- Location: FF_X10_Y35_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1013\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\);
-
--- Location: LABCELL_X10_Y35_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\)) ) ) ) #
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\)))) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011101110111010101100000000000000001011101110101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1012\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1010\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1014\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~4_combout\);
-
--- Location: LABCELL_X12_Y31_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\);
-
--- Location: LABCELL_X12_Y35_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~9_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~9_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\);
-
--- Location: LABCELL_X12_Y35_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1011101010111011111110101111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\);
-
--- Location: LABCELL_X16_Y32_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000000001000010000000000100000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\);
-
--- Location: LABCELL_X16_Y32_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\);
-
--- Location: LABCELL_X16_Y34_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100000000000100010000000001010001010100000101000101010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\);
-
--- Location: LABCELL_X16_Y35_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010101000000000001010100000000010101010000000001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\);
-
--- Location: LABCELL_X12_Y35_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\);
-
--- Location: LABCELL_X12_Y35_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~3_combout\)
--- ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000100010001000100010001000100011001000110011001100100011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4_combout\);
-
--- Location: FF_X12_Y35_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1067\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\);
-
--- Location: FF_X7_Y35_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_NEW_REG1063\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\);
-
--- Location: LABCELL_X6_Y35_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111110011111100111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\);
-
--- Location: FF_X7_Y35_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\);
-
--- Location: LABCELL_X7_Y35_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\))
--- ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000100111100001111111100000000010001001111000011110100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1068\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1064\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR_OTERM1066~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\);
-
--- Location: LABCELL_X16_Y10_N3
-\myVirtualToplevel|SD_DATA_WRITE[7]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_DATA_WRITE[7]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SD_CS~combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000010100000000000001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ALT_INV_SD_CS~combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- combout => \myVirtualToplevel|SD_DATA_WRITE[7]~1_combout\);
-
--- Location: LABCELL_X10_Y15_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux87~2_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux87~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder_combout\);
-
--- Location: LABCELL_X12_Y17_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\);
-
--- Location: LABCELL_X10_Y18_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\);
-
--- Location: LABCELL_X10_Y18_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ &
--- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (\myVirtualToplevel|RESET_n~q\ & !\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\);
-
--- Location: FF_X10_Y15_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~feeder_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0));
-
--- Location: LABCELL_X12_Y25_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\);
-
--- Location: LABCELL_X12_Y26_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|divComplete~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001000000010000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\,
- datae => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divComplete~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\);
-
--- Location: LABCELL_X12_Y25_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000000000000010000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\);
-
--- Location: LABCELL_X12_Y25_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100001111000001010000111100000101000000000000010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\);
-
--- Location: LABCELL_X10_Y22_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\
--- & (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\))) ) )
--- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~3_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100010011000100010001001100010011000100110001000100010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\);
-
--- Location: LABCELL_X29_Y26_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000100000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\);
-
--- Location: LABCELL_X29_Y26_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1_combout\);
-
--- Location: LABCELL_X29_Y26_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000001000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~8_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\);
-
--- Location: LABCELL_X31_Y28_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ ) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\);
-
--- Location: LABCELL_X25_Y32_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a1\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001111111111111101100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a1\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][1]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297_combout\);
-
--- Location: FF_X25_Y32_N22
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~297_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][1]~q\);
-
--- Location: LABCELL_X10_Y16_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000000000000000000110011001100110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\);
-
--- Location: MLABCELL_X28_Y6_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ = ( !\myVirtualToplevel|SD_RESET\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\);
-
--- Location: MLABCELL_X23_Y5_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & !\myVirtualToplevel|SD_HNDSHK_IN\(0))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\
--- & !\myVirtualToplevel|SD_HNDSHK_IN\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000011000000110000001100000001000000010000000100000001000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\);
-
--- Location: MLABCELL_X28_Y5_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~1_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\)))
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101000000000111110100000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~1_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\);
-
--- Location: IOIBUF_X40_Y0_N41
-\SDCARD_MISO[0]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => ww_SDCARD_MISO(0),
- o => \SDCARD_MISO[0]~input_o\);
-
--- Location: FF_X24_Y7_N23
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\);
-
--- Location: LABCELL_X24_Y7_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SD_HNDSHK_IN\(0) &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111110000001111111111000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\);
-
--- Location: LABCELL_X24_Y7_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ = ( !\myVirtualToplevel|SD_RESET\(0) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~q\ &
--- !\myVirtualToplevel|SD_HNDSHK_IN\(0))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110111011001100111011101100110000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0),
- dataf => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\);
-
--- Location: LABCELL_X25_Y7_N45
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\);
-
--- Location: FF_X23_Y5_N26
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\,
- asdata => VCC,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(0));
-
--- Location: MLABCELL_X23_Y5_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100110011001100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(0),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\);
-
--- Location: MLABCELL_X28_Y5_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ &
--- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(0))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector21~0_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010111010000100001011101000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector21~0_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6_combout\);
-
--- Location: FF_X28_Y5_N26
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(0));
-
--- Location: MLABCELL_X28_Y5_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(0),
- cin => GND,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\);
-
--- Location: MLABCELL_X28_Y5_N33
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(1),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~14\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\);
-
--- Location: MLABCELL_X28_Y5_N27
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~25_sumout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~25_sumout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9_combout\);
-
--- Location: FF_X28_Y5_N29
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v~9_combout\,
- sclr => \myVirtualToplevel|SD_RESET\(0),
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(1));
-
--- Location: MLABCELL_X28_Y5_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(2),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~26\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\);
-
--- Location: MLABCELL_X23_Y5_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(2)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011101110110011001110111011001100111011101100110011101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(2),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0_combout\);
-
--- Location: FF_X23_Y5_N1
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector20~0_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(2));
-
--- Location: MLABCELL_X28_Y5_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(2) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\)) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~17_sumout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010101000000000101010100000000111100000000000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~17_sumout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(2),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7_combout\);
-
--- Location: FF_X28_Y5_N14
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[2]~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(2));
-
--- Location: MLABCELL_X28_Y5_N39
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(3),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~18\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\);
-
--- Location: MLABCELL_X23_Y5_N51
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011111111111100001111111111110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(3),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0_combout\);
-
--- Location: FF_X23_Y5_N53
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector19~0_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3));
-
--- Location: MLABCELL_X28_Y5_N9
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3) & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~1_sumout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(3) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000000000001100100010001000010001000000000011001100100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~1_sumout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(3),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3_combout\);
-
--- Location: FF_X28_Y5_N11
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[3]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(3));
-
--- Location: MLABCELL_X28_Y5_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(4),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~2\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\);
-
--- Location: MLABCELL_X23_Y5_N3
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011101110110011001110111011001100111011101100110011101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(4),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0_combout\);
-
--- Location: FF_X23_Y5_N5
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector18~0_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4));
-
--- Location: MLABCELL_X28_Y5_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4) & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~21_sumout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(4) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000000000001100100010001000010000000100000011001000110010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~21_sumout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(4),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8_combout\);
-
--- Location: FF_X28_Y5_N2
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[4]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(4));
-
--- Location: MLABCELL_X28_Y5_N54
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(0) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(2) &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(1) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(4))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(2),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(1),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(4),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(0),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\);
-
--- Location: LABCELL_X26_Y6_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\ = ( \SDCARD_MISO[0]~input_o\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\) ) ) # (
--- !\SDCARD_MISO[0]~input_o\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001001100010011000100110001001100000011000000110000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- dataf => \ALT_INV_SDCARD_MISO[0]~input_o\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\);
-
--- Location: LABCELL_X26_Y6_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\
--- & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111000000000000000011111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6_combout\);
-
--- Location: FF_X26_Y6_N20
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[1]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1));
-
--- Location: LABCELL_X26_Y6_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\
--- & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111000000000000000011111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5_combout\);
-
--- Location: FF_X26_Y6_N50
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[2]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2));
-
--- Location: LABCELL_X26_Y6_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\
--- & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111000000000000000011111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2_combout\);
-
--- Location: FF_X26_Y6_N8
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[3]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3));
-
--- Location: LABCELL_X26_Y6_N9
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111000000000000000011111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7_combout\);
-
--- Location: FF_X26_Y6_N11
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[4]~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4));
-
--- Location: LABCELL_X26_Y6_N51
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111000000000000000011111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3_combout\);
-
--- Location: FF_X26_Y6_N53
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[5]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5));
-
--- Location: LABCELL_X26_Y6_N21
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6) & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111000000000000000011111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4_combout\);
-
--- Location: FF_X26_Y6_N23
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[6]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6));
-
--- Location: LABCELL_X26_Y6_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~1_combout\))) ) )
--- ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000011111111111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v[0]~1_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(7),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8_combout\);
-
--- Location: FF_X26_Y6_N26
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[7]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7));
-
--- Location: LABCELL_X26_Y6_N39
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000001000000010000000100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(7),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0_combout\);
-
--- Location: LABCELL_X26_Y6_N57
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000001000000010000000100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\);
-
--- Location: LABCELL_X26_Y7_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0),
- cin => GND,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\);
-
--- Location: FF_X21_Y10_N44
-\myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector16~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\);
-
--- Location: LABCELL_X20_Y10_N39
-\myVirtualToplevel|Selector14~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector14~0_combout\ = (\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\) #
--- (\myVirtualToplevel|SD_DATA_REQ~q\))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000101000000000100010100000000010001010000000001000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\,
- combout => \myVirtualToplevel|Selector14~0_combout\);
-
--- Location: LABCELL_X20_Y10_N12
-\myVirtualToplevel|Selector15~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector15~8_combout\ = ( !\myVirtualToplevel|SD_DATA_REQ~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & (((!\myVirtualToplevel|Selector15~2_combout\ &
--- \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\)) # (\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\)))) ) ) # ( \myVirtualToplevel|SD_DATA_REQ~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & (!\myVirtualToplevel|Selector15~2_combout\ & \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "on",
- lut_mask => "0000001000000010000000000000000000100010000000100000001000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\,
- datad => \myVirtualToplevel|ALT_INV_Selector15~2_combout\,
- datae => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\,
- datag => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\,
- combout => \myVirtualToplevel|Selector15~8_combout\);
-
--- Location: FF_X20_Y10_N14
-\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector15~8_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\);
-
--- Location: LABCELL_X20_Y10_N30
-\myVirtualToplevel|Selector14~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector14~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\)) # (\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100111111001100110011111100000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- combout => \myVirtualToplevel|Selector14~1_combout\);
-
--- Location: LABCELL_X20_Y10_N48
-\myVirtualToplevel|Selector14~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector14~2_combout\ = ( \myVirtualToplevel|Selector14~1_combout\ & ( !\myVirtualToplevel|Selector17~0_combout\ ) ) # ( !\myVirtualToplevel|Selector14~1_combout\ & ( (!\myVirtualToplevel|Selector17~0_combout\ &
--- (!\myVirtualToplevel|Selector15~2_combout\ & \myVirtualToplevel|Selector14~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010001000000000001000100010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Selector17~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_Selector15~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_Selector14~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Selector14~1_combout\,
- combout => \myVirtualToplevel|Selector14~2_combout\);
-
--- Location: FF_X20_Y10_N49
-\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector14~2_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\);
-
--- Location: FF_X20_Y10_N7
-\myVirtualToplevel|SD_STATE.SD_STATE_READ_2\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector18~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~q\);
-
--- Location: FF_X21_Y10_N38
-\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector13~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\);
-
--- Location: LABCELL_X20_Y10_N0
-\myVirtualToplevel|Selector15~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector15~0_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & !\myVirtualToplevel|SD_DATA_REQ~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000110011000000000011001100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\,
- combout => \myVirtualToplevel|Selector15~0_combout\);
-
--- Location: LABCELL_X21_Y10_N12
-\myVirtualToplevel|Selector15~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector15~6_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & (!\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & !\myVirtualToplevel|Selector15~0_combout\)) )
--- ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & (!\myVirtualToplevel|Selector15~0_combout\ & ((!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100010000000000110001000000000001000100000000000100010000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\,
- datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\,
- datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_Selector15~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~DUPLICATE_q\,
- combout => \myVirtualToplevel|Selector15~6_combout\);
-
--- Location: LABCELL_X21_Y10_N45
-\myVirtualToplevel|Selector11~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector11~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( (!\myVirtualToplevel|Selector11~1_combout\) # ((!\myVirtualToplevel|Selector15~2_combout\) # (\myVirtualToplevel|Selector15~5_combout\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111101011111111111110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Selector11~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_Selector15~5_combout\,
- datad => \myVirtualToplevel|ALT_INV_Selector15~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- combout => \myVirtualToplevel|Selector11~2_combout\);
-
--- Location: FF_X21_Y10_N47
-\myVirtualToplevel|SD_STATE.SD_STATE_RESET\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector11~2_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\);
-
--- Location: LABCELL_X21_Y10_N9
-\myVirtualToplevel|Selector12~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector12~1_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\ & ( (!\myVirtualToplevel|Equal8~1_combout\ & (!\myVirtualToplevel|Selector12~0_combout\ &
--- !\myVirtualToplevel|Selector15~2_combout\)) ) ) ) # ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( !\myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\ & ( !\myVirtualToplevel|Selector12~0_combout\ ) ) ) # (
--- !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( !\myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\ & ( !\myVirtualToplevel|Selector12~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110000000000000000001000000010000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\,
- datab => \myVirtualToplevel|ALT_INV_Selector12~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_Selector15~2_combout\,
- datae => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~q\,
- combout => \myVirtualToplevel|Selector12~1_combout\);
-
--- Location: FF_X21_Y10_N11
-\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector12~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\);
-
--- Location: LABCELL_X24_Y10_N57
-\myVirtualToplevel|SD_RESET_TIMER~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_RESET_TIMER~5_combout\ = ( !\myVirtualToplevel|SD_RESET_TIMER\(0) & ( !\myVirtualToplevel|Equal8~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010000000000000000010101010101010100000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(0),
- combout => \myVirtualToplevel|SD_RESET_TIMER~5_combout\);
-
--- Location: FF_X21_Y10_N46
-\myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector11~2_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y10_N33
-\myVirtualToplevel|Selector3~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector3~0_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ & ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~DUPLICATE_q\,
- combout => \myVirtualToplevel|Selector3~0_combout\);
-
--- Location: FF_X24_Y10_N59
-\myVirtualToplevel|SD_RESET_TIMER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_RESET_TIMER~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- ena => \myVirtualToplevel|Selector3~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_RESET_TIMER\(0));
-
--- Location: LABCELL_X24_Y10_N0
-\myVirtualToplevel|Add0~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add0~26\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(0),
- cin => GND,
- cout => \myVirtualToplevel|Add0~26\);
-
--- Location: LABCELL_X24_Y10_N3
-\myVirtualToplevel|Add0~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add0~17_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add0~26\ ))
--- \myVirtualToplevel|Add0~18\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add0~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(1),
- cin => \myVirtualToplevel|Add0~26\,
- sumout => \myVirtualToplevel|Add0~17_sumout\,
- cout => \myVirtualToplevel|Add0~18\);
-
--- Location: LABCELL_X24_Y10_N30
-\myVirtualToplevel|Selector8~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector8~0_combout\ = (!\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\) # (\myVirtualToplevel|Add0~17_sumout\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100111111001111110011111100111111001111110011111100111111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- datac => \myVirtualToplevel|ALT_INV_Add0~17_sumout\,
- combout => \myVirtualToplevel|Selector8~0_combout\);
-
--- Location: LABCELL_X24_Y10_N39
-\myVirtualToplevel|SD_RESET_TIMER[3]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ & ( (!\myVirtualToplevel|Equal8~1_combout\ & \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\) ) ) # (
--- !\myVirtualToplevel|SD_STATE.SD_STATE_RESET~DUPLICATE_q\ & ( (!\myVirtualToplevel|Equal8~1_combout\) # (!\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101011111010111110101111101000001010000010100000101000001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~DUPLICATE_q\,
- combout => \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\);
-
--- Location: FF_X24_Y10_N32
-\myVirtualToplevel|SD_RESET_TIMER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector8~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_RESET_TIMER\(1));
-
--- Location: LABCELL_X24_Y10_N6
-\myVirtualToplevel|Add0~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add0~9_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add0~18\ ))
--- \myVirtualToplevel|Add0~10\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add0~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(2),
- cin => \myVirtualToplevel|Add0~18\,
- sumout => \myVirtualToplevel|Add0~9_sumout\,
- cout => \myVirtualToplevel|Add0~10\);
-
--- Location: LABCELL_X24_Y10_N24
-\myVirtualToplevel|SD_RESET_TIMER~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_RESET_TIMER~2_combout\ = ( \myVirtualToplevel|Add0~9_sumout\ & ( !\myVirtualToplevel|Equal8~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_Equal8~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Add0~9_sumout\,
- combout => \myVirtualToplevel|SD_RESET_TIMER~2_combout\);
-
--- Location: FF_X24_Y10_N26
-\myVirtualToplevel|SD_RESET_TIMER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_RESET_TIMER~2_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- ena => \myVirtualToplevel|Selector3~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_RESET_TIMER\(2));
-
--- Location: FF_X24_Y10_N46
-\myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_RESET_TIMER~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- ena => \myVirtualToplevel|Selector3~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y10_N9
-\myVirtualToplevel|Add0~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add0~13_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add0~10\ ))
--- \myVirtualToplevel|Add0~14\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add0~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add0~10\,
- sumout => \myVirtualToplevel|Add0~13_sumout\,
- cout => \myVirtualToplevel|Add0~14\);
-
--- Location: LABCELL_X24_Y10_N51
-\myVirtualToplevel|Selector6~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector6~0_combout\ = ( \myVirtualToplevel|Add0~13_sumout\ ) # ( !\myVirtualToplevel|Add0~13_sumout\ & ( !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- dataf => \myVirtualToplevel|ALT_INV_Add0~13_sumout\,
- combout => \myVirtualToplevel|Selector6~0_combout\);
-
--- Location: FF_X24_Y10_N52
-\myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector6~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_RESET_TIMER[3]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y10_N12
-\myVirtualToplevel|Add0~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add0~5_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add0~14\ ))
--- \myVirtualToplevel|Add0~6\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER[4]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add0~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER[4]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add0~14\,
- sumout => \myVirtualToplevel|Add0~5_sumout\,
- cout => \myVirtualToplevel|Add0~6\);
-
--- Location: LABCELL_X24_Y10_N45
-\myVirtualToplevel|SD_RESET_TIMER~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_RESET_TIMER~1_combout\ = ( \myVirtualToplevel|Add0~5_sumout\ & ( !\myVirtualToplevel|Equal8~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Add0~5_sumout\,
- combout => \myVirtualToplevel|SD_RESET_TIMER~1_combout\);
-
--- Location: FF_X24_Y10_N47
-\myVirtualToplevel|SD_RESET_TIMER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_RESET_TIMER~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- ena => \myVirtualToplevel|Selector3~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_RESET_TIMER\(4));
-
--- Location: LABCELL_X24_Y10_N15
-\myVirtualToplevel|Add0~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add0~21_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add0~6\ ))
--- \myVirtualToplevel|Add0~22\ = CARRY(( \myVirtualToplevel|SD_RESET_TIMER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add0~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(5),
- cin => \myVirtualToplevel|Add0~6\,
- sumout => \myVirtualToplevel|Add0~21_sumout\,
- cout => \myVirtualToplevel|Add0~22\);
-
--- Location: LABCELL_X24_Y10_N42
-\myVirtualToplevel|SD_RESET_TIMER~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_RESET_TIMER~4_combout\ = ( \myVirtualToplevel|Add0~21_sumout\ & ( !\myVirtualToplevel|Equal8~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Add0~21_sumout\,
- combout => \myVirtualToplevel|SD_RESET_TIMER~4_combout\);
-
--- Location: FF_X24_Y10_N44
-\myVirtualToplevel|SD_RESET_TIMER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_RESET_TIMER~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- ena => \myVirtualToplevel|Selector3~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_RESET_TIMER\(5));
-
--- Location: LABCELL_X24_Y10_N18
-\myVirtualToplevel|Add0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add0~1_sumout\ = SUM(( \myVirtualToplevel|SD_RESET_TIMER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add0~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(6),
- cin => \myVirtualToplevel|Add0~22\,
- sumout => \myVirtualToplevel|Add0~1_sumout\);
-
--- Location: LABCELL_X24_Y10_N36
-\myVirtualToplevel|SD_RESET_TIMER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_RESET_TIMER~0_combout\ = ( \myVirtualToplevel|Add0~1_sumout\ & ( !\myVirtualToplevel|Equal8~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal8~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Add0~1_sumout\,
- combout => \myVirtualToplevel|SD_RESET_TIMER~0_combout\);
-
--- Location: FF_X24_Y10_N37
-\myVirtualToplevel|SD_RESET_TIMER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_RESET_TIMER~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- ena => \myVirtualToplevel|Selector3~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_RESET_TIMER\(6));
-
--- Location: FF_X24_Y10_N53
-\myVirtualToplevel|SD_RESET_TIMER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector6~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|SD_RESET_TIMER[3]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_RESET_TIMER\(3));
-
--- Location: LABCELL_X24_Y10_N48
-\myVirtualToplevel|Equal8~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal8~0_combout\ = ( !\myVirtualToplevel|SD_RESET_TIMER\(1) & ( (!\myVirtualToplevel|SD_RESET_TIMER\(5) & (!\myVirtualToplevel|SD_RESET_TIMER\(3) & !\myVirtualToplevel|SD_RESET_TIMER\(0))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(5),
- datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(3),
- datad => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(0),
- dataf => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(1),
- combout => \myVirtualToplevel|Equal8~0_combout\);
-
--- Location: LABCELL_X24_Y10_N27
-\myVirtualToplevel|Equal8~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal8~1_combout\ = ( \myVirtualToplevel|Equal8~0_combout\ & ( (!\myVirtualToplevel|SD_RESET_TIMER\(2) & (!\myVirtualToplevel|SD_RESET_TIMER\(4) & !\myVirtualToplevel|SD_RESET_TIMER\(6))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010100000000000001010000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(2),
- datac => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(4),
- datad => \myVirtualToplevel|ALT_INV_SD_RESET_TIMER\(6),
- dataf => \myVirtualToplevel|ALT_INV_Equal8~0_combout\,
- combout => \myVirtualToplevel|Equal8~1_combout\);
-
--- Location: LABCELL_X21_Y10_N57
-\myVirtualToplevel|Selector15~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector15~7_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( (\myVirtualToplevel|Selector15~6_combout\ & ((\myVirtualToplevel|Equal8~1_combout\) # (\myVirtualToplevel|Selector15~4_combout\))) ) ) # (
--- !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( (\myVirtualToplevel|Selector15~6_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) # (\myVirtualToplevel|Selector15~4_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101100001011000010110000101100000011000011110000001100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\,
- datab => \myVirtualToplevel|ALT_INV_Selector15~4_combout\,
- datac => \myVirtualToplevel|ALT_INV_Selector15~6_combout\,
- datad => \myVirtualToplevel|ALT_INV_Equal8~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- combout => \myVirtualToplevel|Selector15~7_combout\);
-
--- Location: LABCELL_X20_Y10_N6
-\myVirtualToplevel|Selector18~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector18~0_combout\ = ( \myVirtualToplevel|Selector15~7_combout\ & ( (\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|Selector15~7_combout\ & ( (!\myVirtualToplevel|Selector15~2_combout\ & (((\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~q\)))) # (\myVirtualToplevel|Selector15~2_combout\ & (\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100000101000001010000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\,
- datab => \myVirtualToplevel|ALT_INV_Selector15~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~q\,
- dataf => \myVirtualToplevel|ALT_INV_Selector15~7_combout\,
- combout => \myVirtualToplevel|Selector18~0_combout\);
-
--- Location: FF_X20_Y10_N8
-\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector18~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\);
-
--- Location: LABCELL_X20_Y10_N18
-\myVirtualToplevel|Selector15~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector15~3_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ &
--- !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\)) ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ((!\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\) #
--- ((!\myVirtualToplevel|SD_DATA_VALID~DUPLICATE_q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110110000000000111011000000000000001100000000000000110000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_DATA_VALID~DUPLICATE_q\,
- datab => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~DUPLICATE_q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\,
- combout => \myVirtualToplevel|Selector15~3_combout\);
-
--- Location: LABCELL_X20_Y10_N36
-\myVirtualToplevel|Selector15~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector15~4_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ & ( (\myVirtualToplevel|Selector15~3_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ &
--- (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ((!\myVirtualToplevel|SD_DATA_REQ~q\))))) ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ & (
--- (\myVirtualToplevel|Selector15~3_combout\ & ((!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_1~q\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & !\myVirtualToplevel|SD_DATA_REQ~q\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101100001010000010110000101000001011000010000000101100001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_1~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_Selector15~3_combout\,
- datad => \myVirtualToplevel|ALT_INV_SD_DATA_REQ~q\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\,
- combout => \myVirtualToplevel|Selector15~4_combout\);
-
--- Location: LABCELL_X21_Y10_N54
-\myVirtualToplevel|Selector15~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector15~5_combout\ = ( \myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & ( (!\myVirtualToplevel|Selector15~4_combout\ & \myVirtualToplevel|Equal8~1_combout\) ) ) # ( !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & !\myVirtualToplevel|Selector15~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000100010001000100010001000100000001100000011000000110000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\,
- datab => \myVirtualToplevel|ALT_INV_Selector15~4_combout\,
- datac => \myVirtualToplevel|ALT_INV_Equal8~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- combout => \myVirtualToplevel|Selector15~5_combout\);
-
--- Location: LABCELL_X21_Y10_N24
-\myVirtualToplevel|Selector10~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector10~0_combout\ = ( \myVirtualToplevel|Selector11~0_combout\ & ( ((!\myVirtualToplevel|Selector15~2_combout\ & \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\)) # (\myVirtualToplevel|Selector15~5_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101111101010101010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Selector15~5_combout\,
- datac => \myVirtualToplevel|ALT_INV_Selector15~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\,
- dataf => \myVirtualToplevel|ALT_INV_Selector11~0_combout\,
- combout => \myVirtualToplevel|Selector10~0_combout\);
-
--- Location: FF_X21_Y10_N25
-\myVirtualToplevel|SD_STATE.SD_STATE_IDLE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector10~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\);
-
--- Location: LABCELL_X21_Y10_N30
-\myVirtualToplevel|Selector2~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector2~0_combout\ = ( \myVirtualToplevel|SD_RD\(0) & ( \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (\myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) #
--- (\myVirtualToplevel|SD_CHANNEL~q\))) ) ) ) # ( !\myVirtualToplevel|SD_RD\(0) & ( \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ &
--- \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|SD_RD\(0) & ( !\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) #
--- (!\myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\)) # (\myVirtualToplevel|SD_CHANNEL~q\) ) ) ) # ( !\myVirtualToplevel|SD_RD\(0) & ( !\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & \myVirtualToplevel|SD_STATE.SD_STATE_READ~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010100000111111111111010100000000101000000000000011110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_CHANNEL~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~DUPLICATE_q\,
- datae => \myVirtualToplevel|ALT_INV_SD_RD\(0),
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\,
- combout => \myVirtualToplevel|Selector2~0_combout\);
-
--- Location: FF_X21_Y10_N31
-\myVirtualToplevel|SD_RD[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector2~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_RD\(0));
-
--- Location: LABCELL_X26_Y8_N12
-\myVirtualToplevel|SD_RD[0]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_RD[0]~_wirecell_combout\ = ( !\myVirtualToplevel|SD_RD\(0) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_SD_RD\(0),
- combout => \myVirtualToplevel|SD_RD[0]~_wirecell_combout\);
-
--- Location: FF_X26_Y7_N7
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13_sumout\,
- asdata => \myVirtualToplevel|SD_RD[0]~_wirecell_combout\,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2));
-
--- Location: LABCELL_X26_Y7_N3
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~2\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\);
-
--- Location: LABCELL_X26_Y7_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(2),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~6\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\);
-
--- Location: FF_X26_Y7_N8
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~13_sumout\,
- asdata => \myVirtualToplevel|SD_RD[0]~_wirecell_combout\,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\);
-
--- Location: FF_X26_Y7_N28
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9_sumout\,
- asdata => VCC,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9));
-
--- Location: LABCELL_X26_Y7_N9
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(3),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~14\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\);
-
--- Location: FF_X26_Y7_N11
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~17_sumout\,
- asdata => \~GND~combout\,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(3));
-
--- Location: LABCELL_X26_Y7_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(4),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~18\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\);
-
--- Location: FF_X26_Y7_N14
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~21_sumout\,
- asdata => \~GND~combout\,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(4));
-
--- Location: LABCELL_X26_Y7_N15
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(5),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~22\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\);
-
--- Location: FF_X26_Y7_N17
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~25_sumout\,
- asdata => \~GND~combout\,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(5));
-
--- Location: LABCELL_X26_Y7_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(6) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(6) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(6),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~26\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\);
-
--- Location: FF_X26_Y7_N20
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~29_sumout\,
- asdata => \~GND~combout\,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(6));
-
--- Location: LABCELL_X26_Y7_N21
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(7) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(7) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(7),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~30\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\);
-
--- Location: FF_X26_Y7_N23
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~33_sumout\,
- asdata => \~GND~combout\,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(7));
-
--- Location: LABCELL_X26_Y7_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(8) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~38\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(8) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(8),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~34\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~38\);
-
--- Location: FF_X26_Y7_N26
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~37_sumout\,
- asdata => \~GND~combout\,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(8));
-
--- Location: LABCELL_X26_Y7_N27
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~38\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9_sumout\);
-
--- Location: FF_X26_Y7_N29
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~9_sumout\,
- asdata => VCC,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y7_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(7) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(3) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(6) &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(5) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(8) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(4)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(6),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(5),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(8),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(4),
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(7),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(3),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\);
-
--- Location: LABCELL_X26_Y7_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1)) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111101111111111111110111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\);
-
--- Location: LABCELL_X24_Y6_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0))))) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101111000000001110111100000000001000110000000000100011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal4~0_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0_combout\);
-
--- Location: LABCELL_X25_Y7_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[4]~0_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\)))) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001111111010101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[4]~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\);
-
--- Location: FF_X26_Y7_N2
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~1_sumout\,
- asdata => VCC,
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0));
-
--- Location: FF_X26_Y7_N5
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add3~5_sumout\,
- asdata => \myVirtualToplevel|SD_RD\(0),
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[0]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1));
-
--- Location: LABCELL_X26_Y7_N39
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000100000000000000010000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\);
-
--- Location: LABCELL_X24_Y6_N9
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000001010000010111110101111101011111010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal4~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62_combout\);
-
--- Location: LABCELL_X26_Y7_N57
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000100000000000000010000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\);
-
--- Location: LABCELL_X24_Y6_N57
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # (\SDCARD_MISO[0]~input_o\))))
--- ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # (\SDCARD_MISO[0]~input_o\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # (\SDCARD_MISO[0]~input_o\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101100000000111110110000000011111011000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datab => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\);
-
--- Location: LABCELL_X26_Y6_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(5) &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(6))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(5),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(6),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(7),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0_combout\);
-
--- Location: LABCELL_X26_Y6_N54
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011000000000000001100000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\);
-
--- Location: LABCELL_X21_Y6_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100010001000100010001000100010001000100010001000100010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\);
-
--- Location: LABCELL_X24_Y7_N51
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & \myVirtualToplevel|SD_HNDSHK_IN\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\);
-
--- Location: MLABCELL_X23_Y6_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ & (
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (\myVirtualToplevel|SD_RESET\(0)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\
--- ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000000000111111111111111100110000000000001111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD0~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57_combout\);
-
--- Location: FF_X23_Y6_N1
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~57_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\);
-
--- Location: LABCELL_X25_Y6_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ $ (!\SDCARD_MISO[0]~input_o\)))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & !\SDCARD_MISO[0]~input_o\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000101010001000100010101000100000000010000010000000001000001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datad => \ALT_INV_SDCARD_MISO[0]~input_o\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\);
-
--- Location: LABCELL_X25_Y6_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000110011111100000011001100000000001100110000000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\);
-
--- Location: LABCELL_X25_Y6_N45
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~76_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010100000000010101010000000000000101000000000000010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~52_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~76_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\);
-
--- Location: LABCELL_X25_Y6_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000111000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~77_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\);
-
--- Location: LABCELL_X25_Y6_N15
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000111000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\);
-
--- Location: LABCELL_X21_Y6_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & (!\myVirtualToplevel|SD_RESET\(0) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\)) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD0~q\ & (!\myVirtualToplevel|SD_RESET\(0) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\)) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~75_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\ & (!\myVirtualToplevel|SD_RESET\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~78_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010100000111100001010000000110000000000000011000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal2~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD0~q\,
- datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~78_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~75_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79_combout\);
-
--- Location: FF_X21_Y6_N38
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~79_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\);
-
--- Location: MLABCELL_X23_Y6_N9
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (!\myVirtualToplevel|SD_RESET\(0) &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) # (\myVirtualToplevel|SD_RESET\(0)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111011111111111100110000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_CMD0_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60_combout\);
-
--- Location: FF_X23_Y6_N10
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~60_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\);
-
--- Location: MLABCELL_X23_Y6_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & (
--- (!\myVirtualToplevel|SD_RESET\(0) & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_CMD0_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010000000000000000000101010101010100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_CMD0_RESPONSE~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87_combout\);
-
--- Location: FF_X23_Y6_N20
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~87_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\);
-
--- Location: LABCELL_X21_Y6_N54
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\);
-
--- Location: LABCELL_X26_Y6_N15
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~77_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~77_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\);
-
--- Location: LABCELL_X21_Y6_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal2~0_combout\ & (!\myVirtualToplevel|SD_RESET\(0) &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~80_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~81_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110011001100110000000000010000001100000001000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal2~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~80_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~81_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82_combout\);
-
--- Location: FF_X21_Y6_N20
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~82_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\);
-
--- Location: MLABCELL_X23_Y6_N39
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (!\myVirtualToplevel|SD_RESET\(0) &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) # (\myVirtualToplevel|SD_RESET\(0)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111011111111111100110000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD55~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55_combout\);
-
--- Location: FF_X23_Y6_N40
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~55_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\);
-
--- Location: MLABCELL_X23_Y6_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((\myVirtualToplevel|SD_RESET\(0)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111011111111111100110000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD41~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56_combout\);
-
--- Location: FF_X23_Y6_N7
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~56_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\);
-
--- Location: MLABCELL_X23_Y6_N57
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD41~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010000000000000000000101010101010100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD41~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74_combout\);
-
--- Location: FF_X23_Y6_N59
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~74_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\);
-
--- Location: LABCELL_X20_Y7_N51
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000010100000101000001010000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\);
-
--- Location: LABCELL_X24_Y7_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr40~0_combout\) #
--- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010111111101111101011111110111110101111101011111010111110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr40~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_doDeselect_v~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0_combout\);
-
--- Location: FF_X24_Y7_N49
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector160~0_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\);
-
--- Location: LABCELL_X25_Y6_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001111110011001100111111001100000000111100000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_doDeselect_v~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\);
-
--- Location: LABCELL_X25_Y6_N51
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001011111010111110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~47_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\);
-
--- Location: LABCELL_X21_Y6_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ &
--- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0)))) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.SEND_CMD55~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000000000011001100000101001101110000010100110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.SEND_CMD55~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~66_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\);
-
--- Location: LABCELL_X21_Y6_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~72_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010001000000000001000100000100010101010100010001010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~72_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73_combout\);
-
--- Location: FF_X21_Y6_N1
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~73_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\);
-
--- Location: LABCELL_X20_Y7_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD0~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD55~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD55~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD0~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\);
-
--- Location: LABCELL_X25_Y5_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011010000000000001101000000000000110000000000000011000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(4),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\);
-
--- Location: LABCELL_X24_Y5_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\);
-
--- Location: LABCELL_X24_Y7_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ &
--- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(9)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(2))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1)))) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100010011001100110001001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(2),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(9),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40_combout\);
-
--- Location: LABCELL_X21_Y6_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & ((!\myVirtualToplevel|SD_RESET\(0)))))) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\) # (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~40_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "on",
- lut_mask => "0000111100001111110011111110111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~40_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- dataf => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datag => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89_combout\);
-
--- Location: FF_X21_Y6_N7
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~89_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\);
-
--- Location: LABCELL_X25_Y7_N39
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\);
-
--- Location: LABCELL_X25_Y7_N3
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\);
-
--- Location: LABCELL_X21_Y6_N45
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_CMD0_RESPONSE~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101000000000101010100000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_CMD0_RESPONSE~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\);
-
--- Location: LABCELL_X24_Y5_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( \SDCARD_MISO[0]~input_o\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( !\SDCARD_MISO[0]~input_o\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( !\SDCARD_MISO[0]~input_o\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010001000000000000000100000000000100010000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- dataf => \ALT_INV_SDCARD_MISO[0]~input_o\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\);
-
--- Location: LABCELL_X21_Y6_N3
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\);
-
--- Location: FF_X26_Y5_N26
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~q\);
-
--- Location: LABCELL_X26_Y5_N39
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) #
--- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000011111111110000001100000011000000110000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\);
-
--- Location: LABCELL_X24_Y5_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ((!\SDCARD_MISO[0]~input_o\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001010000011110000101000001111000010100000111100001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44_combout\);
-
--- Location: LABCELL_X26_Y5_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) # (\SDCARD_MISO[0]~input_o\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) # (\SDCARD_MISO[0]~input_o\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000000000000000000011111111001100111111111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- datab => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\);
-
--- Location: LABCELL_X24_Y5_N3
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & !\SDCARD_MISO[0]~input_o\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000100110000001100010011000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datad => \ALT_INV_SDCARD_MISO[0]~input_o\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\);
-
--- Location: LABCELL_X25_Y5_N21
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001101000000000000110100000000000011000000000000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(5),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\);
-
--- Location: LABCELL_X25_Y5_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(4),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\);
-
--- Location: LABCELL_X25_Y5_N45
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(5),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~10\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\);
-
--- Location: LABCELL_X26_Y5_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # (\SDCARD_MISO[0]~input_o\))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\) # (\SDCARD_MISO[0]~input_o\)))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101000001000000010101000100010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\,
- datad => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\);
-
--- Location: LABCELL_X25_Y5_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\)) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\ ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~0_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~13_sumout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011111111111111101111111111110000111100001111111011111110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector66~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~13_sumout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(5),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~4_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1_combout\);
-
--- Location: FF_X25_Y5_N14
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector66~1_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5));
-
--- Location: LABCELL_X25_Y5_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~26\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(6),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~14\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~26\);
-
--- Location: LABCELL_X25_Y5_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\ &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\) # (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\)) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~44_combout\)) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~25_sumout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000101111111011101100001111000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~44_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~25_sumout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~4_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(6),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0_combout\);
-
--- Location: FF_X25_Y5_N2
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector65~0_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6));
-
--- Location: LABCELL_X26_Y5_N3
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110011111100111111001111110000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\);
-
--- Location: LABCELL_X26_Y5_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111000001110000011100000111000001110000011100000111000001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1_combout\);
-
--- Location: LABCELL_X21_Y7_N51
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\);
-
--- Location: LABCELL_X26_Y5_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011000000000000001100000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4_combout\);
-
--- Location: LABCELL_X26_Y5_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~4_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111011000000000011101100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~4_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\);
-
--- Location: LABCELL_X26_Y5_N9
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ &
--- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\)))) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111011101110000011101110111000001100110011000000110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\);
-
--- Location: LABCELL_X26_Y5_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~1_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000110011001100110000001111000011110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(0),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~1_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~5_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~3_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\);
-
--- Location: LABCELL_X25_Y5_N27
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\))) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111011111111111100010000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~2_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8_combout\);
-
--- Location: FF_X25_Y5_N29
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[0]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0));
-
--- Location: LABCELL_X25_Y5_N51
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(7),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~26\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\);
-
--- Location: LABCELL_X24_Y5_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\ ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\ ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & !\SDCARD_MISO[0]~input_o\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~29_sumout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100010001000100110001000100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~29_sumout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datad => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\);
-
--- Location: LABCELL_X24_Y5_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011111111111111101111111111001100111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~1_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(7),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2_combout\);
-
--- Location: FF_X24_Y5_N50
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~2_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7));
-
--- Location: MLABCELL_X23_Y5_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\);
-
--- Location: MLABCELL_X23_Y6_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\);
-
--- Location: LABCELL_X24_Y5_N27
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\);
-
--- Location: MLABCELL_X23_Y5_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # (!\SDCARD_MISO[0]~input_o\)))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~2_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~3_combout\ &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100000000001100100000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~3_combout\,
- datac => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector87~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\);
-
--- Location: LABCELL_X25_Y5_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(0),
- cin => GND,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\);
-
--- Location: LABCELL_X25_Y5_N33
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(1),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~18\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\);
-
--- Location: LABCELL_X24_Y5_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~21_sumout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & !\SDCARD_MISO[0]~input_o\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000011111000011111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\,
- datad => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~21_sumout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\);
-
--- Location: LABCELL_X24_Y5_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\) # (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\)) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\)) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~4_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1011101110111011111111111011111110111011101110111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~4_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector70~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(1),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5_combout\);
-
--- Location: FF_X24_Y5_N32
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector70~5_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1));
-
--- Location: LABCELL_X25_Y5_N54
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(1) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(6) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(0) &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(7))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(6),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(7),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(1),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\);
-
--- Location: LABCELL_X24_Y5_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\ = ( \SDCARD_MISO[0]~input_o\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ &
--- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\))) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\)))) ) ) ) # ( !\SDCARD_MISO[0]~input_o\ & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\)) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) ) ) ) # ( \SDCARD_MISO[0]~input_o\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) ) ) ) # ( !\SDCARD_MISO[0]~input_o\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~47_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000010100000101000001111001111110000101000111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~0_combout\,
- datae => \ALT_INV_SDCARD_MISO[0]~input_o\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~47_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\);
-
--- Location: LABCELL_X25_Y5_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(2),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~22\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\);
-
--- Location: LABCELL_X26_Y5_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\)))) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\))) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector71~0_combout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~1_sumout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\) #
--- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~5_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~3_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~43_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000100110101011000000010010001111001101111011110100010101100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~5_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~3_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~43_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector71~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~1_sumout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\);
-
--- Location: LABCELL_X25_Y5_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\))) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector69~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~0_combout\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~2_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111011111111111100010000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~1_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~2_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(2),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector69~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6_combout\);
-
--- Location: FF_X25_Y5_N26
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2));
-
--- Location: LABCELL_X25_Y5_N39
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(3),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~2\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~6\);
-
--- Location: LABCELL_X24_Y5_N9
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~5_sumout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & !\SDCARD_MISO[0]~input_o\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000010000111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datac => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~5_sumout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\);
-
--- Location: LABCELL_X24_Y5_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\) # (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\)) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\)) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~2_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1011101110111011111111111111101110111011101110111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~2_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(3),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3_combout\);
-
--- Location: FF_X24_Y5_N38
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~3_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3));
-
--- Location: LABCELL_X25_Y5_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\)) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\ ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\) #
--- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector64~0_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[2]~7_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\)) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector68~4_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~0_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add4~9_sumout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1011101110111011111111111111101110101010101010101111111111111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector67~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add4~9_sumout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector64~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v[2]~7_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(4),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector68~4_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1_combout\);
-
--- Location: FF_X25_Y5_N8
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector67~1_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4));
-
--- Location: LABCELL_X25_Y5_N57
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(3) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(4) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(5) &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|bitCnt_v\(2))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(4),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(5),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(2),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_bitCnt_v\(3),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\);
-
--- Location: LABCELL_X26_Y5_N57
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~1_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\);
-
--- Location: LABCELL_X25_Y7_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\);
-
--- Location: LABCELL_X24_Y6_N15
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ &
--- !\myVirtualToplevel|SD_RESET\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000001010000000000000101000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\);
-
--- Location: LABCELL_X24_Y6_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~62_combout\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~63_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~64_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000000000000010100000001011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~62_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~64_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~63_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65_combout\);
-
--- Location: FF_X24_Y6_N26
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~65_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\);
-
--- Location: MLABCELL_X23_Y5_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\))) # (\SDCARD_MISO[0]~input_o\) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & ( (\SDCARD_MISO[0]~input_o\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000011111110111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[13]~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0_combout\);
-
--- Location: FF_X23_Y5_N38
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0));
-
--- Location: LABCELL_X21_Y6_N27
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111011101111111111101110100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\);
-
--- Location: LABCELL_X24_Y6_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ = ( \myVirtualToplevel|SD_WR\(0) & ( \myVirtualToplevel|SD_RD\(0) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # (!\SDCARD_MISO[0]~input_o\))) ) ) ) # ( !\myVirtualToplevel|SD_WR\(0) & ( \myVirtualToplevel|SD_RD\(0) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # (!\SDCARD_MISO[0]~input_o\))) ) ) ) # ( \myVirtualToplevel|SD_WR\(0) & ( !\myVirtualToplevel|SD_RD\(0) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # (!\SDCARD_MISO[0]~input_o\))) ) ) ) # ( !\myVirtualToplevel|SD_WR\(0) & ( !\myVirtualToplevel|SD_RD\(0) & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) # (!\SDCARD_MISO[0]~input_o\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011111100101111001100110010001000110011001000100011001100100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- datad => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datae => \myVirtualToplevel|ALT_INV_SD_WR\(0),
- dataf => \myVirtualToplevel|ALT_INV_SD_RD\(0),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\);
-
--- Location: LABCELL_X24_Y7_N45
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\);
-
--- Location: MLABCELL_X23_Y5_N57
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\);
-
--- Location: LABCELL_X24_Y6_N33
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110011111100111111001111110011111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\);
-
--- Location: MLABCELL_X23_Y6_N33
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\))) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~53_combout\ & ( (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111011100000000000010001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WAIT_FOR_HOST_RW~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~53_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54_combout\);
-
--- Location: FF_X23_Y6_N34
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~54_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\);
-
--- Location: LABCELL_X21_Y6_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & (
--- (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\)))) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~70_combout\ & (!\myVirtualToplevel|SD_RESET\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010100000111100001010000000000000101100001111000010110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~70_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~66_combout\,
- datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WAIT_FOR_HOST_RW~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71_combout\);
-
--- Location: FF_X21_Y6_N32
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~71_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\);
-
--- Location: LABCELL_X21_Y6_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ &
--- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ &
--- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111011111110000011101111111000000010111100100000001011110010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0_combout\);
-
--- Location: FF_X21_Y6_N13
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~0_combout\,
- asdata => VCC,
- sload => \myVirtualToplevel|SD_RESET\(0),
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\);
-
--- Location: LABCELL_X21_Y10_N51
-\myVirtualToplevel|Selector1~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Selector1~0_combout\ = ( \myVirtualToplevel|SD_WR\(0) & ( \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) #
--- (\myVirtualToplevel|SD_CHANNEL~q\))) ) ) ) # ( !\myVirtualToplevel|SD_WR\(0) & ( \myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ &
--- \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|SD_WR\(0) & ( !\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\) #
--- (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\)) # (\myVirtualToplevel|SD_CHANNEL~q\) ) ) ) # ( !\myVirtualToplevel|SD_WR\(0) & ( !\myVirtualToplevel|SD_STATE.SD_STATE_IDLE~q\ & ( (!\myVirtualToplevel|SD_CHANNEL~q\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|busy_o~q\ & \myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010100000111111111111010100000000101000000000000011110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_CHANNEL~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_busy_o~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~DUPLICATE_q\,
- datae => \myVirtualToplevel|ALT_INV_SD_WR\(0),
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_IDLE~q\,
- combout => \myVirtualToplevel|Selector1~0_combout\);
-
--- Location: FF_X21_Y10_N52
-\myVirtualToplevel|SD_WR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Selector1~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_WR\(0));
-
--- Location: LABCELL_X25_Y7_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ = ( !\myVirtualToplevel|SD_RD\(0) & ( !\myVirtualToplevel|SD_WR\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SD_WR\(0),
- dataf => \myVirtualToplevel|ALT_INV_SD_RD\(0),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\);
-
--- Location: LABCELL_X21_Y6_N15
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~41_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~41_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\);
-
--- Location: MLABCELL_X23_Y5_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (\SDCARD_MISO[0]~input_o\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr13~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000101010100000000000000010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datac => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr13~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\);
-
--- Location: MLABCELL_X23_Y6_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD41~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((\myVirtualToplevel|SD_RESET\(0)) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111011111111111100110000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_ACMD41_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD41~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61_combout\);
-
--- Location: FF_X23_Y6_N43
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~61_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\);
-
--- Location: MLABCELL_X23_Y6_N21
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & (
--- (!\myVirtualToplevel|SD_RESET\(0) & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\))) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.CHK_ACMD41_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010000000000000000000101010101010100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.CHK_ACMD41_RESPONSE~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88_combout\);
-
--- Location: FF_X23_Y6_N23
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~88_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\);
-
--- Location: LABCELL_X26_Y6_N3
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2) & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(4) &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(3) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001000000000000000100000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(2),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(4),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(3),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\);
-
--- Location: LABCELL_X26_Y7_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000000000001000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\);
-
--- Location: LABCELL_X26_Y6_N45
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_STD_MATCH~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o~3_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\);
-
--- Location: LABCELL_X24_Y6_N51
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & ( ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal4~0_combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111110011111111111111001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal4~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\);
-
--- Location: LABCELL_X21_Y6_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.CHK_ACMD41_RESPONSE~q\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & (!\myVirtualToplevel|SD_RESET\(0) & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal1~1_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~85_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & !\myVirtualToplevel|SD_RESET\(0)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000111100001111000000010000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.CHK_ACMD41_RESPONSE~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal1~1_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~85_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86_combout\);
-
--- Location: FF_X21_Y6_N50
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~86_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\);
-
--- Location: LABCELL_X25_Y6_N54
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & \SDCARD_MISO[0]~input_o\)))) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & !\SDCARD_MISO[0]~input_o\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000101110001100000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datad => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~48_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\);
-
--- Location: MLABCELL_X23_Y6_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & !\myVirtualToplevel|SD_RESET\(0))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.SEND_CMD8~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~51_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # ((\myVirtualToplevel|SD_RESET\(0)) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111011111111111100110000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~51_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.GET_CMD8_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.SEND_CMD8~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52_combout\);
-
--- Location: FF_X23_Y6_N37
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~52_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\);
-
--- Location: MLABCELL_X23_Y6_N54
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & (
--- (!\myVirtualToplevel|SD_RESET\(0) & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.GET_CMD8_RESPONSE~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010000000000000000000101010101010100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.GET_CMD8_RESPONSE~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69_combout\);
-
--- Location: FF_X23_Y6_N56
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~69_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\);
-
--- Location: LABCELL_X24_Y7_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD8_RESPONSE~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector110~1_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000110000000000000011000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD8_RESPONSE~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector110~1_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0_combout\);
-
--- Location: FF_X24_Y7_N7
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector159~0_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\);
-
--- Location: MLABCELL_X28_Y5_N21
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111100000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\);
-
--- Location: MLABCELL_X28_Y5_N45
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\ ))
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~6\ = CARRY(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(5) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(5),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~22\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\,
- cout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~6\);
-
--- Location: MLABCELL_X23_Y5_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011101110110011001110111011001100111011101100110011101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(5),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0_combout\);
-
--- Location: FF_X23_Y5_N44
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector17~0_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5));
-
--- Location: MLABCELL_X28_Y5_N3
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5) & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~5_sumout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(5) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000000000001100100010001000010001000000000011001100100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~5_sumout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(5),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4_combout\);
-
--- Location: FF_X28_Y5_N5
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[5]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(5));
-
--- Location: MLABCELL_X28_Y5_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ = SUM(( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(6) ) + ( VCC ) + ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(6),
- cin => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~6\,
- sumout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\);
-
--- Location: MLABCELL_X23_Y5_N45
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011101110110011001110111011001100111011101100110011101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(6),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0_combout\);
-
--- Location: FF_X23_Y5_N46
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector16~0_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6));
-
--- Location: MLABCELL_X28_Y5_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6) & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Add0~9_sumout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|clkDivider_v\(6) & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~2_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[0]~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000000000001100100010001000010000000100000011001000110010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~2_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v[0]~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Add0~9_sumout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_clkDivider_v\(6),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5_combout\);
-
--- Location: FF_X28_Y5_N8
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v[6]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(6));
-
--- Location: MLABCELL_X28_Y5_N57
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(3) & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(6) &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclkPhaseTimer_v\(5)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(6),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(5),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclkPhaseTimer_v\(3),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\);
-
--- Location: LABCELL_X26_Y6_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~1_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~1_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\);
-
--- Location: LABCELL_X24_Y6_N21
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\);
-
--- Location: LABCELL_X24_Y6_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ &
--- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\)))) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\)) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000011110000000100001111000000010000101100000001000010110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\,
- datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46_combout\);
-
--- Location: FF_X24_Y6_N19
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~46_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\);
-
--- Location: LABCELL_X25_Y6_N21
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & !\myVirtualToplevel|SD_RESET\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\);
-
--- Location: LABCELL_X25_Y6_N27
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( !\myVirtualToplevel|SD_RESET\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\);
-
--- Location: LABCELL_X25_Y6_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & (
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\))) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~59_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\ & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\)))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~58_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000101011111111111010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~59_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~58_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60_combout\);
-
--- Location: FF_X25_Y6_N32
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~60_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\);
-
--- Location: LABCELL_X26_Y5_N54
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_TX~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010000000000000001000000000000000100000000000000010000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_TX~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\);
-
--- Location: LABCELL_X26_Y5_N45
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\ = ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\)) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100111111111111110011111111111111001111111111111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\);
-
--- Location: LABCELL_X26_Y5_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ &
--- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~2_combout\ &
--- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\))))) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & (
--- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~1_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ &
--- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "on",
- lut_mask => "0011001100110011001100110011001100000000010100000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~2_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datag => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3_combout\);
-
--- Location: FF_X26_Y5_N25
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~3_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\);
-
--- Location: MLABCELL_X23_Y6_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\))) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector87~0_combout\ & ( (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111011100000000000010001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_WAIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector87~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50_combout\);
-
--- Location: FF_X23_Y6_N32
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~50_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\);
-
--- Location: LABCELL_X26_Y6_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\ & ( ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.WR_WAIT~q\) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~66_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o~3_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_BLK~q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|STD_MATCH~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100000001000000010000000100000001111111110000000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o~3_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_BLK~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_STD_MATCH~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.WR_WAIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~66_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\);
-
--- Location: LABCELL_X24_Y6_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\ & ( !\myVirtualToplevel|SD_RESET\(0) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & !\myVirtualToplevel|SD_RESET\(0)) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~67_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\) #
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\) # (!\SDCARD_MISO[0]~input_o\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001110000000110000001100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datad => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~67_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68_combout\);
-
--- Location: FF_X24_Y6_N44
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~68_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\);
-
--- Location: LABCELL_X25_Y6_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|doDeselect_v~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_doDeselect_v~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\);
-
--- Location: LABCELL_X25_Y6_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.GET_CMD_RESPONSE~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~42_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.GET_CMD_RESPONSE~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\);
-
--- Location: LABCELL_X25_Y6_N3
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\)))) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|getCmdResponse_v~q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~52_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010101010100000101010101000000010001000100000001000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~52_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.REPORT_ERROR~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_getCmdResponse_v~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\);
-
--- Location: LABCELL_X24_Y6_N30
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ((\myVirtualToplevel|SD_RD\(0)))) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WAIT_FOR_HOST_RW~q\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000000000011001100001111001100110000111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\,
- datac => \myVirtualToplevel|ALT_INV_SD_RD\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WAIT_FOR_HOST_RW~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\);
-
--- Location: MLABCELL_X23_Y6_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ &
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\))) ) ) ) # (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~48_combout\ & ( (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\) #
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~47_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111011100000000000010001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~47_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.RD_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~48_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49_combout\);
-
--- Location: FF_X23_Y6_N25
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~49_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\);
-
--- Location: MLABCELL_X23_Y6_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.RD_BLK~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~56_combout\) # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010000000000000000000101010101010100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~56_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.RD_BLK~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57_combout\);
-
--- Location: FF_X23_Y6_N50
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~57_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\);
-
--- Location: MLABCELL_X23_Y6_N15
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\)))) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & ( (!\myVirtualToplevel|SD_RESET\(0) &
--- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal0~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110011001100000011001100110000000000110001000000000011000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal0~2_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\);
-
--- Location: LABCELL_X24_Y5_N54
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ = ( \SDCARD_MISO[0]~input_o\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ &
--- (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\))) ) ) ) # ( !\SDCARD_MISO[0]~input_o\ & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~1_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal12~0_combout\)) ) ) ) # ( \SDCARD_MISO[0]~input_o\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~42_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000001010000010100000000000100010000010100010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal12~0_combout\,
- datae => \ALT_INV_SDCARD_MISO[0]~input_o\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~42_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\);
-
--- Location: LABCELL_X24_Y6_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0)) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\ ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ & ( ((!\myVirtualToplevel|SD_RESET\(0) &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~40_combout\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~43_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~41_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111001011110000111100001111000011111010111110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~41_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~40_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~43_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44_combout\);
-
--- Location: FF_X24_Y6_N2
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~44_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\);
-
--- Location: LABCELL_X25_Y6_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ &
--- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\)))) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( (!\myVirtualToplevel|SD_RESET\(0) & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.DESELECT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~39_combout\)) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001010101010000000101010101000000010101000100000001010100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.DESELECT~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~39_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61_combout\);
-
--- Location: FF_X25_Y6_N25
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~61_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\);
-
--- Location: LABCELL_X26_Y5_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.TX_BITS~q\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.PULSE_SCLK~q\ &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000011000000110000001100000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.PULSE_SCLK~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.TX_BITS~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\);
-
--- Location: LABCELL_X25_Y6_N9
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\ = ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector29~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector29~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\);
-
--- Location: MLABCELL_X23_Y5_N15
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~0_combout\ &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|WideOr34~combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001010000010100000101000001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_mosi_o~0_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_WideOr34~combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\);
-
--- Location: MLABCELL_X23_Y5_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & ( (\SDCARD_MISO[0]~input_o\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~42_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~45_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.WR_WAIT~q\) # ((\SDCARD_MISO[0]~input_o\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|sclk_r~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110001111111111111111100000000000000011111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \ALT_INV_SDCARD_MISO[0]~input_o\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~45_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.WR_WAIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_sclk_r~DUPLICATE_q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.START_INIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v~42_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46_combout\);
-
--- Location: FF_X23_Y5_N7
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v~46_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\);
-
--- Location: LABCELL_X24_Y6_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~53_combout\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnState_v.START_INIT~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnState_v.START_INIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~53_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54_combout\);
-
--- Location: LABCELL_X24_Y7_N18
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]~2_combout\ & ((!\myVirtualToplevel|SD_HNDSHK_IN\(0))
--- # (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100100010001100110010001000110011000000000011001100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_HNDSHK_IN\(0),
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o[2]~2_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\);
-
--- Location: LABCELL_X25_Y6_N36
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~54_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ &
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\ & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\)) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~50_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~48_combout\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~49_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~51_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010101010101000100011101010111010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~51_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~48_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~54_combout\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~50_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o[3]~0_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~49_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55_combout\);
-
--- Location: FF_X25_Y6_N38
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~55_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\);
-
--- Location: LABCELL_X24_Y9_N0
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(0) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(0),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0_combout\);
-
--- Location: FF_X24_Y9_N2
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector15~0_combout\,
- asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0),
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(0));
-
--- Location: MLABCELL_X18_Y9_N39
-\myVirtualToplevel|IO_DATA_READ_SD[16]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ_SD[16]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(0),
- combout => \myVirtualToplevel|IO_DATA_READ_SD[16]~feeder_combout\);
-
--- Location: MLABCELL_X9_Y15_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\);
-
--- Location: FF_X9_Y15_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG785\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\);
-
--- Location: FF_X10_Y16_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG504\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\);
-
--- Location: FF_X10_Y18_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_NEW_REG781\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM782\);
-
--- Location: LABCELL_X10_Y18_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux26~2_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000000000000000110011111111110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux26~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector18~0_combout\);
-
--- Location: FF_X20_Y39_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_NEW_REG1434\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[0]_OTERM1435\);
-
--- Location: LABCELL_X12_Y17_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxState~54\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # ((\myVirtualToplevel|MEM_BUSY~1_combout\) #
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011011111111111111101111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\);
-
--- Location: LABCELL_X16_Y31_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\);
-
--- Location: MLABCELL_X13_Y38_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110000000000110011000000000011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\);
-
--- Location: LABCELL_X16_Y35_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111011111110111100000000000000001100110011101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0_combout\);
-
--- Location: LABCELL_X16_Y33_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000010000000000000001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\);
-
--- Location: LABCELL_X14_Y33_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644_BDD12645\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111001100110011001111110000111100000011000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644_BDD12645\);
-
--- Location: LABCELL_X14_Y33_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_RESYN12644_BDD12645\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011010000010100000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_RESYN12644_BDD12645\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\);
-
--- Location: LABCELL_X16_Y33_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000010100000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\);
-
--- Location: LABCELL_X16_Y33_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010100000000000001010000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\);
-
--- Location: LABCELL_X14_Y33_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\);
-
--- Location: LABCELL_X16_Y35_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010001010100010001001111111101010000010100000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\);
-
--- Location: LABCELL_X16_Y35_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111000000000000000000000000001010100000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\);
-
--- Location: LABCELL_X16_Y35_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector634~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111101001111010001010101000000001111010111110100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector634~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1_combout\);
-
--- Location: FF_X16_Y35_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\);
-
--- Location: LABCELL_X14_Y36_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\);
-
--- Location: LABCELL_X21_Y22_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\);
-
--- Location: LABCELL_X16_Y29_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector420~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector420~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\);
-
--- Location: LABCELL_X16_Y29_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1_combout\);
-
--- Location: LABCELL_X16_Y30_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010010100010111000011011110010000000010011110110000101011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\);
-
--- Location: LABCELL_X17_Y30_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr171~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011001110000000001100111000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr171~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\);
-
--- Location: LABCELL_X16_Y29_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector363~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~1_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000111010100000000011101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector363~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\);
-
--- Location: LABCELL_X16_Y29_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_NEW3341\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_OTERM3342\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1006~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110001001100110011000100110011000000000011001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1006~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_OTERM3342\);
-
--- Location: FF_X16_Y29_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid_OTERM3342\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y26_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.valid~q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000100000000000001010000000100000001000001010000010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.valid~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\);
-
--- Location: LABCELL_X12_Y32_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\);
-
--- Location: LABCELL_X12_Y38_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100000000000000010000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\);
-
--- Location: FF_X13_Y36_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\);
-
--- Location: MLABCELL_X13_Y36_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\)))) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100111110001010110011111000101011001111100010101111111110101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\);
-
--- Location: MLABCELL_X13_Y36_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[1]~55_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110100000000001111010000000000111111000000000011111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[1]~55_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12442_BDD12443\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\);
-
--- Location: MLABCELL_X13_Y36_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111011001110111000000000000000001111110011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~32_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\);
-
--- Location: MLABCELL_X13_Y36_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ & \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector502~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100000000000000010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_RESYN12444_BDD12445\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector502~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\);
-
--- Location: MLABCELL_X13_Y36_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) #
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111110111001111111100000000000000001101110011011100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4_combout\);
-
--- Location: FF_X13_Y36_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\);
-
--- Location: LABCELL_X10_Y35_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_WRITE~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110000001100000011000000110000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_WRITE~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\);
-
--- Location: LABCELL_X17_Y34_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~36_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101100000000001110111000000000111111000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~36_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\);
-
--- Location: LABCELL_X16_Y34_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001000111111001100000011111100100010001011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\);
-
--- Location: LABCELL_X17_Y34_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector700~1_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000111000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector700~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\);
-
--- Location: LABCELL_X17_Y34_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101111111110100010100000000000000001111111101000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1_combout\);
-
--- Location: FF_X17_Y34_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\);
-
--- Location: MLABCELL_X9_Y37_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\);
-
--- Location: LABCELL_X6_Y35_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READTOS~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011001000110010001100001111000011111010111110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\);
-
--- Location: LABCELL_X16_Y35_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000000010000010100000101000001010000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\);
-
--- Location: LABCELL_X14_Y38_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\)) ) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000010101010001100000000000000110000111111110011000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\);
-
--- Location: LABCELL_X14_Y38_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~56_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001110000011000000110000001100000011100000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~56_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8899_BDD8900\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\);
-
--- Location: LABCELL_X17_Y34_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111000001100000011100000111000001111000011000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\);
-
--- Location: LABCELL_X14_Y38_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111110001000111111111000100011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\);
-
--- Location: LABCELL_X14_Y36_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\);
-
--- Location: LABCELL_X14_Y38_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000110000001101000111110011111100111111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~8_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_RESYN12560_BDD12561\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\);
-
--- Location: LABCELL_X14_Y38_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\);
-
--- Location: LABCELL_X14_Y38_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100000001000100010000000100010001000100010001000100010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READWORDTOTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12646_BDD12647\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\);
-
--- Location: LABCELL_X14_Y38_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector568~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110111011101110100000000111111111111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN8901_BDD8902\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector568~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12650_BDD12651\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_RESYN12648_BDD12649\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_combout\);
-
--- Location: FF_X14_Y38_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\);
-
--- Location: LABCELL_X14_Y34_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011010101010101010100000000111111110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READBYTETOTOS~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READBYTETOTOS~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\);
-
--- Location: LABCELL_X16_Y36_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\);
-
--- Location: LABCELL_X16_Y36_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101011100000011010101110000001100000011000000110000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\);
-
--- Location: LABCELL_X16_Y36_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000000000111100000111000001110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\);
-
--- Location: LABCELL_X16_Y36_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\);
-
--- Location: LABCELL_X16_Y33_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100001111111111110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\);
-
--- Location: LABCELL_X16_Y35_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011110000000000001111000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\);
-
--- Location: LABCELL_X16_Y35_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_RESYN12640_BDD12641\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010111011000010110011001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_RESYN12640_BDD12641\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\);
-
--- Location: LABCELL_X16_Y36_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~4_combout\ & (
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111101111111111111110111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8531_BDD8532\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\);
-
--- Location: LABCELL_X16_Y36_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011111111110010001100110011001100111111111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_WRITE~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8535_BDD8536\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8533_BDD8534\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_RESYN8537_BDD8538\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_combout\);
-
--- Location: FF_X16_Y36_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\);
-
--- Location: LABCELL_X10_Y36_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITE~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011111111111100001111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITE~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\);
-
--- Location: LABCELL_X14_Y34_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001100000011110000111100001101000011000000110100001101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\);
-
--- Location: FF_X14_Y34_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y34_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000010100000000000111011001100110011101100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\);
-
--- Location: LABCELL_X14_Y34_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\
--- & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111000000000000000000000111000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\);
-
--- Location: LABCELL_X14_Y34_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector898~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100010001111101011111000100000000000000001111010111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector898~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0_combout\);
-
--- Location: FF_X14_Y34_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\);
-
--- Location: FF_X14_Y37_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\);
-
--- Location: LABCELL_X10_Y37_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\);
-
--- Location: MLABCELL_X13_Y37_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\
--- ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110011001101110000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9097_BDD9098\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\);
-
--- Location: LABCELL_X14_Y37_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011001100101010001111110010101000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_RESYN9099_BDD9100\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\);
-
--- Location: MLABCELL_X13_Y33_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\);
-
--- Location: LABCELL_X14_Y37_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001000000000000000000000000010101010000000001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8541_BDD8542\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_RESYN8543_BDD8544\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\);
-
--- Location: LABCELL_X14_Y37_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110111111101111111011111110111111101111111010000000011111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\);
-
--- Location: LABCELL_X14_Y37_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000000000111111111111111100110000000000000011001000100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3_combout\);
-
--- Location: FF_X14_Y37_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\);
-
--- Location: MLABCELL_X9_Y34_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITE~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITE~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\);
-
--- Location: FF_X13_Y39_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\);
-
--- Location: MLABCELL_X13_Y39_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~30_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011101110111111111010111010101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~30_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\);
-
--- Location: MLABCELL_X13_Y39_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\)) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001111111011000000111111001100000011101010110000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\);
-
--- Location: MLABCELL_X13_Y39_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector766~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111000000000000000000000010000010100000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector766~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\);
-
--- Location: MLABCELL_X13_Y39_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector964~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111110011101100111100000000000000001100111011001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector964~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0_combout\);
-
--- Location: FF_X13_Y39_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y34_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\)))) ) )
--- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101001100000000010100111111000001010011000011110101001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READBYTETOTOS~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READBYTETOTOS~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READBYTETOTOS~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\);
-
--- Location: MLABCELL_X13_Y32_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\);
-
--- Location: LABCELL_X12_Y17_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxState~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux4~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & !\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000010000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux4~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\);
-
--- Location: LABCELL_X12_Y17_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxState~55\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~55_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~54_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~53_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111011001111111111101100111111111110110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~54_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~53_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~55_combout\);
-
--- Location: FF_X12_Y17_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~55_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\);
-
--- Location: LABCELL_X17_Y16_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000000000000011000000000000111111000000000011111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\);
-
--- Location: LABCELL_X20_Y10_N9
-\myVirtualToplevel|Mux74~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux74~0_combout\ = ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ~q\ & ( (!\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~q\ & !\myVirtualToplevel|SD_STATE.SD_STATE_RESET_1~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\,
- datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET_1~q\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ~q\,
- combout => \myVirtualToplevel|Mux74~0_combout\);
-
--- Location: FF_X10_Y32_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\);
-
--- Location: FF_X10_Y34_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1404\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\);
-
--- Location: FF_X10_Y34_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1402\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\);
-
--- Location: LABCELL_X14_Y31_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100001000000000010000100000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\);
-
--- Location: LABCELL_X14_Y29_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000000000000001000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\);
-
--- Location: LABCELL_X14_Y33_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000011110000110000001111000010000000101000001000000010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\);
-
--- Location: LABCELL_X14_Y33_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000110011001000000011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\);
-
--- Location: LABCELL_X16_Y31_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\);
-
--- Location: LABCELL_X16_Y31_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\);
-
--- Location: LABCELL_X10_Y34_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector633~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000000000000010100000000000001010000010100000101000001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector633~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\);
-
--- Location: MLABCELL_X13_Y33_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\);
-
--- Location: LABCELL_X12_Y35_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\);
-
--- Location: MLABCELL_X9_Y34_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~54_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_RESYN12428_BDD12429\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010111011101000001011000010101010111111111010000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~54_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_RESYN12428_BDD12429\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\);
-
--- Location: LABCELL_X10_Y34_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector637~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector636~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010110000000000001011000000000000101000000000000010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector636~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector637~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0_combout\);
-
--- Location: FF_X10_Y34_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_NEW_REG1406\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\);
-
--- Location: LABCELL_X10_Y34_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001100101111111100110000001100000011001000110010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1405\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1403\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS_OTERM1407\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\);
-
--- Location: LABCELL_X14_Y33_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\);
-
--- Location: MLABCELL_X9_Y34_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\);
-
--- Location: MLABCELL_X9_Y34_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~51_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_RESYN12434_BDD12435\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111000000000101111111001100110011000000000001001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~51_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_RESYN12434_BDD12435\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_combout\);
-
--- Location: LABCELL_X16_Y35_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010000000100000001000000110011000100000011001100010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\);
-
--- Location: LABCELL_X10_Y34_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector567~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000000000001100000000000000110000001100000011000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector567~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0_combout\);
-
--- Location: MLABCELL_X9_Y34_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector570~2_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector571~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000010000011110000001000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector571~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector570~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0_combout\);
-
--- Location: FF_X9_Y34_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1360\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\);
-
--- Location: MLABCELL_X9_Y34_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110101111101011111010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\);
-
--- Location: FF_X9_Y34_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1362\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITETOINDADDR~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\);
-
--- Location: FF_X9_Y34_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_NEW_REG1358\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\);
-
--- Location: FF_X9_Y34_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\);
-
--- Location: MLABCELL_X9_Y34_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111110101000001000100010001001111111101010100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1361\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1363\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS_OTERM1359\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\);
-
--- Location: MLABCELL_X13_Y34_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\);
-
--- Location: MLABCELL_X9_Y34_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\);
-
--- Location: MLABCELL_X9_Y34_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_RESYN12432_BDD12433\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ &
--- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010100000101110111011000010101010101000001111111111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_RESYN12432_BDD12433\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_combout\);
-
--- Location: LABCELL_X10_Y34_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector501~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000000000000010100000000000001010000010100000101000001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector501~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0_combout\);
-
--- Location: LABCELL_X10_Y34_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector504~2_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~2_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101100001010000010110000101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector504~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0_combout\);
-
--- Location: FF_X10_Y34_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1366\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\);
-
--- Location: FF_X9_Y34_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1292\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_WRITE~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\);
-
--- Location: FF_X10_Y34_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1364\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\);
-
--- Location: MLABCELL_X13_Y34_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READBYTETOTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\);
-
--- Location: FF_X13_Y34_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_NEW_REG1368\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITETOINDADDR~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\);
-
--- Location: LABCELL_X10_Y34_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011111111000000100011001100000010111111110000001000000010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1367\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1365\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS_OTERM1369\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\);
-
--- Location: FF_X10_Y34_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1284\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\);
-
--- Location: FF_X10_Y34_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1286\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\);
-
--- Location: LABCELL_X17_Y35_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector699~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000000000000010100000000000001010000010100000101000001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector699~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0_combout\);
-
--- Location: LABCELL_X14_Y35_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\);
-
--- Location: LABCELL_X12_Y31_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001100000011000000110000001100000011000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\);
-
--- Location: LABCELL_X17_Y35_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_RESYN12430_BDD12431\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010111011101000001011000010101010111111111010000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_RESYN12430_BDD12431\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_combout\);
-
--- Location: LABCELL_X17_Y35_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector702~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector703~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010111010000000001011101000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector703~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector702~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3_combout\);
-
--- Location: FF_X17_Y35_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_NEW_REG1288\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector702~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\);
-
--- Location: LABCELL_X10_Y34_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\
--- & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110100001100010111010101110100001101000011000000110100001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1285\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1287\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS_OTERM1289\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\);
-
--- Location: LABCELL_X10_Y34_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001001000110100010101100111000010011010101111001101111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READADDTOTOS~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].cmd.MX_CMD_READADDTOTOS~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\);
-
--- Location: FF_X12_Y34_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG1055\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\);
-
--- Location: FF_X12_Y34_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_NEW_REG1370\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\);
-
--- Location: LABCELL_X12_Y32_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\);
-
--- Location: LABCELL_X17_Y32_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\);
-
--- Location: LABCELL_X17_Y35_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~47_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_RESYN12424_BDD12425\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000101000001010000011110011111111111010001010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~47_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_RESYN12424_BDD12425\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_combout\);
-
--- Location: LABCELL_X17_Y35_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector897~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000000000000010100000000000001010000010100000101000001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector897~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0_combout\);
-
--- Location: LABCELL_X17_Y35_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector900~2_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector901~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101100001010000010110000101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector901~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector900~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0_combout\);
-
--- Location: FF_X17_Y35_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_NEW_REG1372\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\);
-
--- Location: LABCELL_X12_Y34_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011101110111010101100000000000000001011101110101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM1056\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1371\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS_OTERM1373\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\);
-
--- Location: FF_X10_Y33_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1620\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\);
-
--- Location: LABCELL_X16_Y36_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITE~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100110011111111110011001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_WRITE~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\);
-
--- Location: FF_X16_Y36_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1622\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_WRITETOINDADDR~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\);
-
--- Location: LABCELL_X14_Y31_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\);
-
--- Location: LABCELL_X17_Y32_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\);
-
--- Location: LABCELL_X17_Y32_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_RESYN12420_BDD12421\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010100000000010111111101111111011111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_RESYN12420_BDD12421\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_combout\);
-
--- Location: LABCELL_X17_Y32_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000000000000010100000000000001010000010100000101000001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3_combout\);
-
--- Location: LABCELL_X17_Y32_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~5_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector769~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010111010000000001011101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector769~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0_combout\);
-
--- Location: FF_X17_Y32_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_NEW_REG1624\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\);
-
--- Location: LABCELL_X10_Y33_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\
--- & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\
--- & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001110101111000000111010101100000000101011110000000010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1621\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1623\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS_OTERM1625\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\);
-
--- Location: FF_X9_Y34_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_NEW_REG985\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\);
-
--- Location: LABCELL_X14_Y34_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\);
-
--- Location: MLABCELL_X9_Y34_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\);
-
--- Location: MLABCELL_X9_Y34_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_RESYN12426_BDD12427\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111110101010111111111010101000000000000000000011111100101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_RESYN12426_BDD12427\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_combout\);
-
--- Location: MLABCELL_X9_Y34_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector963~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000000000000010100000000000001010101000000000101010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector963~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0_combout\);
-
--- Location: MLABCELL_X9_Y34_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector966~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector967~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101100001010000010110000101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector967~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector966~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3_combout\);
-
--- Location: FF_X9_Y34_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1294\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector966~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\);
-
--- Location: FF_X9_Y34_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_NEW_REG1290\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\);
-
--- Location: MLABCELL_X9_Y34_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001100000000000000110011111111111111110000101000001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_WRITEHWORDTOADDR_OTERM986\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1295\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1293~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS_OTERM1291\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\);
-
--- Location: LABCELL_X14_Y33_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\);
-
--- Location: LABCELL_X10_Y33_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\);
-
--- Location: LABCELL_X10_Y33_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_RESYN12422_BDD12423\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010001000101011111000110010101111100011001010111110001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_RESYN12422_BDD12423\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\);
-
--- Location: LABCELL_X10_Y34_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~2_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector831~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010100000111100001010000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector831~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\);
-
--- Location: LABCELL_X10_Y34_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector768~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector835~0_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector834~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010000010100000101000000010000000000000001000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector768~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector834~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector835~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0_combout\);
-
--- Location: FF_X10_Y34_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1450\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\);
-
--- Location: MLABCELL_X13_Y38_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1211~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_WRITE~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000011000000110000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_WRITE~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1211~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\);
-
--- Location: FF_X13_Y38_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1452\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~1_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\);
-
--- Location: FF_X10_Y34_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_NEW_REG1448\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\);
-
--- Location: LABCELL_X10_Y34_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010001000100010011111111010100001111111101010100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1451\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1453\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM944\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM942~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS_OTERM1449\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\);
-
--- Location: LABCELL_X10_Y34_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000011010000000100111101001100011100110111000001111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].cmd.MX_CMD_READADDTOTOS~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].cmd.MX_CMD_READADDTOTOS~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].cmd.MX_CMD_READADDTOTOS~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\);
-
--- Location: LABCELL_X10_Y34_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\);
-
--- Location: LABCELL_X10_Y18_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxState~60\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~60_combout\ = ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux6~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) ) ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000000000000000000000000000100000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux6~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~60_combout\);
-
--- Location: LABCELL_X17_Y17_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxState~59\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~59_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) #
--- (\myVirtualToplevel|MEM_BUSY~1_combout\))) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1101111111111111110111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~59_combout\);
-
--- Location: LABCELL_X17_Y17_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxState~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxState~61_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~60_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~59_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~37_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~12_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal0~12_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101111110011000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal0~12_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~37_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~60_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~59_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~61_combout\);
-
--- Location: FF_X17_Y17_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxState~61_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\);
-
--- Location: LABCELL_X24_Y9_N48
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0_combout\ = (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ &
--- ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(9))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1)))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001110001011000000111000101100000011100010110000001110001011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(9),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0_combout\);
-
--- Location: FF_X24_Y9_N49
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector6~0_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(9));
-
--- Location: LABCELL_X21_Y9_N15
-\myVirtualToplevel|IO_DATA_READ_SD[25]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ_SD[25]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(9)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(9),
- combout => \myVirtualToplevel|IO_DATA_READ_SD[25]~feeder_combout\);
-
--- Location: LABCELL_X10_Y14_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[28]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[28]~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\);
-
--- Location: LABCELL_X16_Y16_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder_combout\);
-
--- Location: FF_X16_Y16_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[25]~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(25));
-
--- Location: LABCELL_X16_Y16_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[25]~feeder_combout\);
-
--- Location: MLABCELL_X4_Y24_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Div2~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Div2~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\);
-
--- Location: LABCELL_X7_Y24_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mod2~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mod2~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1243~6_combout\);
-
--- Location: LABCELL_X19_Y4_N51
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdAutoRefresh~q\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdIsReady~q\ & \myVirtualToplevel|RESET_n~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdIsReady~q\,
- datad => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdAutoRefresh~q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\);
-
--- Location: LABCELL_X19_Y11_N6
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~0_combout\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Equal5~0_combout\) # ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdBusy~q\ &
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_0~6_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010101010111010101010101011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_Equal5~0_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdBusy~q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_0~6_combout\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[31]~0_combout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3_combout\);
-
--- Location: FF_X19_Y11_N7
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[31]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\);
-
--- Location: FF_X19_Y12_N50
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_NEW_REG8\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\);
-
--- Location: LABCELL_X19_Y12_N0
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000100000000000000000000000000000001000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0),
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0_combout\);
-
--- Location: FF_X19_Y12_N2
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\);
-
--- Location: IOIBUF_X29_Y0_N35
-\SDRAM_DQ[0]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => SDRAM_DQ(0),
- o => \SDRAM_DQ[0]~input_o\);
-
--- Location: DDIOINCELL_X29_Y0_N48
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_NEW_REG10\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \SDRAM_DQ[0]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\);
-
--- Location: LABCELL_X19_Y12_N33
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\ ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\) ) ) ) # (
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM11\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]_OTERM9\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111000000000000111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM9\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]_OTERM11\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\);
-
--- Location: FF_X9_Y25_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~35_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\);
-
--- Location: FF_X10_Y25_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~32_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(12));
-
--- Location: LABCELL_X17_Y14_N27
-\myVirtualToplevel|MEM_DATA_READ[10]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ = ( \myVirtualToplevel|LessThan0~0_combout\ ) # ( !\myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23),
- dataf => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[10]~2_combout\);
-
--- Location: LABCELL_X20_Y18_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder_combout\);
-
--- Location: FF_X20_Y18_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~feeder_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\);
-
--- Location: FF_X20_Y18_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(10));
-
--- Location: LABCELL_X20_Y18_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(10) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[10]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001100000011000000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[10]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(10),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\);
-
--- Location: LABCELL_X12_Y25_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000101010001010100011111001100000000000000000000000011110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\);
-
--- Location: LABCELL_X12_Y25_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_RESYN8483_BDD8484\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000100000001000010011000100010001001100010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[18]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_RESYN8483_BDD8484\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\);
-
--- Location: LABCELL_X12_Y20_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_NEW3177\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_OTERM3178\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101010101001100110101010100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_OTERM3178\);
-
--- Location: FF_X12_Y20_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[10]_OTERM3178\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10));
-
--- Location: LABCELL_X12_Y25_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000010101010000000001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\);
-
--- Location: LABCELL_X12_Y25_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101011111010101010101111100000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\);
-
--- Location: LABCELL_X12_Y24_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\
--- & ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\))) ) )
--- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~1_combout\
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[26]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100010001000100110001000100010011000100110001001100010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[26]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\);
-
--- Location: LABCELL_X12_Y23_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_NEW3049\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_OTERM3050\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10)))))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_OTERM3050\);
-
--- Location: FF_X12_Y23_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[10]_OTERM3050\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10));
-
--- Location: MLABCELL_X13_Y29_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011011100110111001101110011011100000101000001010000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\);
-
--- Location: MLABCELL_X13_Y29_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)))) ) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000111111001100000011000000111010001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\);
-
--- Location: LABCELL_X12_Y20_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_NEW2985\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_OTERM2986\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000101000100011010111110111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_OTERM2986\);
-
--- Location: FF_X12_Y20_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[10]_OTERM2986\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10));
-
--- Location: LABCELL_X12_Y25_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\
--- & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000011100000111011100000000000000000100000001000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\);
-
--- Location: LABCELL_X12_Y25_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[26]~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_RESYN8487_BDD8488\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000010001000010001001100010001000100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[26]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_RESYN8487_BDD8488\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\);
-
--- Location: LABCELL_X12_Y20_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_NEW3113\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_OTERM3114\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_OTERM3114\);
-
--- Location: FF_X12_Y20_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[10]_OTERM3114\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10));
-
--- Location: LABCELL_X12_Y20_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(10)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(10))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(10)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100011101000111010001110100011100000000001100111100110011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(10),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(10),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(10),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\);
-
--- Location: LABCELL_X10_Y21_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_NEW2793\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_OTERM2794\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101010101000011110101010100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_OTERM2794\);
-
--- Location: FF_X10_Y21_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[10]_OTERM2794\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10));
-
--- Location: MLABCELL_X9_Y22_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_NEW2857\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_OTERM2858\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10)))))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_OTERM2858\);
-
--- Location: FF_X9_Y22_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[10]_OTERM2858\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10));
-
--- Location: LABCELL_X12_Y25_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111101011111000011110101111100000000010101010000000001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1_combout\);
-
--- Location: LABCELL_X12_Y25_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100011011000100010001000100010001101110110001000110111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\);
-
--- Location: LABCELL_X6_Y21_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_NEW2729\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_OTERM2730\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001001100011100110111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_OTERM2730\);
-
--- Location: FF_X6_Y21_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[10]_OTERM2730\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10));
-
--- Location: LABCELL_X12_Y25_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000011111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\);
-
--- Location: LABCELL_X12_Y22_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]~1_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100010001000111010001110100011101000100010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[18]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\);
-
--- Location: LABCELL_X6_Y21_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_NEW2921\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_OTERM2922\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000011000100011100111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_OTERM2922\);
-
--- Location: FF_X6_Y21_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[10]_OTERM2922\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10));
-
--- Location: LABCELL_X6_Y21_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10))))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(10) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(10)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(10))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100110001000011010011110111000001111100011100110111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(10),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(10),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(10),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\);
-
--- Location: MLABCELL_X9_Y16_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux95~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111110000111111111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux95~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2_combout\);
-
--- Location: MLABCELL_X9_Y14_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\);
-
--- Location: FF_X9_Y14_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10));
-
--- Location: MLABCELL_X13_Y10_N3
-\myVirtualToplevel|UART1|Equal7~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal7~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- combout => \myVirtualToplevel|UART1|Equal7~0_combout\);
-
--- Location: LABCELL_X19_Y17_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder_combout\);
-
--- Location: FF_X19_Y17_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~feeder_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\);
-
--- Location: FF_X20_Y15_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15));
-
--- Location: LABCELL_X19_Y17_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[15]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010000010100000101000001011111010111110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[15]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(15),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\);
-
--- Location: LABCELL_X6_Y21_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_NEW2925\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_OTERM2926\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000010100111111111101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_OTERM2926\);
-
--- Location: FF_X6_Y21_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[15]_OTERM2926\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15));
-
--- Location: LABCELL_X6_Y21_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_NEW2733\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_OTERM2734\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000101000000111111010111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_OTERM2734\);
-
--- Location: FF_X6_Y21_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[15]_OTERM2734\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15));
-
--- Location: MLABCELL_X9_Y22_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_NEW2861\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_OTERM2862\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15)))))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_OTERM2862\);
-
--- Location: FF_X9_Y22_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[15]_OTERM2862\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15));
-
--- Location: MLABCELL_X9_Y22_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_NEW2797\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_OTERM2798\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15)))))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_OTERM2798\);
-
--- Location: FF_X9_Y22_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[15]_OTERM2798\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15));
-
--- Location: LABCELL_X6_Y21_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(15)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(15))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(15)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101001101010011000000001111000001010011010100110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(15),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(15),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(15),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(15),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\);
-
--- Location: LABCELL_X7_Y22_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_NEW3117\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_OTERM3118\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_OTERM3118\);
-
--- Location: FF_X7_Y22_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[15]_OTERM3118\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15));
-
--- Location: LABCELL_X7_Y22_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_NEW3181\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_OTERM3182\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_OTERM3182\);
-
--- Location: FF_X7_Y22_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[15]_OTERM3182\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15));
-
--- Location: LABCELL_X7_Y22_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_NEW2989\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_OTERM2990\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000010000100111100111011011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_OTERM2990\);
-
--- Location: FF_X7_Y22_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[15]_OTERM2990\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15));
-
--- Location: LABCELL_X12_Y24_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_NEW3053\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_OTERM3054\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\
--- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101111101011111010100000011000000111111001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_OTERM3054\);
-
--- Location: FF_X12_Y24_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[15]_OTERM3054\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15));
-
--- Location: LABCELL_X7_Y22_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(15) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(15) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(15)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(15))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001010100010000001111010011101010010111100100101011111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(15),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(15),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(15),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(15),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\);
-
--- Location: LABCELL_X7_Y16_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux90~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000001111000011111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\);
-
--- Location: MLABCELL_X9_Y14_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux90~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder_combout\);
-
--- Location: FF_X9_Y14_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[15]~feeder_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15));
-
--- Location: MLABCELL_X18_Y9_N48
-\myVirtualToplevel|SD_ADDR[0][15]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_ADDR[0][15]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(15),
- combout => \myVirtualToplevel|SD_ADDR[0][15]~feeder_combout\);
-
--- Location: FF_X18_Y9_N49
-\myVirtualToplevel|SD_ADDR[0][15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_ADDR[0][15]~feeder_combout\,
- ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_ADDR[0][15]~q\);
-
--- Location: LABCELL_X19_Y9_N39
-\myVirtualToplevel|Mux68~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux68~0_combout\ = ( \myVirtualToplevel|SD_ADDR[0][15]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|SD_RESET\(0))) ) ) # ( !\myVirtualToplevel|SD_ADDR[0][15]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- \myVirtualToplevel|SD_RESET\(0))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100000001000000010000000110001001100010011000100110001001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ALT_INV_SD_RESET\(0),
- dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][15]~q\,
- combout => \myVirtualToplevel|Mux68~0_combout\);
-
--- Location: LABCELL_X21_Y15_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ & ( (((\myVirtualToplevel|MEM_BUSY~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\)) #
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ &
--- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & !\myVirtualToplevel|MEM_BUSY~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100000000000000010000000000001111111111111110111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\);
-
--- Location: LABCELL_X21_Y15_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|WideOr2~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111111110000111111111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr2~combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\);
-
--- Location: LABCELL_X21_Y15_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ &
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ &
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ &
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000010100000000000000000000010100000101000001010000010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\);
-
--- Location: LABCELL_X21_Y15_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ &
--- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) # (\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ &
--- (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\)) # (\myVirtualToplevel|MEM_BUSY~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~3_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~2_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000100110011001100110011001100110001000100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1_combout\);
-
--- Location: FF_X21_Y15_N22
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\);
-
--- Location: LABCELL_X19_Y9_N27
-\myVirtualToplevel|IO_DATA_READ_SD[31]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (\myVirtualToplevel|RESET_n~q\ & \myVirtualToplevel|SD_CS~combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000100000000000000010000000000000001000000000000000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datac => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_CS~combout\,
- combout => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\);
-
--- Location: FF_X19_Y9_N40
-\myVirtualToplevel|IO_DATA_READ_SD[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Mux68~0_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SD\(15));
-
--- Location: FF_X10_Y32_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_NEW_REG1408\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]~53_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[8]_OTERM1409\);
-
--- Location: LABCELL_X17_Y16_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000000000000000000110011001100110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\);
-
--- Location: LABCELL_X17_Y16_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ = (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010100000000010101010000000001010101000000000101010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\);
-
--- Location: LABCELL_X17_Y16_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101111100001111010111110000111101011111000000000101111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\);
-
--- Location: FF_X19_Y12_N5
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_NEW_REG40\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM41\);
-
--- Location: IOIBUF_X19_Y0_N52
-\SDRAM_DQ[7]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => SDRAM_DQ(7),
- o => \SDRAM_DQ[7]~input_o\);
-
--- Location: DDIOINCELL_X19_Y0_N65
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_NEW_REG42\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \SDRAM_DQ[7]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\);
-
--- Location: LABCELL_X19_Y12_N51
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM41\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM41\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111010000001011111111100000000111110100000010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM41\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM43\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]~22_combout\);
-
--- Location: FF_X13_Y14_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1));
-
--- Location: MLABCELL_X13_Y14_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux88~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111111101010000000000000101000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux88~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\);
-
--- Location: MLABCELL_X13_Y14_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100011111000100010001111100010001000100010001000100010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr116~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2_combout\);
-
--- Location: FF_X13_Y14_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~2_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\);
-
--- Location: FF_X6_Y26_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~59_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(6));
-
--- Location: FF_X10_Y25_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~47_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(5));
-
--- Location: LABCELL_X7_Y26_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100110011001100000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- cin => GND,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\);
-
--- Location: MLABCELL_X4_Y26_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\);
-
--- Location: LABCELL_X10_Y24_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|sp~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~49_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\);
-
--- Location: LABCELL_X6_Y26_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\);
-
--- Location: MLABCELL_X9_Y29_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\);
-
--- Location: LABCELL_X10_Y25_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111101011111111111110101111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\);
-
--- Location: LABCELL_X10_Y25_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|tInsnExec~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000000000000010100000000000001000000000000000100000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_tInsnExec~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\);
-
--- Location: LABCELL_X10_Y24_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|sp~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~49_sumout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|sp~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add21~49_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100001111001100110000111101010101000000000101010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~49_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~42_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~49_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\);
-
--- Location: LABCELL_X10_Y24_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) ) )
--- ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~43_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111111111111111111100000000000000001111111111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~43_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44_combout\);
-
--- Location: FF_X10_Y24_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[4]~44_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4));
-
--- Location: MLABCELL_X4_Y26_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~54\);
-
--- Location: MLABCELL_X4_Y26_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|sp~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~53_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~45_combout\);
-
--- Location: LABCELL_X6_Y26_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~54\);
-
--- Location: LABCELL_X7_Y26_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\);
-
--- Location: LABCELL_X19_Y12_N12
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle\(0) &
--- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|sdCycle[4]~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle\(0),
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[4]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_sdCycle[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0_combout\);
-
--- Location: FF_X19_Y12_N13
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG12\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\);
-
--- Location: IOIBUF_X24_Y0_N1
-\SDRAM_DQ[13]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => SDRAM_DQ(13),
- o => \SDRAM_DQ[13]~input_o\);
-
--- Location: DDIOINCELL_X24_Y0_N14
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_NEW_REG88\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \SDRAM_DQ[13]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\);
-
--- Location: FF_X21_Y13_N59
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_NEW_REG86\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\);
-
--- Location: LABCELL_X21_Y13_N6
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\ ) ) # (
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) #
--- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM89\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]_OTERM87\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000110000001111111100111111001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM89\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[29]_OTERM87\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[29]~27_combout\);
-
--- Location: FF_X16_Y14_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]_OTERM3336\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~DUPLICATE_q\);
-
--- Location: IOIBUF_X22_Y0_N52
-\SDRAM_DQ[2]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => SDRAM_DQ(2),
- o => \SDRAM_DQ[2]~input_o\);
-
--- Location: DDIOINCELL_X22_Y0_N65
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_NEW_REG32\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \SDRAM_DQ[2]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\);
-
--- Location: FF_X21_Y12_N19
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_NEW_REG64\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\);
-
--- Location: LABCELL_X21_Y12_N15
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\ ) ) # (
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) #
--- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]_OTERM65\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000110000001111111100111111001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM33\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[18]_OTERM65\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[18]~10_combout\);
-
--- Location: LABCELL_X24_Y9_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0_combout\ = (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(2))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010101000000000101010100000000010101010000000001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(2),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0_combout\);
-
--- Location: FF_X24_Y9_N14
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector13~0_combout\,
- asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(2),
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(2));
-
--- Location: MLABCELL_X18_Y9_N30
-\myVirtualToplevel|IO_DATA_READ_SD[18]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ_SD[18]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(2)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(2),
- combout => \myVirtualToplevel|IO_DATA_READ_SD[18]~feeder_combout\);
-
--- Location: FF_X10_Y15_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_NEW_REG921\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]_OTERM922\);
-
--- Location: IOIBUF_X24_Y0_N18
-\SDRAM_DQ[10]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => SDRAM_DQ(10),
- o => \SDRAM_DQ[10]~input_o\);
-
--- Location: DDIOINCELL_X24_Y0_N31
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_NEW_REG24\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \SDRAM_DQ[10]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\);
-
--- Location: FF_X20_Y12_N52
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_NEW_REG22\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM23\);
-
--- Location: LABCELL_X20_Y12_N30
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM23\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) #
--- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM23\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]_OTERM25\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000010001000000000001000111101110111111111110111011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM25\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[26]_OTERM23\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[26]~31_combout\);
-
--- Location: FF_X34_Y19_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1692~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(6));
-
--- Location: LABCELL_X35_Y19_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(20),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\);
-
--- Location: LABCELL_X35_Y20_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(20),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\);
-
--- Location: MLABCELL_X34_Y19_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~13_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add56~13_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000000000011001111001100111111111100110011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~13_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0_combout\);
-
--- Location: FF_X34_Y19_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1678~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(20));
-
--- Location: LABCELL_X35_Y20_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(21),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\);
-
--- Location: LABCELL_X35_Y19_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(21),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\);
-
--- Location: LABCELL_X35_Y20_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add56~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add44~5_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010101010000000001010101001010101111111110101010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0_combout\);
-
--- Location: FF_X35_Y20_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1677~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(21));
-
--- Location: LABCELL_X35_Y19_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add56~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add56~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(22),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add56~10\);
-
--- Location: FF_X35_Y20_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\);
-
--- Location: LABCELL_X35_Y20_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add44~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add44~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[22]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add44~10\);
-
--- Location: LABCELL_X35_Y20_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add44~9_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_DumpL1_1~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add56~9_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000001010000010110101111101011111010111110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_DumpL1_1~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add56~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add44~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0_combout\);
-
--- Location: FF_X35_Y20_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1676~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(22));
-
--- Location: FF_X10_Y25_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_NEW_REG893\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM894\);
-
--- Location: FF_X6_Y25_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_NEW_REG891\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]_OTERM892\);
-
--- Location: FF_X5_Y25_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_NEW_REG1176\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]_OTERM1177\);
-
--- Location: LABCELL_X17_Y28_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\);
-
--- Location: FF_X20_Y17_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(19));
-
--- Location: FF_X20_Y17_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE_q\);
-
--- Location: LABCELL_X20_Y17_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(19)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[19]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(19)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001100000000001100110000110011111111110011001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word[19]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\);
-
--- Location: FF_X20_Y17_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(18));
-
--- Location: LABCELL_X20_Y17_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[18]~feeder_combout\);
-
--- Location: LABCELL_X20_Y16_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadByteToTOS~q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadWordToTOS~DUPLICATE_q\)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101010101010000010101010101000001010101010100000101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadWordToTOS~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadByteToTOS~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\);
-
--- Location: FF_X19_Y15_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~25_sumout\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[18]~30_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(18));
-
--- Location: LABCELL_X12_Y15_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) # (
--- !\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(7)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(7),
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29_combout\);
-
--- Location: FF_X12_Y15_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG552\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~29_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM553\);
-
--- Location: LABCELL_X12_Y15_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\)))) ) ) ) #
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000110011000010100000101001011111001100110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]~10_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28_combout\);
-
--- Location: FF_X12_Y15_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG550\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~28_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM551\);
-
--- Location: FF_X12_Y15_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_NEW_REG548\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\);
-
--- Location: FF_X12_Y16_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_NEW_REG508\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\);
-
--- Location: LABCELL_X12_Y15_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM551\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM553\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM549\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM551\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]_OTERM553\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000011011111111110001101100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM553\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM551\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[7]_OTERM549\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[7]~10_combout\);
-
--- Location: LABCELL_X21_Y10_N21
-\myVirtualToplevel|Mux75~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux75~0_combout\ = ( !\myVirtualToplevel|SD_STATE.SD_STATE_READ_1~q\ & ( (\myVirtualToplevel|SD_STATE.SD_STATE_RESET~q\ & (!\myVirtualToplevel|SD_STATE.SD_STATE_WRITE_2~q\ & !\myVirtualToplevel|SD_STATE.SD_STATE_WRITE~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000000000000010100000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_RESET~q\,
- datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE_2~q\,
- datad => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_WRITE~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_1~q\,
- combout => \myVirtualToplevel|Mux75~0_combout\);
-
--- Location: LABCELL_X20_Y18_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[8]~feeder_combout\);
-
--- Location: LABCELL_X16_Y30_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Mult2~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Mult2~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\);
-
--- Location: LABCELL_X20_Y25_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\)))) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "on",
- lut_mask => "1111111111111111111111111111111101010001010101010101000101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\,
- datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~5_combout\);
-
--- Location: LABCELL_X29_Y26_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc~19_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1331~1_combout\);
-
--- Location: LABCELL_X25_Y25_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\);
-
--- Location: LABCELL_X26_Y24_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624_BDD12625\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~29_sumout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~37_sumout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~45_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110000010100000101000001010000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~37_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~45_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~29_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~49_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624_BDD12625\);
-
--- Location: LABCELL_X26_Y24_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~25_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_RESYN12624_BDD12625\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~17_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~33_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~13_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~9_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~17_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~33_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~13_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~9_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~25_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_RESYN12624_BDD12625\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\);
-
--- Location: LABCELL_X26_Y25_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(17) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010101000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[17]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(17),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~10\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\);
-
--- Location: LABCELL_X26_Y25_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[18]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[18]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[18]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[18]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\);
-
--- Location: LABCELL_X26_Y25_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[19]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[19]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[19]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\);
-
--- Location: LABCELL_X26_Y25_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(20) ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100110011001100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[20]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(20),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\);
-
--- Location: LABCELL_X26_Y25_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add1~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add1~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[21]~DUPLICATE_q\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[21]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[21]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[21]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add1~58\);
-
--- Location: LABCELL_X26_Y24_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~65_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~65_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~53_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5_combout\);
-
--- Location: LABCELL_X26_Y24_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628_BDD12629\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~69_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~61_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~93_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~93_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~69_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~61_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628_BDD12629\);
-
--- Location: LABCELL_X26_Y24_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~77_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_RESYN12628_BDD12629\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~85_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~73_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~89_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~81_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~85_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~73_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~89_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~81_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~77_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_RESYN12628_BDD12629\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_combout\);
-
--- Location: LABCELL_X26_Y24_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~1_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add1~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add1~57_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000100000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~1_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~5_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add1~57_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\);
-
--- Location: LABCELL_X12_Y24_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~26_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_multResult[31]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|multResult[31]~1_combout\);
-
--- Location: FF_X18_Y14_N32
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG4\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM5\);
-
--- Location: IOIBUF_X29_Y0_N52
-\SDRAM_DQ[1]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => SDRAM_DQ(1),
- o => \SDRAM_DQ[1]~input_o\);
-
--- Location: DDIOINCELL_X29_Y0_N65
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG6\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \SDRAM_DQ[1]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\);
-
--- Location: MLABCELL_X18_Y14_N39
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM5\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM7\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM5\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001010000011110000101000001111010111110000111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM5\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM7\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\);
-
--- Location: LABCELL_X12_Y9_N3
-\myVirtualToplevel|UART0|RX_ENABLE_FIFO~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_ENABLE_FIFO~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1),
- combout => \myVirtualToplevel|UART0|RX_ENABLE_FIFO~0_combout\);
-
--- Location: IOIBUF_X22_Y0_N35
-\SDRAM_DQ[5]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => SDRAM_DQ(5),
- o => \SDRAM_DQ[5]~input_o\);
-
--- Location: DDIOINCELL_X22_Y0_N48
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_NEW_REG56\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \SDRAM_DQ[5]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\);
-
--- Location: FF_X20_Y12_N43
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_NEW_REG74\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\);
-
--- Location: LABCELL_X21_Y12_N21
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\ ) ) # (
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\) #
--- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]_OTERM75\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000110000001111111100111111001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM57\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[21]_OTERM75\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[21]~5_combout\);
-
--- Location: LABCELL_X12_Y29_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr165~combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000000000000000000000000000001000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr165~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\);
-
--- Location: MLABCELL_X9_Y29_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010001111100010101000111110001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\);
-
--- Location: LABCELL_X14_Y32_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000111110100000000011111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\);
-
--- Location: LABCELL_X12_Y28_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001100000000000000110000000000010111010000000001011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3_combout\);
-
--- Location: LABCELL_X14_Y29_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|state~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~2_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000011111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\);
-
--- Location: LABCELL_X17_Y29_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000100000000000000010000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\);
-
--- Location: LABCELL_X12_Y28_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157_BDD9158\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111100110010101111101011111010111110001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157_BDD9158\);
-
--- Location: LABCELL_X14_Y29_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001000000000000000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\);
-
--- Location: LABCELL_X12_Y28_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\)
--- # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111110000111111111111000000110011001100000011001100110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\);
-
--- Location: LABCELL_X12_Y28_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100001111111111110000111111110000111111111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\);
-
--- Location: LABCELL_X12_Y28_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_BDD9162\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~39_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000001110000111100001111000011111111011101111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12598_BDD12599\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~39_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_RESYN12596_BDD12597\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_BDD9162\);
-
--- Location: LABCELL_X14_Y30_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000010000110001000010000001001011001000000101101111000000110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\);
-
--- Location: MLABCELL_X13_Y29_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001000000000000010000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\);
-
--- Location: MLABCELL_X13_Y30_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111111110000000011111111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\);
-
--- Location: MLABCELL_X13_Y30_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_RESYN8809_BDD8810\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100001111000000100000001000000000000011110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_RESYN8809_BDD8810\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\);
-
--- Location: MLABCELL_X13_Y30_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159_BDD9160\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~23_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110111011100000111011100000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~23_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159_BDD9160\);
-
--- Location: LABCELL_X12_Y28_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9161_BDD9162\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9159_BDD9160\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_RESYN9157_BDD9158\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~38_combout\))))
--- ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000010001000100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9157_BDD9158\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~38_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9161_BDD9162\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_RESYN9159_BDD9160\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_combout\);
-
--- Location: LABCELL_X12_Y28_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~5_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001100000011000011111111001100001111111100110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\);
-
--- Location: MLABCELL_X4_Y26_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010000010100000101011111010111110101111101011111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~65_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1072~0_combout\);
-
--- Location: FF_X6_Y26_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(9));
-
--- Location: LABCELL_X6_Y26_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\);
-
--- Location: LABCELL_X6_Y26_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(9),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~58\);
-
--- Location: LABCELL_X7_Y26_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\);
-
--- Location: LABCELL_X7_Y26_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\);
-
--- Location: LABCELL_X7_Y26_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\);
-
--- Location: LABCELL_X7_Y26_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\);
-
--- Location: MLABCELL_X4_Y26_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\);
-
--- Location: MLABCELL_X4_Y26_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\);
-
--- Location: MLABCELL_X4_Y26_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\);
-
--- Location: MLABCELL_X4_Y26_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|sp~48\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp~48_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~57_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~48_combout\);
-
--- Location: LABCELL_X6_Y26_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|sp~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~57_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp~48_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111010101010101010100001111000011110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~57_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~48_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\);
-
--- Location: LABCELL_X6_Y26_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) )
--- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~49_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001111111111000000111111111100000000111111000000000011111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(9),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~49_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50_combout\);
-
--- Location: FF_X6_Y26_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~50_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\);
-
--- Location: LABCELL_X7_Y26_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\);
-
--- Location: LABCELL_X7_Y26_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\);
-
--- Location: LABCELL_X12_Y29_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011011111000000001101111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\);
-
--- Location: LABCELL_X12_Y29_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000000000001100000000000000110011000000110011001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\);
-
--- Location: MLABCELL_X13_Y30_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100110000001000000000000000000001001100000010000100110000001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\);
-
--- Location: LABCELL_X7_Y18_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[0]~4_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Write~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[1]~3_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000100010001001100010001000100110000000100010011000000010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[1]~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Write~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[0]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0_combout\);
-
--- Location: FF_X9_Y24_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1330\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux97~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\);
-
--- Location: LABCELL_X10_Y17_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))
--- ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2MxAddrInCache~13_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100000101000110110000111100010001000000000001000100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~13_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2MxAddrInCache~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\);
-
--- Location: FF_X10_Y17_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_NEW_REG751\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\);
-
--- Location: FF_X7_Y16_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\);
-
--- Location: FF_X6_Y18_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1332\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\);
-
--- Location: LABCELL_X12_Y16_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder_combout\);
-
--- Location: FF_X12_Y16_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_NEW_REG1328\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\);
-
--- Location: LABCELL_X6_Y18_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1333\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1329\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]_OTERM1331\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100000000111110111111101000000001000001011111101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1331\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1333\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]_OTERM1329\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\);
-
--- Location: LABCELL_X6_Y18_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[8]~13_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110011000000001111001100001100111111110000110011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[8]~13_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[0]~2_combout\);
-
--- Location: LABCELL_X12_Y15_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) )
--- # ( !\myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[9]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[9]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33_combout\);
-
--- Location: FF_X12_Y15_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG540\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~33_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\);
-
--- Location: FF_X12_Y15_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG536\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\);
-
--- Location: FF_X10_Y30_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1526\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\);
-
--- Location: LABCELL_X12_Y29_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010100000101011111010000010101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\);
-
--- Location: MLABCELL_X9_Y30_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(9) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(9),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\);
-
--- Location: MLABCELL_X13_Y29_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000000000001100110000000010100000000000001111000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\);
-
--- Location: LABCELL_X10_Y30_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41_combout\);
-
--- Location: FF_X10_Y30_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1532\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~41_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1533\);
-
--- Location: MLABCELL_X13_Y32_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000000000000110000000000110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\);
-
--- Location: MLABCELL_X13_Y32_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437_BDD8438\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~28_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100010101000001010001010100001111000111110000111100011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~28_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437_BDD8438\);
-
--- Location: LABCELL_X12_Y31_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111101011111010111001100111111111100010011110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\);
-
--- Location: LABCELL_X12_Y31_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~17_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~29_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_RESYN12630_BDD12631\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100111100000000110011100000000000001111000011110000111000001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_RESYN12630_BDD12631\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~29_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~17_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_combout\);
-
--- Location: LABCELL_X10_Y28_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435_BDD8436\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001000000010000000100000001000000010000000101111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435_BDD8436\);
-
--- Location: LABCELL_X16_Y31_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000001010000010100000011000011110000011100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~18_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\);
-
--- Location: LABCELL_X10_Y28_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~7_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8435_BDD8436\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011111111111100001111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8435_BDD8436\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\);
-
--- Location: LABCELL_X10_Y28_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8437_BDD8438\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_RESYN8439_BDD8440\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000100010001000100010001000101111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8437_BDD8438\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_RESYN8439_BDD8440\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\);
-
--- Location: FF_X10_Y28_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1528\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\);
-
--- Location: LABCELL_X7_Y32_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~57_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010101011111111111111111010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~57_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0_combout\);
-
--- Location: FF_X7_Y32_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y29_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101110000011101010111000001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\);
-
--- Location: FF_X12_Y29_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_NEW_REG1530\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\);
-
--- Location: LABCELL_X10_Y30_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1533\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1529\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1531\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]_OTERM1527\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010100000101111101010101010101010101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1527\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1533\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1529\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]_OTERM1531\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\);
-
--- Location: LABCELL_X12_Y29_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101111000001011010111100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\);
-
--- Location: LABCELL_X14_Y28_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111001000000000011100100000000000000000000000000111001000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\);
-
--- Location: LABCELL_X10_Y30_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37_combout\);
-
--- Location: FF_X10_Y30_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1542\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~37_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1543\);
-
--- Location: FF_X10_Y30_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1536\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\);
-
--- Location: LABCELL_X12_Y29_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011010101110001001101010111000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\);
-
--- Location: FF_X12_Y29_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1540\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\);
-
--- Location: LABCELL_X14_Y29_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100000000001100110010001000100010000000000010001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\);
-
--- Location: LABCELL_X14_Y30_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010100001010000000001001001000000100000110100000001000011100110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\);
-
--- Location: LABCELL_X14_Y29_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010001000101010001000100010101000100010001010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0_combout\);
-
--- Location: LABCELL_X14_Y32_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100000001000000010000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\);
-
--- Location: LABCELL_X14_Y29_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000011000100110000001100010011000100110001001100010011000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\);
-
--- Location: LABCELL_X14_Y31_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000000000000110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\);
-
--- Location: LABCELL_X14_Y31_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~41_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~7_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110011111100101010001010100011111100000000001010100000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~41_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\);
-
--- Location: LABCELL_X14_Y29_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110111010100000111011101010000011101110101010101110111010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\);
-
--- Location: LABCELL_X14_Y29_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8783_BDD8784\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_RESYN8785_BDD8786\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~27_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~3_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101000100000000000000000000000001111001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~27_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8783_BDD8784\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_RESYN8785_BDD8786\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_combout\);
-
--- Location: LABCELL_X14_Y29_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~4_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~3_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1101110111011101110111011101110100000000110100000000000011010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\);
-
--- Location: FF_X14_Y29_N34
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_NEW_REG1538\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\);
-
--- Location: LABCELL_X10_Y30_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1541\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1543\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1539\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]_OTERM1537\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000001011111010100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1543\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1537\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1541\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]_OTERM1539\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\);
-
--- Location: FF_X10_Y30_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1378\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\);
-
--- Location: LABCELL_X12_Y29_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001100000011001000110000001100100010000000100010001000000010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\);
-
--- Location: FF_X12_Y29_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1382\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\);
-
--- Location: MLABCELL_X13_Y29_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100111000000000000000000000000001001110010011100000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\);
-
--- Location: MLABCELL_X13_Y29_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110011000000111111001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\);
-
--- Location: LABCELL_X10_Y30_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101001101010011010100110101001101010000010111110101000001011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42_combout\);
-
--- Location: FF_X10_Y30_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1384\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~42_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1385\);
-
--- Location: MLABCELL_X13_Y31_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~4_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011000000110000001111010111110000111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3_combout\);
-
--- Location: MLABCELL_X13_Y31_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~9_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110011111100111111000000000010101000101010001010100000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~9_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6_combout\);
-
--- Location: MLABCELL_X13_Y31_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~42_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000001011100110100000101111111110000010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~42_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4_combout\);
-
--- Location: LABCELL_X12_Y31_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5_combout\);
-
--- Location: MLABCELL_X13_Y31_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000010000000000000000000000000001000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\);
-
--- Location: MLABCELL_X13_Y31_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1350~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~31_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~7_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000001011100110100001111000011110000111111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1350~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~31_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8_combout\);
-
--- Location: MLABCELL_X13_Y31_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~6_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~5_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000000000000001000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~6_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\);
-
--- Location: MLABCELL_X13_Y31_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~2_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010000010100000101011111111111111110000101000001011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~9_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\);
-
--- Location: FF_X13_Y31_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_NEW_REG1380\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\);
-
--- Location: LABCELL_X10_Y30_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1383\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1385\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1381\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]_OTERM1379\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010101010101010101010000110000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1379\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1383\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1385\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]_OTERM1381\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\);
-
--- Location: FF_X10_Y30_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1560\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\);
-
--- Location: LABCELL_X12_Y29_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110101000001011111010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\);
-
--- Location: MLABCELL_X13_Y29_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000000100000001100000011000010100000000000001111000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\);
-
--- Location: LABCELL_X10_Y30_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40_combout\);
-
--- Location: FF_X10_Y30_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1566\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~40_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1567\);
-
--- Location: LABCELL_X12_Y29_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001100000011001000110000001100100010000000100010001000000010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\);
-
--- Location: FF_X12_Y29_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1564\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\);
-
--- Location: LABCELL_X14_Y31_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000010000000000000010100000001000100000000010001001000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\);
-
--- Location: LABCELL_X16_Y32_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111110000000000001111000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\);
-
--- Location: LABCELL_X14_Y31_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_RESYN8781_BDD8782\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000101010101000000000101010100010000000100000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_RESYN8781_BDD8782\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\);
-
--- Location: LABCELL_X14_Y31_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~40_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101011001000111110101100100000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~40_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7_combout\);
-
--- Location: LABCELL_X14_Y31_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011000000000000000000000001000000000001001100010110000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\);
-
--- Location: LABCELL_X14_Y29_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100000000000001010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1_combout\);
-
--- Location: LABCELL_X14_Y29_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\)))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111110001000111111111000100011111010100010001111101010001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\);
-
--- Location: LABCELL_X14_Y29_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110011111100111111001111110011111100000000001111110000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\);
-
--- Location: LABCELL_X14_Y29_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~25_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8431_BDD8432\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_RESYN8429_BDD8430\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111000001110101000000000000000001110000011101010111000001110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8431_BDD8432\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_RESYN8429_BDD8430\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~25_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\);
-
--- Location: LABCELL_X14_Y29_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~7_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector1348~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1011101110111011000000000000000010111011101110110000101100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1348~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\);
-
--- Location: FF_X13_Y29_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_NEW_REG1562\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\);
-
--- Location: LABCELL_X10_Y30_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1565\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1567\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1563\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]_OTERM1561\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101000011110011001101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1561\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1567\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1565\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]_OTERM1563\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\);
-
--- Location: LABCELL_X10_Y30_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[9]~43_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[9]~41_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[9]~38_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[9]~42_combout\))) ) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000100110000101010011011110001100101011101001110110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[9]~42_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[9]~38_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[9]~43_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[9]~41_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\);
-
--- Location: FF_X7_Y32_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1256\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1074~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\);
-
--- Location: LABCELL_X12_Y29_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010100000101011111010000010101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\);
-
--- Location: MLABCELL_X13_Y30_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000001000000010001000100010011000000000000001100110000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\);
-
--- Location: LABCELL_X6_Y32_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000101110000011000010111000011101001111110001110100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41_combout\);
-
--- Location: FF_X6_Y32_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1258\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~41_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1259\);
-
--- Location: FF_X6_Y32_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1250\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\);
-
--- Location: LABCELL_X14_Y31_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110111001100110011011100000000000001010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\);
-
--- Location: LABCELL_X10_Y32_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~5_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000011110000111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\);
-
--- Location: LABCELL_X12_Y32_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010000000000000101000001010101010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2_combout\);
-
--- Location: LABCELL_X12_Y32_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\);
-
--- Location: LABCELL_X12_Y32_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\
--- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_RESYN8443_BDD8444\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~34_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100111011101111111100001100000011000000111000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~34_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_RESYN8443_BDD8444\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_combout\);
-
--- Location: LABCELL_X12_Y32_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~5_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~8_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~35_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111101000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~35_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\);
-
--- Location: LABCELL_X14_Y31_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\);
-
--- Location: LABCELL_X14_Y31_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\)
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101000001010101010100000101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~19_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\);
-
--- Location: LABCELL_X14_Y31_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~12_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~6_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110000001100110011000000110011111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~12_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\);
-
--- Location: LABCELL_X10_Y31_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))))
--- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8801_BDD8802\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_RESYN8799_BDD8800\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~8_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010001000101010101000100010101010100010001010101010101000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~8_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8801_BDD8802\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_RESYN8799_BDD8800\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\);
-
--- Location: FF_X10_Y31_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1252\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\);
-
--- Location: LABCELL_X12_Y29_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101110000011101010111000001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\);
-
--- Location: FF_X12_Y29_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_NEW_REG1254\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\);
-
--- Location: LABCELL_X6_Y32_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\ )
--- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1259\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1253\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1255\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1251\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010111110101000000001111111100000011111100110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1259\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1251\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1253\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1255\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\);
-
--- Location: LABCELL_X12_Y29_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010000011111010101000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\);
-
--- Location: MLABCELL_X13_Y30_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010000000000010001000100010011000000000000001100000011000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\);
-
--- Location: LABCELL_X6_Y32_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000101110000011000010111000011101001111110001110100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40_combout\);
-
--- Location: FF_X6_Y32_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1426\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~40_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1427\);
-
--- Location: FF_X6_Y32_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1420\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\);
-
--- Location: LABCELL_X14_Y32_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000001111000000010000111100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\);
-
--- Location: LABCELL_X7_Y31_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111100111111001111111111111100001111001111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\);
-
--- Location: LABCELL_X7_Y31_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~19_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_RESYN8445_BDD8446\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111100111111001111110001010100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~19_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_RESYN8445_BDD8446\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_combout\);
-
--- Location: LABCELL_X14_Y31_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803_BDD8804\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~17_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110010101000111111001010100011001100100010001100110010001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~17_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803_BDD8804\);
-
--- Location: LABCELL_X14_Y30_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\);
-
--- Location: LABCELL_X14_Y31_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_RESYN9155_BDD9156\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100001101000001010000010100000000000000110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_RESYN9155_BDD9156\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\);
-
--- Location: MLABCELL_X13_Y31_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8803_BDD8804\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111010000000001111101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8803_BDD8804\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\);
-
--- Location: MLABCELL_X13_Y31_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|NOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~7_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001100110000000101111111110000010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\);
-
--- Location: MLABCELL_X13_Y31_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~37_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~3_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~44_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101011111010110010001111101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~44_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~37_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\);
-
--- Location: LABCELL_X7_Y31_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~5_combout\)))
--- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8805_BDD8806\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_RESYN8807_BDD8808\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010100000101010101010000010101010101000001010101010100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~7_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8805_BDD8806\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_RESYN8807_BDD8808\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\);
-
--- Location: FF_X7_Y31_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1422\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\);
-
--- Location: LABCELL_X12_Y29_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder10~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001100000011001000110000001100100010000000100010001000000010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder10~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\);
-
--- Location: FF_X12_Y29_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_NEW_REG1424\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\);
-
--- Location: LABCELL_X6_Y32_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\ )
--- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1427\)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1423\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1425\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]_OTERM1421\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101001011111000011110000111100011011000110110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1427\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1421\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1423\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]_OTERM1425\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\);
-
--- Location: FF_X6_Y32_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1276\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\);
-
--- Location: LABCELL_X12_Y29_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101010001100111010101000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\);
-
--- Location: MLABCELL_X13_Y30_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder9~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~16_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000011001000000000000000000001000000110010000100000011001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder9~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\);
-
--- Location: LABCELL_X6_Y32_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011010100000101000000110011001100110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44_combout\);
-
--- Location: FF_X6_Y32_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1282\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~44_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1283\);
-
--- Location: LABCELL_X7_Y30_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000000000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\);
-
--- Location: LABCELL_X7_Y30_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal139~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_RESYN8789_BDD8790\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000011111000000000000111100000000001000100000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_RESYN8789_BDD8790\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal139~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\);
-
--- Location: LABCELL_X14_Y32_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~0_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100000000001100110000000000110011000000010011001100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_WRITEBYTETOADDR~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\);
-
--- Location: MLABCELL_X13_Y30_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791_BDD8792\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(0)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx\(1))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoWriteIdx[2]~DUPLICATE_q\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111011111110111111111111111000000000111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx[2]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(1),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoWriteIdx\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791_BDD8792\);
-
--- Location: LABCELL_X7_Y28_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector505~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~33_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000000000000000000000111111110000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~33_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector505~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5_combout\);
-
--- Location: LABCELL_X7_Y30_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8791_BDD8792\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~10_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~5_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111000001100000011100000110000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~10_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8791_BDD8792\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\);
-
--- Location: MLABCELL_X13_Y30_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector464~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~14_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state~22_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Selector765~0_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110001010100111111000101010000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state~22_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector765~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~14_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector464~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\);
-
--- Location: MLABCELL_X13_Y30_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ &
--- ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_RESYN8441_BDD8442\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~7_combout\
--- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~43_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~11_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010100010101000111111001010100010101000000000001111110000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~7_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~43_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_RESYN8441_BDD8442\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~32_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\);
-
--- Location: LABCELL_X7_Y30_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~9_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_RESYN8795_BDD8796\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~11_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector1363~0_combout\)))
--- ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011000000110011001100000011001100110000001100110011001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~9_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1363~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_RESYN8795_BDD8796\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\);
-
--- Location: FF_X7_Y30_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1278\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\);
-
--- Location: LABCELL_X12_Y29_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~3_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder8~5_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001100000011001000110000001100100010000000100010001000000010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder8~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~15_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\);
-
--- Location: FF_X12_Y29_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_NEW_REG1280\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\);
-
--- Location: LABCELL_X6_Y32_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\ )
--- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1283\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1279\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1281\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]_OTERM1277\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011010100110101001100110011001100110000001111110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1277\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1283\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1279\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]_OTERM1281\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\);
-
--- Location: LABCELL_X6_Y32_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\
--- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~57_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~57_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111101010101000011110000000000001111010101010000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~57_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~57_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38_combout\);
-
--- Location: FF_X6_Y32_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1476\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~38_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1477\);
-
--- Location: FF_X7_Y32_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1470\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\);
-
--- Location: FF_X9_Y31_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1474\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\);
-
--- Location: FF_X12_Y28_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_NEW_REG1472\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\);
-
--- Location: LABCELL_X7_Y32_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]_OTERM1257\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1475\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1477\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1473\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]_OTERM1471\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100110011001100110000010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1477\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1471\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1475\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]_OTERM1257\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].cmd.MX_CMD_WRITEBYTETOADDR_OTERM940\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]_OTERM1473\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\);
-
--- Location: LABCELL_X6_Y32_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) # ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[9]~45_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[9]~39_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[9]~42_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[9]~41_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001000010011100010101001101101000110010101111100111011011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[9]~42_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[9]~41_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[9]~45_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[9]~39_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\);
-
--- Location: MLABCELL_X13_Y17_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111110000111111111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\);
-
--- Location: LABCELL_X12_Y15_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\)))) ) ) ) #
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100001011101000011000000110000101010011111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32_combout\);
-
--- Location: FF_X12_Y15_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_NEW_REG538\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~32_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\);
-
--- Location: LABCELL_X12_Y15_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\ & (
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM537\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM539\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]_OTERM541\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000100111111110011011100000000110001001111111111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM541\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM537\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[9]_OTERM539\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[9]~12_combout\);
-
--- Location: LABCELL_X16_Y15_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & ( \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & (
--- \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(10) & ( !\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010101001010101010101011111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(10),
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35_combout\);
-
--- Location: FF_X16_Y15_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG534\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~35_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\);
-
--- Location: FF_X14_Y14_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG530\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\);
-
--- Location: MLABCELL_X4_Y26_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\);
-
--- Location: MLABCELL_X4_Y26_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~61_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000000000000000011111111111111111100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~61_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\);
-
--- Location: MLABCELL_X9_Y30_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(10) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(10),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\);
-
--- Location: LABCELL_X12_Y27_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100001100001111110000110000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\);
-
--- Location: LABCELL_X12_Y27_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~42_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010011110111001101111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[10]~42_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43_combout\);
-
--- Location: FF_X12_Y27_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[10]~43_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10));
-
--- Location: LABCELL_X12_Y28_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000101110000011000010111000011101001111110001110100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\);
-
--- Location: LABCELL_X12_Y28_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~40_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000011000100011100111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[10]~40_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41_combout\);
-
--- Location: FF_X12_Y28_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[10]~41_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10));
-
--- Location: LABCELL_X5_Y30_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\);
-
--- Location: LABCELL_X5_Y30_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10)
--- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~46_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100000101101110111010111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[10]~46_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47_combout\);
-
--- Location: FF_X5_Y30_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[10]~47_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10));
-
--- Location: LABCELL_X5_Y30_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111010100000101000000000000111111110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\);
-
--- Location: LABCELL_X6_Y31_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~43_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000000000101110101111111100010101000000001011111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[10]~43_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44_combout\);
-
--- Location: FF_X6_Y31_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[10]~44_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10));
-
--- Location: LABCELL_X12_Y27_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(10) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(10) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(10) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(10) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000000001111111100110011001100110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(10),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(10),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(10),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(10),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\);
-
--- Location: LABCELL_X12_Y27_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\);
-
--- Location: LABCELL_X12_Y27_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~43_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10)
--- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010000000100111101110011011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[10]~43_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44_combout\);
-
--- Location: FF_X12_Y27_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[10]~44_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10));
-
--- Location: LABCELL_X12_Y27_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\);
-
--- Location: LABCELL_X12_Y27_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~39_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100010001110011111101110100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[10]~39_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40_combout\);
-
--- Location: FF_X12_Y27_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[10]~40_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10));
-
--- Location: LABCELL_X12_Y27_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110011000011110011001100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\);
-
--- Location: LABCELL_X12_Y27_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~42_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010011110111001101111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[10]~42_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43_combout\);
-
--- Location: FF_X12_Y27_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[10]~43_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10));
-
--- Location: LABCELL_X12_Y27_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~61_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add20~61_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010100110011010101010011001101010101000011110101010100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~61_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~61_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\);
-
--- Location: LABCELL_X12_Y27_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1073~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~44_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010001000000111101110111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1073~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[10]~44_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45_combout\);
-
--- Location: FF_X12_Y27_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[10]~45_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10));
-
--- Location: LABCELL_X12_Y27_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(10) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(10) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(10) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(10) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111001100110011001101010101010101010000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(10),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(10),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(10),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(10),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\);
-
--- Location: LABCELL_X12_Y27_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\);
-
--- Location: LABCELL_X14_Y14_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ &
--- (\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & (\myVirtualToplevel|MEM_DATA_READ[10]~119_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001101010101000011110000111100110011010101010011001101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]~13_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34_combout\);
-
--- Location: FF_X14_Y14_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_NEW_REG532\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\);
-
--- Location: LABCELL_X14_Y14_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM531\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM533\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM503\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]_OTERM535\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000010000110011111101111100100000001100001110111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM503\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM509~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM535\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM531\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[10]_OTERM533\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[10]~13_combout\);
-
--- Location: MLABCELL_X13_Y23_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_NEW3047\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_OTERM3048\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100110011000011110011001100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_OTERM3048\);
-
--- Location: FF_X13_Y23_N22
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[11]_OTERM3048\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11));
-
--- Location: LABCELL_X7_Y25_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_NEW3175\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_OTERM3176\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(11) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_OTERM3176\);
-
--- Location: FF_X7_Y25_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[11]_OTERM3176\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(11));
-
--- Location: LABCELL_X7_Y25_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_NEW3111\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_OTERM3112\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(11) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_OTERM3112\);
-
--- Location: FF_X7_Y25_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[11]_OTERM3112\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(11));
-
--- Location: LABCELL_X7_Y25_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_NEW2983\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_OTERM2984\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000001101011111111100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_OTERM2984\);
-
--- Location: FF_X7_Y25_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[11]_OTERM2984\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11));
-
--- Location: LABCELL_X7_Y25_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(11) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(11) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(11) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(11) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000011110000111101010101010101010000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(11),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(11),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(11),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(11),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\);
-
--- Location: LABCELL_X7_Y20_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_NEW2919\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_OTERM2920\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000011011111000111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_OTERM2920\);
-
--- Location: FF_X7_Y20_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[11]_OTERM2920\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11));
-
--- Location: LABCELL_X7_Y20_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_NEW2791\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_OTERM2792\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(11) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_OTERM2792\);
-
--- Location: FF_X7_Y20_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[11]_OTERM2792\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(11));
-
--- Location: LABCELL_X7_Y20_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_NEW2727\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_OTERM2728\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000111011111111100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_OTERM2728\);
-
--- Location: FF_X7_Y20_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[11]_OTERM2728\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11));
-
--- Location: MLABCELL_X9_Y20_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_NEW2855\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_OTERM2856\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(11),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_OTERM2856\);
-
--- Location: FF_X9_Y20_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[11]_OTERM2856\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11));
-
--- Location: LABCELL_X6_Y20_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(11)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(11) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(11))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(11)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001001110111000001010000010100100010011101111010111110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(11),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(11),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(11),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(11),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\);
-
--- Location: LABCELL_X6_Y18_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux94~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000001010000010110101111101011111010111110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\);
-
--- Location: MLABCELL_X9_Y14_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux94~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder_combout\);
-
--- Location: FF_X9_Y14_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[11]~feeder_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11));
-
--- Location: MLABCELL_X18_Y9_N24
-\myVirtualToplevel|SD_ADDR[0][11]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_ADDR[0][11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11),
- combout => \myVirtualToplevel|SD_ADDR[0][11]~feeder_combout\);
-
--- Location: FF_X18_Y9_N25
-\myVirtualToplevel|SD_ADDR[0][11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_ADDR[0][11]~feeder_combout\,
- ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_ADDR[0][11]~q\);
-
--- Location: LABCELL_X19_Y9_N9
-\myVirtualToplevel|Mux72~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux72~0_combout\ = ( \myVirtualToplevel|SD_ADDR[0][11]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- (\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) # ( !\myVirtualToplevel|SD_ADDR[0][11]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- (\myVirtualToplevel|SD_STATE.SD_STATE_READ_2~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000101000000000000010110101010000001011010101000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datac => \myVirtualToplevel|ALT_INV_SD_STATE.SD_STATE_READ_2~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][11]~q\,
- combout => \myVirtualToplevel|Mux72~0_combout\);
-
--- Location: FF_X19_Y9_N11
-\myVirtualToplevel|IO_DATA_READ_SD[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Mux72~0_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SD\(11));
-
--- Location: MLABCELL_X9_Y15_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\);
-
--- Location: LABCELL_X10_Y14_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ & ( (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) #
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\)) # (\myVirtualToplevel|MEM_BUSY~1_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ & ( (!\myVirtualToplevel|MEM_BUSY~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ &
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~0_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)
--- # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)) # (\myVirtualToplevel|MEM_BUSY~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010111111111111100100000000000000111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0_combout\);
-
--- Location: FF_X10_Y14_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\);
-
--- Location: MLABCELL_X9_Y15_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ & ( (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) #
--- (\myVirtualToplevel|MEM_BUSY~1_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & (!\myVirtualToplevel|MEM_BUSY~1_combout\ &
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~0_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\) #
--- (\myVirtualToplevel|MEM_BUSY~1_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001111111111111101000000000000000111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0_combout\);
-
--- Location: FF_X9_Y15_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\);
-
--- Location: FF_X19_Y12_N1
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_NEW_REG2\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux110~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\);
-
--- Location: IOIBUF_X25_Y0_N52
-\SDRAM_DQ[3]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => SDRAM_DQ(3),
- o => \SDRAM_DQ[3]~input_o\);
-
--- Location: DDIOINCELL_X25_Y0_N65
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_NEW_REG36\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \SDRAM_DQ[3]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\);
-
--- Location: FF_X18_Y13_N35
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_NEW_REG34\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM35\);
-
--- Location: MLABCELL_X18_Y13_N51
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM35\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\) #
--- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM35\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]_OTERM37\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000011000000000000001111111100111111111111110011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM37\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[3]_OTERM35\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[3]~24_combout\);
-
--- Location: MLABCELL_X9_Y26_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~49_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111111001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~49_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\);
-
--- Location: MLABCELL_X9_Y30_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\);
-
--- Location: LABCELL_X5_Y28_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0110011001100110011001100110011000000000111100000000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\);
-
--- Location: LABCELL_X5_Y28_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~33_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010011110111001101111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[4]~33_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34_combout\);
-
--- Location: FF_X5_Y28_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[4]~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4));
-
--- Location: MLABCELL_X4_Y29_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101101001011010010110100101101000110011001100110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\);
-
--- Location: LABCELL_X5_Y29_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~36_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010101101110101011111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[4]~36_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37_combout\);
-
--- Location: FF_X5_Y29_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[4]~37_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4));
-
--- Location: MLABCELL_X9_Y27_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\
--- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)
--- $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001111001100001100111100110001010000010100000101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\);
-
--- Location: MLABCELL_X9_Y27_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~37_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100000000111110111111101000000001000001011111101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[4]~37_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38_combout\);
-
--- Location: FF_X9_Y27_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[4]~38_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4));
-
--- Location: MLABCELL_X4_Y29_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111111110000001100110011001100001111111100000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\);
-
--- Location: MLABCELL_X4_Y29_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~38_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010001000000111101110111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[4]~38_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39_combout\);
-
--- Location: FF_X4_Y29_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[4]~39_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4));
-
--- Location: MLABCELL_X4_Y29_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(4) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(4) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(4) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(4) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011010101010101010100001111000011110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(4),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(4),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(4),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\);
-
--- Location: MLABCELL_X4_Y29_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010110101010001100110011001101010101101010100000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\);
-
--- Location: MLABCELL_X4_Y29_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ & (
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~40_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000000111111110100111100000000011100001111111101111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[4]~40_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41_combout\);
-
--- Location: FF_X4_Y29_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[4]~41_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4));
-
--- Location: MLABCELL_X4_Y29_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101101001011010001100110011001101011010010110100000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\);
-
--- Location: MLABCELL_X4_Y29_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~37_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000000111111101001111011100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[4]~37_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38_combout\);
-
--- Location: FF_X4_Y29_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[4]~38_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4));
-
--- Location: MLABCELL_X9_Y30_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111111111110000000001000111010001110100011101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\);
-
--- Location: MLABCELL_X9_Y30_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~36_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010011111111110101001100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[4]~36_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37_combout\);
-
--- Location: FF_X9_Y30_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[4]~37_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4));
-
--- Location: LABCELL_X6_Y27_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~49_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) $
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010110101010010101011010101000110000001100000011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~49_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\);
-
--- Location: LABCELL_X6_Y27_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\
--- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1079~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~34_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001001100011100110111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[4]~34_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1079~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35_combout\);
-
--- Location: FF_X6_Y27_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[4]~35_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4));
-
--- Location: MLABCELL_X4_Y29_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(4) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(4) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(4) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(4) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101001100110011001100000000111111110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(4),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(4),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(4),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\);
-
--- Location: MLABCELL_X4_Y29_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111111110000111100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\);
-
--- Location: LABCELL_X14_Y16_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux47~2_combout\ ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux47~2_combout\,
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\);
-
--- Location: LABCELL_X14_Y16_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux46~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux46~2_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\);
-
--- Location: LABCELL_X14_Y16_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\);
-
--- Location: LABCELL_X14_Y16_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux45~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add6~49_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001000001111000000100000111111010010110111111101001011011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~49_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux45~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\);
-
--- Location: LABCELL_X16_Y14_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4))))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[4]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector212~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(4) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010000101011111111111100010000101100000000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(4),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[4]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector212~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0_combout\);
-
--- Location: FF_X16_Y14_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0_combout\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(4));
-
--- Location: MLABCELL_X4_Y26_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001100000000001100110011111111110011001111111111001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~53_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\);
-
--- Location: MLABCELL_X9_Y30_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(5) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(5),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~54\);
-
--- Location: LABCELL_X5_Y30_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100000101111101010000010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\);
-
--- Location: LABCELL_X5_Y30_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~35_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010011110111001101111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[5]~35_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36_combout\);
-
--- Location: FF_X5_Y30_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[5]~36_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5));
-
--- Location: LABCELL_X5_Y29_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000101110000011000010111000011101001111110001110100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\);
-
--- Location: LABCELL_X5_Y29_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~38_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000010101101011101011111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[5]~38_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39_combout\);
-
--- Location: FF_X5_Y29_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[5]~39_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5));
-
--- Location: LABCELL_X10_Y28_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100100010011101110010001001110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\);
-
--- Location: LABCELL_X10_Y28_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\
--- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~39_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001001000111100110111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[5]~39_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40_combout\);
-
--- Location: FF_X10_Y28_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[5]~40_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5));
-
--- Location: LABCELL_X5_Y31_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001100000011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\);
-
--- Location: LABCELL_X5_Y31_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~40_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010000000101011011101010111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[5]~40_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41_combout\);
-
--- Location: FF_X5_Y31_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[5]~41_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5));
-
--- Location: LABCELL_X5_Y30_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(5) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(5) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(5) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(5) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000011110000111101010101010101010000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(5),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(5),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(5),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(5),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\);
-
--- Location: LABCELL_X6_Y30_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001101010000010111110101000001011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\);
-
--- Location: LABCELL_X6_Y30_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~38_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000010101101110101011111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[5]~38_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39_combout\);
-
--- Location: FF_X6_Y30_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[5]~39_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5));
-
--- Location: LABCELL_X5_Y30_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100001111010101010000111101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\);
-
--- Location: LABCELL_X5_Y30_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~42_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000111111111110100011100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[5]~42_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43_combout\);
-
--- Location: FF_X5_Y30_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[5]~43_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5));
-
--- Location: LABCELL_X6_Y30_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001101010000010111110101000001011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\);
-
--- Location: LABCELL_X6_Y30_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~36_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010000000101011011101010111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[5]~36_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37_combout\);
-
--- Location: FF_X6_Y30_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[5]~37_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5));
-
--- Location: LABCELL_X5_Y31_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~53_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~53_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001100000011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~53_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~53_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\);
-
--- Location: LABCELL_X5_Y31_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~39_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1078~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000000000101110101111111100010101000000001011111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1078~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[5]~39_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40_combout\);
-
--- Location: FF_X5_Y31_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[5]~40_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5));
-
--- Location: LABCELL_X5_Y30_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(5) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(5) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(5) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(5) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000011110000111100000000111111110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(5),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(5),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(5),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(5),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\);
-
--- Location: LABCELL_X5_Y30_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111110000111111111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\);
-
--- Location: LABCELL_X14_Y16_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\);
-
--- Location: LABCELL_X14_Y16_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add6~53_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux44~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101101000100000010110100010000001011111111110000101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux44~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~53_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\);
-
--- Location: LABCELL_X16_Y14_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5))))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[5]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector211~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001000000010111101011111111100000010101000100101010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[5]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector211~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0_combout\);
-
--- Location: FF_X16_Y14_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0_combout\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5));
-
--- Location: FF_X14_Y15_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_OTERM3329\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(12));
-
--- Location: MLABCELL_X4_Y26_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\);
-
--- Location: MLABCELL_X4_Y25_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\);
-
--- Location: LABCELL_X10_Y25_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(12)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|sp\(12) & \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000011111111111100001111111111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(12),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~33_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\);
-
--- Location: LABCELL_X7_Y26_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~34\);
-
--- Location: MLABCELL_X9_Y30_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add27~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\);
-
--- Location: MLABCELL_X9_Y29_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\);
-
--- Location: MLABCELL_X9_Y31_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111001000100010001000001111000011110111011101110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\);
-
--- Location: MLABCELL_X9_Y31_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~28_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100000011110111011100111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[12]~28_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29_combout\);
-
--- Location: FF_X9_Y31_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[12]~29_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12));
-
--- Location: MLABCELL_X9_Y31_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000000001111000000110011001100110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\);
-
--- Location: MLABCELL_X9_Y31_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ & (
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~30_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000100111111111111010000000000000001111111111111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[12]~30_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31_combout\);
-
--- Location: FF_X9_Y31_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[12]~31_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12));
-
--- Location: MLABCELL_X9_Y31_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\
--- & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000011000000111111001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\);
-
--- Location: MLABCELL_X9_Y31_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~25_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100100011110011011110111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[12]~25_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26_combout\);
-
--- Location: FF_X9_Y31_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[12]~26_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12));
-
--- Location: LABCELL_X10_Y28_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\);
-
--- Location: LABCELL_X10_Y28_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~29_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000010000111111111101110000000000000100111111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[12]~29_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30_combout\);
-
--- Location: FF_X10_Y28_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[12]~30_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12));
-
--- Location: LABCELL_X12_Y31_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(12) & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(12))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(12)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010100001111000000000011001101010101000011111111111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(12),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(12),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(12),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(12),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\);
-
--- Location: LABCELL_X6_Y30_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\);
-
--- Location: LABCELL_X6_Y30_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ & (
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~32_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001000000000111100101111111100000111000000001111011111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[12]~32_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33_combout\);
-
--- Location: FF_X6_Y30_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[12]~33_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12));
-
--- Location: LABCELL_X6_Y31_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101001001110000010100100111000011011010111110001101101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\);
-
--- Location: LABCELL_X6_Y31_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~28_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000000000101110101111111100010101000000001011111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[12]~28_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29_combout\);
-
--- Location: FF_X6_Y31_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[12]~29_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12));
-
--- Location: LABCELL_X6_Y30_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101001100000011000001010101010101010011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\);
-
--- Location: LABCELL_X7_Y30_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12)
--- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~29_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100010001101011111011101100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[12]~29_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30_combout\);
-
--- Location: FF_X7_Y30_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[12]~30_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12));
-
--- Location: LABCELL_X6_Y30_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~33_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~33_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001100000011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~33_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~33_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\);
-
--- Location: LABCELL_X6_Y30_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1071~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~26_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001001000111100110111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[12]~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1071~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27_combout\);
-
--- Location: FF_X6_Y30_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[12]~27_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12));
-
--- Location: LABCELL_X6_Y29_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(12) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(12) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(12) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(12) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101000011110000111100000000111111110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(12),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(12),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(12),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(12),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\);
-
--- Location: LABCELL_X10_Y19_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111111110000111100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\);
-
--- Location: LABCELL_X14_Y16_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux43~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux43~2_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\);
-
--- Location: LABCELL_X14_Y16_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux42~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux42~2_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\);
-
--- Location: LABCELL_X14_Y16_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux41~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux41~2_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\);
-
--- Location: LABCELL_X14_Y16_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux40~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux40~2_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\);
-
--- Location: LABCELL_X14_Y16_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux39~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux39~2_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\);
-
--- Location: LABCELL_X14_Y16_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux38~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux38~2_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\);
-
--- Location: LABCELL_X14_Y15_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add6~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add6~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add6~34\);
-
--- Location: LABCELL_X14_Y15_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\)))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux37~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_TOSNOS~q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add6~33_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101001011111000010100101111101000110010101110100011001010111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_TOSNOS~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux37~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add6~33_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\);
-
--- Location: LABCELL_X14_Y15_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[12]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector204~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~0_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000100111111110011111100001100010001000011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[12]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx[12]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\);
-
--- Location: LABCELL_X14_Y15_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_NEW3328\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_OTERM3329\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(12))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) # ((\myVirtualToplevel|MEM_DATA_READ[12]~147_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector204~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ &
--- (\myVirtualToplevel|MEM_DATA_READ[12]~147_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[16]~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector204~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_OTERM3329\);
-
--- Location: FF_X14_Y15_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]_OTERM3329\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[12]~DUPLICATE_q\);
-
--- Location: MLABCELL_X4_Y25_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\);
-
--- Location: MLABCELL_X4_Y25_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\);
-
--- Location: MLABCELL_X9_Y25_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add19~41_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010000010100000101000011111010111110101111101011111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~41_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\);
-
--- Location: LABCELL_X7_Y26_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~42\);
-
--- Location: MLABCELL_X9_Y29_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add27~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(13) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(13),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\);
-
--- Location: MLABCELL_X9_Y29_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add27~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add27~42\);
-
--- Location: LABCELL_X6_Y27_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110011000011110011001100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\);
-
--- Location: LABCELL_X6_Y27_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~32_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100000011110111011100111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~32_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr[14]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33_combout\);
-
--- Location: FF_X6_Y27_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr[14]~33_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14));
-
--- Location: LABCELL_X7_Y27_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~13_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~12_combout\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~13_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\);
-
--- Location: LABCELL_X7_Y27_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~11_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~34_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[3]~10_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010000000100111101110011011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[14]~34_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr[3]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35_combout\);
-
--- Location: FF_X7_Y27_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr[14]~35_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14));
-
--- Location: LABCELL_X7_Y27_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~12_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\);
-
--- Location: LABCELL_X7_Y27_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~33_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14)
--- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[16]~9_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000100000101011010111010111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~10_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[14]~33_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr[16]~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34_combout\);
-
--- Location: FF_X7_Y27_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[14]~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14));
-
--- Location: LABCELL_X6_Y27_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~7_combout\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\);
-
--- Location: LABCELL_X6_Y27_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[23]~6_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~29_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100000011110111011100111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[14]~29_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr[23]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30_combout\);
-
--- Location: FF_X6_Y27_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr[14]~30_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14));
-
--- Location: LABCELL_X7_Y27_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].addr\(14) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr\(14) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].addr\(14) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].addr\(14) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101000000001111111100001111000011110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].addr\(14),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].addr\(14),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].addr\(14),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].addr\(14),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\);
-
--- Location: LABCELL_X6_Y27_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~9_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~8_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001101010000010100000101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\);
-
--- Location: LABCELL_X6_Y27_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~30_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[15]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010000000100111101110011011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[14]~30_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr[15]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31_combout\);
-
--- Location: FF_X6_Y27_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr[14]~31_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14));
-
--- Location: LABCELL_X7_Y27_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~11_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100001111000000000000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~11_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\);
-
--- Location: LABCELL_X7_Y27_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14) &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~8_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[11]~9_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~32_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000011111101011111001100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[14]~32_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~9_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr[11]~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33_combout\);
-
--- Location: FF_X7_Y27_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr[14]~33_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14));
-
--- Location: LABCELL_X7_Y27_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~15_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~15_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~14_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\);
-
--- Location: LABCELL_X7_Y27_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14)
--- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~12_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[22]~13_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~36_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000101000101101010111110111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~13_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[14]~36_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr[22]~12_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37_combout\);
-
--- Location: FF_X7_Y27_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr[14]~37_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14));
-
--- Location: MLABCELL_X9_Y28_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~12_combout\) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add27~41_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~41_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000011110000000000110011001100110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~41_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add27~41_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\);
-
--- Location: MLABCELL_X9_Y28_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14)
--- & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~9_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].cmd.MX_CMD_READTOS~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector1069~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[22]~10_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~33_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000010101101011101011111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].cmd.MX_CMD_READTOS~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~10_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1069~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[14]~33_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr[22]~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34_combout\);
-
--- Location: FF_X9_Y28_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr[14]~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14));
-
--- Location: LABCELL_X7_Y27_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].addr\(14) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].addr\(14) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].addr\(14) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].addr\(14) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000000001111111101010101010101010011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].addr\(14),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].addr\(14),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].addr\(14),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].addr\(14),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\);
-
--- Location: LABCELL_X7_Y27_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux35~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux35~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux35~2_combout\);
-
--- Location: MLABCELL_X4_Y25_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Idle~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~37_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111110101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~37_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Idle~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1070~0_combout\);
-
--- Location: FF_X20_Y18_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(13));
-
--- Location: LABCELL_X20_Y18_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder_combout\);
-
--- Location: FF_X20_Y18_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[13]~feeder_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13));
-
--- Location: LABCELL_X20_Y18_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(13)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(13) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(13) & \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(13),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\);
-
--- Location: LABCELL_X12_Y22_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_NEW2979\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_OTERM2980\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000001001111111111100100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_OTERM2980\);
-
--- Location: FF_X12_Y22_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[13]_OTERM2980\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13));
-
--- Location: MLABCELL_X13_Y22_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_NEW3171\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_OTERM3172\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_OTERM3172\);
-
--- Location: FF_X13_Y22_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[13]_OTERM3172\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13));
-
--- Location: LABCELL_X12_Y22_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_NEW3043\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_OTERM3044\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(13) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_OTERM3044\);
-
--- Location: FF_X12_Y22_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[13]_OTERM3044\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(13));
-
--- Location: LABCELL_X12_Y22_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_NEW3107\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_OTERM3108\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_OTERM3108\);
-
--- Location: FF_X12_Y22_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[13]_OTERM3108\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13));
-
--- Location: LABCELL_X12_Y22_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(13) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(13)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(13) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(13))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(13)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100001111001100110000111100000000010101011111111101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(13),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(13),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\);
-
--- Location: LABCELL_X12_Y22_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_NEW2851\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_OTERM2852\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(13) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_OTERM2852\);
-
--- Location: FF_X12_Y22_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[13]_OTERM2852\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(13));
-
--- Location: LABCELL_X12_Y22_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_NEW2723\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_OTERM2724\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000001101011111111100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_OTERM2724\);
-
--- Location: FF_X12_Y22_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[13]_OTERM2724\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13));
-
--- Location: LABCELL_X12_Y22_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_NEW2915\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_OTERM2916\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000010000001111111001011110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_OTERM2916\);
-
--- Location: FF_X12_Y22_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[13]_OTERM2916\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13));
-
--- Location: LABCELL_X12_Y22_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_NEW2787\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_OTERM2788\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_OTERM2788\);
-
--- Location: FF_X12_Y22_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[13]_OTERM2788\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13));
-
--- Location: LABCELL_X12_Y22_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(13)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(13) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(13) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(13)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(13))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100110011000011110011001101010101000000000101010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(13),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(13),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(13),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(13),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\);
-
--- Location: MLABCELL_X9_Y20_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux92~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux92~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2_combout\);
-
--- Location: FF_X9_Y14_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13));
-
--- Location: MLABCELL_X18_Y9_N18
-\myVirtualToplevel|SD_ADDR[0][13]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_ADDR[0][13]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(13),
- combout => \myVirtualToplevel|SD_ADDR[0][13]~feeder_combout\);
-
--- Location: FF_X18_Y9_N20
-\myVirtualToplevel|SD_ADDR[0][13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_ADDR[0][13]~feeder_combout\,
- ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_ADDR[0][13]~q\);
-
--- Location: MLABCELL_X18_Y9_N12
-\myVirtualToplevel|Mux70~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux70~0_combout\ = ( \myVirtualToplevel|SD_RD\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SD_ADDR[0][13]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)
--- & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) # ( !\myVirtualToplevel|SD_RD\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SD_ADDR[0][13]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000000000000011000000000000001100001100110000110000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][13]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ALT_INV_SD_RD\(0),
- combout => \myVirtualToplevel|Mux70~0_combout\);
-
--- Location: FF_X18_Y9_N13
-\myVirtualToplevel|IO_DATA_READ_SD[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Mux70~0_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SD\(13));
-
--- Location: LABCELL_X19_Y18_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder_combout\);
-
--- Location: FF_X19_Y18_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~feeder_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[5]~DUPLICATE_q\);
-
--- Location: LABCELL_X21_Y11_N57
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]~17_combout\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder_combout\);
-
--- Location: FF_X21_Y11_N58
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_NEW_REG54\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\);
-
--- Location: LABCELL_X21_Y11_N30
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\ ) ) # (
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) #
--- (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM57\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]_OTERM55\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000011001111111111110011001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM57\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[5]_OTERM55\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[5]~17_combout\);
-
--- Location: FF_X16_Y14_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector212~0_combout\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\);
-
--- Location: FF_X16_Y14_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector211~0_combout\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\);
-
--- Location: FF_X16_Y14_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector205~0_combout\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11));
-
--- Location: M10K_X22_Y18_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 5,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 5,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a13_PORTBDATAOUT_bus\);
-
--- Location: FF_X18_Y14_N7
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y14_N54
-\myVirtualToplevel|INT_ENABLE[16]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|INT_ENABLE[16]~0_combout\ = (\myVirtualToplevel|INTR0_CS~combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000101000000000000010100000000000001010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- combout => \myVirtualToplevel|INT_ENABLE[16]~0_combout\);
-
--- Location: FF_X17_Y14_N10
-\myVirtualToplevel|INT_ENABLE[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|INT_ENABLE\(5));
-
--- Location: LABCELL_X16_Y14_N51
-\myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\ = ( \myVirtualToplevel|INTR0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111100000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\,
- dataf => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\,
- combout => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\);
-
--- Location: FF_X20_Y14_N56
-\myVirtualToplevel|IO_DATA_READ_INTRCTL[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|INT_ENABLE\(5),
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- sload => VCC,
- ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(5));
-
--- Location: MLABCELL_X9_Y12_N30
-\myVirtualToplevel|Add4~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add4~33_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|Add4~34\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(0),
- cin => GND,
- sumout => \myVirtualToplevel|Add4~33_sumout\,
- cout => \myVirtualToplevel|Add4~34\);
-
--- Location: LABCELL_X10_Y15_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder_combout\);
-
--- Location: FF_X10_Y15_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[2]~feeder_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2));
-
--- Location: LABCELL_X10_Y11_N0
-\myVirtualToplevel|Add3~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add3~17_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|Add3~18\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(0),
- cin => GND,
- sumout => \myVirtualToplevel|Add3~17_sumout\,
- cout => \myVirtualToplevel|Add3~18\);
-
--- Location: LABCELL_X10_Y11_N45
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ = ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101000000000101010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\,
- combout => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\);
-
--- Location: MLABCELL_X13_Y10_N36
-\myVirtualToplevel|UART1|Mux0~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Mux0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- combout => \myVirtualToplevel|UART1|Mux0~0_combout\);
-
--- Location: LABCELL_X10_Y11_N24
-\myVirtualToplevel|RTC_TICK_HALT~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_TICK_HALT~0_combout\ = ( \myVirtualToplevel|RTC_TICK_HALT~q\ & ( \myVirtualToplevel|UART1|Mux0~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\) # ((!\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|RTC_TICK_HALT~q\ & ( \myVirtualToplevel|UART1|Mux0~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\))) ) ) ) # (
--- \myVirtualToplevel|RTC_TICK_HALT~q\ & ( !\myVirtualToplevel|UART1|Mux0~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000101111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_RTC_TICK_HALT~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\,
- combout => \myVirtualToplevel|RTC_TICK_HALT~0_combout\);
-
--- Location: FF_X10_Y11_N26
-\myVirtualToplevel|RTC_TICK_HALT\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_TICK_HALT~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_TICK_HALT~q\);
-
--- Location: LABCELL_X10_Y11_N51
-\myVirtualToplevel|RTC_MICROSEC_TICK[1]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\ = ( \myVirtualToplevel|RTC_TICK_HALT~q\ ) # ( !\myVirtualToplevel|RTC_TICK_HALT~q\ & ( !\myVirtualToplevel|Equal13~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal13~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_TICK_HALT~q\,
- combout => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\);
-
--- Location: LABCELL_X10_Y11_N54
-\myVirtualToplevel|RTC_MICROSEC_TICK[1]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|Equal13~1_combout\) # ((!\myVirtualToplevel|RTC_TICK_HALT~q\) # (\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\))
--- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|Equal13~1_combout\) # (!\myVirtualToplevel|RTC_TICK_HALT~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101011111010111110101111101011111010111111111111101011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal13~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_TICK_HALT~q\,
- datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\,
- combout => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\);
-
--- Location: FF_X10_Y11_N38
-\myVirtualToplevel|RTC_MICROSEC_TICK[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|Add3~17_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\,
- sload => VCC,
- ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MICROSEC_TICK\(0));
-
--- Location: LABCELL_X10_Y11_N3
-\myVirtualToplevel|Add3~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add3~1_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add3~18\ ))
--- \myVirtualToplevel|Add3~2\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add3~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(1),
- cin => \myVirtualToplevel|Add3~18\,
- sumout => \myVirtualToplevel|Add3~1_sumout\,
- cout => \myVirtualToplevel|Add3~2\);
-
--- Location: FF_X10_Y11_N5
-\myVirtualToplevel|RTC_MICROSEC_TICK[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add3~1_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\,
- ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MICROSEC_TICK\(1));
-
--- Location: LABCELL_X10_Y11_N6
-\myVirtualToplevel|Add3~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add3~21_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add3~2\ ))
--- \myVirtualToplevel|Add3~22\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add3~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(2),
- cin => \myVirtualToplevel|Add3~2\,
- sumout => \myVirtualToplevel|Add3~21_sumout\,
- cout => \myVirtualToplevel|Add3~22\);
-
--- Location: FF_X10_Y11_N8
-\myVirtualToplevel|RTC_MICROSEC_TICK[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add3~21_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\,
- ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MICROSEC_TICK\(2));
-
--- Location: LABCELL_X10_Y11_N9
-\myVirtualToplevel|Add3~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add3~5_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add3~22\ ))
--- \myVirtualToplevel|Add3~6\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add3~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(3),
- cin => \myVirtualToplevel|Add3~22\,
- sumout => \myVirtualToplevel|Add3~5_sumout\,
- cout => \myVirtualToplevel|Add3~6\);
-
--- Location: FF_X10_Y11_N11
-\myVirtualToplevel|RTC_MICROSEC_TICK[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add3~5_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\,
- ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MICROSEC_TICK\(3));
-
--- Location: LABCELL_X10_Y11_N12
-\myVirtualToplevel|Add3~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add3~9_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add3~6\ ))
--- \myVirtualToplevel|Add3~10\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add3~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(4),
- cin => \myVirtualToplevel|Add3~6\,
- sumout => \myVirtualToplevel|Add3~9_sumout\,
- cout => \myVirtualToplevel|Add3~10\);
-
--- Location: FF_X10_Y11_N14
-\myVirtualToplevel|RTC_MICROSEC_TICK[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add3~9_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\,
- ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MICROSEC_TICK\(4));
-
--- Location: LABCELL_X10_Y11_N15
-\myVirtualToplevel|Add3~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add3~25_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add3~10\ ))
--- \myVirtualToplevel|Add3~26\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add3~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(5),
- cin => \myVirtualToplevel|Add3~10\,
- sumout => \myVirtualToplevel|Add3~25_sumout\,
- cout => \myVirtualToplevel|Add3~26\);
-
--- Location: FF_X10_Y11_N17
-\myVirtualToplevel|RTC_MICROSEC_TICK[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add3~25_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\,
- ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MICROSEC_TICK\(5));
-
--- Location: LABCELL_X10_Y11_N18
-\myVirtualToplevel|Add3~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add3~29_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add3~26\ ))
--- \myVirtualToplevel|Add3~30\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add3~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(6),
- cin => \myVirtualToplevel|Add3~26\,
- sumout => \myVirtualToplevel|Add3~29_sumout\,
- cout => \myVirtualToplevel|Add3~30\);
-
--- Location: FF_X10_Y11_N20
-\myVirtualToplevel|RTC_MICROSEC_TICK[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add3~29_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\,
- ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MICROSEC_TICK\(6));
-
--- Location: LABCELL_X10_Y11_N21
-\myVirtualToplevel|Add3~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add3~13_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add3~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(7),
- cin => \myVirtualToplevel|Add3~30\,
- sumout => \myVirtualToplevel|Add3~13_sumout\);
-
--- Location: FF_X10_Y11_N23
-\myVirtualToplevel|RTC_MICROSEC_TICK[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add3~13_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~0_combout\,
- ena => \myVirtualToplevel|RTC_MICROSEC_TICK[1]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MICROSEC_TICK\(7));
-
--- Location: LABCELL_X10_Y11_N48
-\myVirtualToplevel|Equal13~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal13~0_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_TICK\(5) & ( (!\myVirtualToplevel|RTC_MICROSEC_TICK\(2) & (\myVirtualToplevel|RTC_MICROSEC_TICK\(6) & \myVirtualToplevel|RTC_MICROSEC_TICK\(0))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011000000000000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(2),
- datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(6),
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(0),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(5),
- combout => \myVirtualToplevel|Equal13~0_combout\);
-
--- Location: LABCELL_X10_Y11_N33
-\myVirtualToplevel|Equal13~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal13~1_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_TICK\(1) & ( \myVirtualToplevel|RTC_MICROSEC_TICK\(3) ) ) # ( !\myVirtualToplevel|RTC_MICROSEC_TICK\(1) & ( \myVirtualToplevel|RTC_MICROSEC_TICK\(3) ) ) # (
--- \myVirtualToplevel|RTC_MICROSEC_TICK\(1) & ( !\myVirtualToplevel|RTC_MICROSEC_TICK\(3) & ( ((!\myVirtualToplevel|Equal13~0_combout\) # (\myVirtualToplevel|RTC_MICROSEC_TICK\(4))) # (\myVirtualToplevel|RTC_MICROSEC_TICK\(7)) ) ) ) # (
--- !\myVirtualToplevel|RTC_MICROSEC_TICK\(1) & ( !\myVirtualToplevel|RTC_MICROSEC_TICK\(3) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111110101111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(7),
- datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(4),
- datad => \myVirtualToplevel|ALT_INV_Equal13~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(1),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_TICK\(3),
- combout => \myVirtualToplevel|Equal13~1_combout\);
-
--- Location: LABCELL_X16_Y11_N48
-\myVirtualToplevel|RTC_MILLISEC_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000110000000000000011000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- combout => \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\);
-
--- Location: MLABCELL_X9_Y12_N27
-\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\ = ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (!\myVirtualToplevel|Equal13~1_combout\) # ((\myVirtualToplevel|UART1|Equal7~0_combout\ & \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\)) ) ) # (
--- !\myVirtualToplevel|TIMER0_CS~2_combout\ & ( !\myVirtualToplevel|Equal13~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011111100110011001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_Equal13~1_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\,
- combout => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\);
-
--- Location: FF_X9_Y12_N38
-\myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add4~29_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\,
- sload => \myVirtualToplevel|Equal13~1_combout\,
- ena => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\);
-
--- Location: MLABCELL_X9_Y12_N21
-\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1_combout\ = ( !\myVirtualToplevel|RTC_MICROSEC_COUNTER\(3) & ( (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(1) & (!\myVirtualToplevel|RTC_MICROSEC_COUNTER\(4) &
--- \myVirtualToplevel|RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010000000000000101000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(1),
- datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(4),
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(3),
- combout => \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~1_combout\);
-
--- Location: MLABCELL_X9_Y12_N45
-\myVirtualToplevel|Add4~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add4~5_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add4~2\ ))
--- \myVirtualToplevel|Add4~6\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add4~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(5),
- cin => \myVirtualToplevel|Add4~2\,
- sumout => \myVirtualToplevel|Add4~5_sumout\,
- cout => \myVirtualToplevel|Add4~6\);
-
--- Location: MLABCELL_X9_Y12_N48
-\myVirtualToplevel|Add4~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add4~13_sumout\ = SUM(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(6) ) + ( GND ) + ( \myVirtualToplevel|Add4~6\ ))
--- \myVirtualToplevel|Add4~14\ = CARRY(( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(6) ) + ( GND ) + ( \myVirtualToplevel|Add4~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(6),
- cin => \myVirtualToplevel|Add4~6\,
- sumout => \myVirtualToplevel|Add4~13_sumout\,
- cout => \myVirtualToplevel|Add4~14\);
-
--- Location: IOIBUF_X19_Y0_N35
-\SDRAM_DQ[6]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => SDRAM_DQ(6),
- o => \SDRAM_DQ[6]~input_o\);
-
--- Location: DDIOINCELL_X19_Y0_N48
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_NEW_REG46\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \SDRAM_DQ[6]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\);
-
--- Location: FF_X20_Y14_N25
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_NEW_REG44\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM45\);
-
--- Location: LABCELL_X20_Y14_N15
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM45\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) #
--- ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\)) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM45\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3\ & \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000101000000000000010111111010111111111111101011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM47\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM45\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]~21_combout\);
-
--- Location: M10K_X11_Y17_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 6,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 6,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\);
-
--- Location: FF_X13_Y12_N58
-\myVirtualToplevel|INT_ENABLE[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|INT_ENABLE\(6));
-
--- Location: FF_X20_Y14_N2
-\myVirtualToplevel|IO_DATA_READ_INTRCTL[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|INT_ENABLE\(6),
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- sload => VCC,
- ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(6));
-
--- Location: LABCELL_X16_Y14_N30
-\myVirtualToplevel|Equal4~0_RESYN12606\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal4~0_RESYN12606_BDD12607\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100000000001100110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|Equal4~0_RESYN12606_BDD12607\);
-
--- Location: LABCELL_X17_Y13_N24
-\myVirtualToplevel|Equal4~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal4~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ & ( \myVirtualToplevel|Equal4~0_RESYN12606_BDD12607\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000010000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_Equal4~0_RESYN12606_BDD12607\,
- combout => \myVirtualToplevel|Equal4~0_combout\);
-
--- Location: LABCELL_X16_Y8_N24
-\myVirtualToplevel|UART1_CS\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1_CS~combout\ = ( \myVirtualToplevel|IO_SELECT~combout\ & ( \myVirtualToplevel|Equal4~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- combout => \myVirtualToplevel|UART1_CS~combout\);
-
--- Location: LABCELL_X14_Y7_N6
-\myVirtualToplevel|UART1|RX_ENABLE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_ENABLE~0_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- combout => \myVirtualToplevel|UART1|RX_ENABLE~0_combout\);
-
--- Location: LABCELL_X14_Y9_N30
-\myVirtualToplevel|UART1|TX_ENABLE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_ENABLE~0_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000010000000100000001000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|TX_ENABLE~0_combout\);
-
--- Location: FF_X14_Y7_N8
-\myVirtualToplevel|UART1|RX_ENABLE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_ENABLE~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_ENABLE~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_ENABLE~q\);
-
--- Location: LABCELL_X16_Y8_N3
-\myVirtualToplevel|UART1|RX_RESET~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_RESET~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|UART1_CS~combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|UART1_CS~combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|UART1_CS~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111111111111111100011111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|RX_RESET~0_combout\);
-
--- Location: FF_X16_Y8_N5
-\myVirtualToplevel|UART1|RX_RESET\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_RESET~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_RESET~q\);
-
--- Location: LABCELL_X14_Y5_N3
-\myVirtualToplevel|UART1|RX_DATA[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ = ( !\myVirtualToplevel|UART1|RX_ENABLE~q\ & ( \myVirtualToplevel|UART1|RX_RESET~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_RESET~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- combout => \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\);
-
--- Location: FF_X16_Y6_N23
-\myVirtualToplevel|UART1|RXD_SYNC2\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \UART_RX_1~input_o\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RXD_SYNC2~q\);
-
--- Location: FF_X16_Y6_N38
-\myVirtualToplevel|UART1|RXD_SYNC\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RXD_SYNC2~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RXD_SYNC~q\);
-
--- Location: LABCELL_X14_Y6_N18
-\myVirtualToplevel|UART1|Selector4~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Selector4~0_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ & ( \myVirtualToplevel|UART1|RXD_SYNC~q\ ) ) # ( !\myVirtualToplevel|UART1|RX_STATE.bits~q\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- combout => \myVirtualToplevel|UART1|Selector4~0_combout\);
-
--- Location: FF_X16_Y6_N10
-\myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_STATE.start~0_combout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y6_N21
-\myVirtualToplevel|UART1|RX_BUFFER[1]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\ = ( \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & ( (\myVirtualToplevel|UART1|RX_CLOCK~q\ & (((!\myVirtualToplevel|UART1|RXD_SYNC~q\ & \myVirtualToplevel|UART1|RX_STATE.start~DUPLICATE_q\)) #
--- (\myVirtualToplevel|UART1|RX_STATE.bits~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000010111010000000001011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~DUPLICATE_q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\,
- combout => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\);
-
--- Location: FF_X14_Y6_N19
-\myVirtualToplevel|UART1|RX_BUFFER[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector4~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER\(8));
-
--- Location: LABCELL_X14_Y6_N9
-\myVirtualToplevel|UART1|Selector5~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Selector5~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(8) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(8),
- combout => \myVirtualToplevel|UART1|Selector5~0_combout\);
-
--- Location: FF_X14_Y6_N11
-\myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector5~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y6_N6
-\myVirtualToplevel|UART1|Selector6~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Selector6~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[7]~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART1|Selector6~0_combout\);
-
--- Location: FF_X14_Y6_N7
-\myVirtualToplevel|UART1|RX_BUFFER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector6~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER\(6));
-
--- Location: LABCELL_X14_Y6_N3
-\myVirtualToplevel|UART1|Selector7~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Selector7~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(6) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(6),
- combout => \myVirtualToplevel|UART1|Selector7~0_combout\);
-
--- Location: FF_X14_Y6_N5
-\myVirtualToplevel|UART1|RX_BUFFER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector7~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER\(5));
-
--- Location: LABCELL_X14_Y6_N0
-\myVirtualToplevel|UART1|Selector8~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Selector8~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(5) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(5),
- combout => \myVirtualToplevel|UART1|Selector8~0_combout\);
-
--- Location: FF_X14_Y6_N1
-\myVirtualToplevel|UART1|RX_BUFFER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector8~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER\(4));
-
--- Location: LABCELL_X14_Y6_N39
-\myVirtualToplevel|UART1|Selector9~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Selector9~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(4) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(4),
- combout => \myVirtualToplevel|UART1|Selector9~0_combout\);
-
--- Location: FF_X14_Y6_N40
-\myVirtualToplevel|UART1|RX_BUFFER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector9~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER\(3));
-
--- Location: LABCELL_X14_Y6_N36
-\myVirtualToplevel|UART1|Selector10~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Selector10~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(3) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(3),
- combout => \myVirtualToplevel|UART1|Selector10~0_combout\);
-
--- Location: FF_X14_Y6_N38
-\myVirtualToplevel|UART1|RX_BUFFER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector10~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER\(2));
-
--- Location: LABCELL_X14_Y6_N51
-\myVirtualToplevel|UART1|Selector11~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Selector11~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(2) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(2),
- combout => \myVirtualToplevel|UART1|Selector11~0_combout\);
-
--- Location: FF_X14_Y6_N53
-\myVirtualToplevel|UART1|RX_BUFFER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector11~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER\(1));
-
--- Location: LABCELL_X14_Y6_N48
-\myVirtualToplevel|UART1|Selector12~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Selector12~0_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(1) & ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(1),
- combout => \myVirtualToplevel|UART1|Selector12~0_combout\);
-
--- Location: FF_X14_Y6_N49
-\myVirtualToplevel|UART1|RX_BUFFER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector12~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER\(0));
-
--- Location: LABCELL_X16_Y6_N24
-\myVirtualToplevel|UART1|RX_STATE.bits~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_STATE.bits~0_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.bits~q\ & ( \myVirtualToplevel|UART1|RXD_SYNC~q\ & ( (!\myVirtualToplevel|UART1|RX_BUFFER\(0)) # (\myVirtualToplevel|UART1|RX_ENABLE~q\) ) ) ) # (
--- \myVirtualToplevel|UART1|RX_STATE.bits~q\ & ( !\myVirtualToplevel|UART1|RXD_SYNC~q\ & ( (!\myVirtualToplevel|UART1|RX_BUFFER\(0)) # ((\myVirtualToplevel|UART1|RX_STATE.start~q\) # (\myVirtualToplevel|UART1|RX_ENABLE~q\)) ) ) ) # (
--- !\myVirtualToplevel|UART1|RX_STATE.bits~q\ & ( !\myVirtualToplevel|UART1|RXD_SYNC~q\ & ( (\myVirtualToplevel|UART1|RX_STATE.stop~0_combout\ & \myVirtualToplevel|UART1|RX_STATE.start~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010101110011111111111100000000000000001100111111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~0_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(0),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~q\,
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\,
- combout => \myVirtualToplevel|UART1|RX_STATE.bits~0_combout\);
-
--- Location: FF_X16_Y6_N25
-\myVirtualToplevel|UART1|RX_STATE.bits\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_STATE.bits~0_combout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_STATE.bits~q\);
-
--- Location: LABCELL_X16_Y6_N57
-\myVirtualToplevel|UART1|RX_STATE.stop~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.stop~0_combout\ & ( (!\myVirtualToplevel|UART1|RX_STATE.bits~q\) # ((!\myVirtualToplevel|UART1|RX_ENABLE~q\ & \myVirtualToplevel|UART1|RX_BUFFER\(0))) ) ) # (
--- !\myVirtualToplevel|UART1|RX_STATE.stop~0_combout\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & (\myVirtualToplevel|UART1|RX_STATE.bits~q\ & \myVirtualToplevel|UART1|RX_BUFFER\(0))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001010000000000000101011110000111110101111000011111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(0),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~0_combout\,
- combout => \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\);
-
--- Location: LABCELL_X16_Y6_N9
-\myVirtualToplevel|UART1|RX_STATE.start~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_STATE.start~0_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ & ( !\myVirtualToplevel|UART1|RX_STATE.idle~q\ ) ) # ( !\myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ & (
--- \myVirtualToplevel|UART1|RX_STATE.start~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111111110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~2_combout\,
- combout => \myVirtualToplevel|UART1|RX_STATE.start~0_combout\);
-
--- Location: FF_X16_Y6_N11
-\myVirtualToplevel|UART1|RX_STATE.start\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_STATE.start~0_combout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_STATE.start~q\);
-
--- Location: LABCELL_X16_Y6_N6
-\myVirtualToplevel|UART1|RX_STATE.idle~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_STATE.idle~0_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_STATE.start~q\ & (!\myVirtualToplevel|UART1|RX_STATE.stop~q\)) # (\myVirtualToplevel|UART1|RX_STATE.start~q\ &
--- ((!\myVirtualToplevel|UART1|RXD_SYNC~q\))) ) ) # ( !\myVirtualToplevel|UART1|RX_STATE.stop~2_combout\ & ( \myVirtualToplevel|UART1|RX_STATE.idle~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111110111000101110001011100010111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.start~q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~2_combout\,
- combout => \myVirtualToplevel|UART1|RX_STATE.idle~0_combout\);
-
--- Location: FF_X16_Y6_N8
-\myVirtualToplevel|UART1|RX_STATE.idle\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_STATE.idle~0_combout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_STATE.idle~q\);
-
--- Location: LABCELL_X19_Y18_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder_combout\);
-
--- Location: FF_X19_Y18_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[14]~feeder_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(14));
-
--- Location: FF_X19_Y18_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(14));
-
--- Location: LABCELL_X19_Y18_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(14) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(14) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(14),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\);
-
--- Location: LABCELL_X6_Y21_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_NEW2721\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_OTERM2722\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000011000100011100111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_OTERM2722\);
-
--- Location: FF_X6_Y21_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[14]_OTERM2722\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14));
-
--- Location: LABCELL_X10_Y22_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_NEW2849\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_OTERM2850\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(14) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_OTERM2850\);
-
--- Location: FF_X10_Y22_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[14]_OTERM2850\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(14));
-
--- Location: LABCELL_X10_Y22_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_NEW2785\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_OTERM2786\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(14) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_OTERM2786\);
-
--- Location: FF_X10_Y22_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[14]_OTERM2786\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(14));
-
--- Location: LABCELL_X6_Y21_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_NEW2913\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_OTERM2914\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010000000100111101110011011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_OTERM2914\);
-
--- Location: FF_X6_Y21_N34
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[14]_OTERM2914\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14));
-
--- Location: LABCELL_X5_Y21_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(14)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(14))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(14)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(14)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(14)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101101011111010111100100010011101110010001001110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(14),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(14),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(14),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\);
-
--- Location: MLABCELL_X13_Y22_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_NEW2977\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_OTERM2978\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000101000100011010111110111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_OTERM2978\);
-
--- Location: FF_X13_Y22_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[14]_OTERM2978\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14));
-
--- Location: MLABCELL_X13_Y22_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_NEW3041\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_OTERM3042\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(14) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_OTERM3042\);
-
--- Location: FF_X13_Y22_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[14]_OTERM3042\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(14));
-
--- Location: MLABCELL_X13_Y22_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_NEW3105\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_OTERM3106\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001111001100110000111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_OTERM3106\);
-
--- Location: FF_X13_Y22_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[14]_OTERM3106\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14));
-
--- Location: MLABCELL_X13_Y22_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_NEW3169\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_OTERM3170\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_OTERM3170\);
-
--- Location: FF_X13_Y22_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[14]_OTERM3170\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14));
-
--- Location: MLABCELL_X13_Y22_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(14)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(14))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(14)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(14) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(14)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101101011111010111100010001101110110001000110111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(14),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(14),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(14),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\);
-
--- Location: LABCELL_X6_Y18_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux91~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010100000000010101010000000001010101111111110101010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\);
-
--- Location: MLABCELL_X9_Y14_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux91~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder_combout\);
-
--- Location: FF_X9_Y14_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~feeder_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\);
-
--- Location: LABCELL_X16_Y8_N12
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( \myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\);
-
--- Location: FF_X16_Y7_N50
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14));
-
--- Location: LABCELL_X14_Y7_N3
-\myVirtualToplevel|UART1|RX_COUNTER[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.idle~q\ & ( !\myVirtualToplevel|UART1|RX_ENABLE~q\ ) ) # ( !\myVirtualToplevel|UART1|RX_STATE.idle~q\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ &
--- !\myVirtualToplevel|UART1|RXD_SYNC~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- combout => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\);
-
--- Location: FF_X16_Y7_N4
-\myVirtualToplevel|UART1|RX_COUNTER[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~16_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(13));
-
--- Location: FF_X20_Y18_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12));
-
--- Location: LABCELL_X20_Y16_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder_combout\);
-
--- Location: FF_X20_Y16_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[12]~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(12));
-
--- Location: LABCELL_X20_Y18_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(12) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(12) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(12)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(12),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\);
-
--- Location: MLABCELL_X9_Y20_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_NEW3173\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_OTERM3174\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001111001100110000111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_OTERM3174\);
-
--- Location: FF_X9_Y20_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[12]_OTERM3174\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12));
-
--- Location: MLABCELL_X9_Y20_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_NEW3109\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_OTERM3110\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_OTERM3110\);
-
--- Location: FF_X9_Y20_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[12]_OTERM3110\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12));
-
--- Location: MLABCELL_X9_Y20_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_NEW2981\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_OTERM2982\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000100000001111111010011110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_OTERM2982\);
-
--- Location: FF_X9_Y20_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[12]_OTERM2982\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12));
-
--- Location: MLABCELL_X9_Y20_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_NEW3045\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_OTERM3046\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001111001100110000111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_OTERM3046\);
-
--- Location: FF_X9_Y20_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[12]_OTERM3046\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12));
-
--- Location: MLABCELL_X9_Y20_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(12) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(12) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(12) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(12) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101000000001111111100110011001100110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(12),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(12),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(12),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(12),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\);
-
--- Location: MLABCELL_X9_Y20_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_NEW2725\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_OTERM2726\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000101000100011010111110111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_OTERM2726\);
-
--- Location: FF_X9_Y20_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[12]_OTERM2726\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12));
-
--- Location: MLABCELL_X9_Y20_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_NEW2789\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_OTERM2790\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(12) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_OTERM2790\);
-
--- Location: FF_X9_Y20_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[12]_OTERM2790\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(12));
-
--- Location: MLABCELL_X9_Y20_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_NEW2917\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_OTERM2918\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000010001111111111101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_OTERM2918\);
-
--- Location: FF_X9_Y20_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[12]_OTERM2918\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12));
-
--- Location: LABCELL_X10_Y22_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_NEW2853\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_OTERM2854\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(12))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\)))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(12))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110101011000000011010101101000101111011110100010111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(12),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_OTERM2854\);
-
--- Location: FF_X10_Y22_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[12]_OTERM2854\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(12));
-
--- Location: MLABCELL_X9_Y20_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(12) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(12) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(12) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(12) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111010101010101010100000000111111110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(12),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(12),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(12),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(12),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\);
-
--- Location: MLABCELL_X9_Y20_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux93~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux93~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2_combout\);
-
--- Location: FF_X9_Y14_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~11_combout\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[0]~8_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12));
-
--- Location: FF_X14_Y7_N35
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(12));
-
--- Location: FF_X16_Y7_N8
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(11));
-
--- Location: LABCELL_X14_Y7_N39
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0_combout\);
-
--- Location: FF_X14_Y7_N41
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(10));
-
--- Location: LABCELL_X14_Y7_N36
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4_combout\);
-
--- Location: FF_X14_Y7_N37
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(5));
-
--- Location: LABCELL_X14_Y7_N21
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1_combout\);
-
--- Location: FF_X14_Y7_N22
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(2));
-
--- Location: FF_X16_Y8_N58
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(1));
-
--- Location: LABCELL_X14_Y7_N48
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5_combout\);
-
--- Location: FF_X14_Y7_N50
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[0]~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(0));
-
--- Location: LABCELL_X16_Y7_N0
-\myVirtualToplevel|UART1|RX_COUNTER~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~15_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & ((!\myVirtualToplevel|UART1|RX_COUNTER\(0)))) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & (!\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(0)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111110000110000111111000011000011111100001100001111110000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(0),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(0),
- combout => \myVirtualToplevel|UART1|RX_COUNTER~15_combout\);
-
--- Location: FF_X16_Y7_N1
-\myVirtualToplevel|UART1|RX_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~15_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(1),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(0));
-
--- Location: LABCELL_X17_Y7_N0
-\myVirtualToplevel|UART1|Add1~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~54\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(0),
- cin => GND,
- cout => \myVirtualToplevel|UART1|Add1~54\);
-
--- Location: LABCELL_X17_Y7_N3
-\myVirtualToplevel|UART1|Add1~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~17_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~54\ ))
--- \myVirtualToplevel|UART1|Add1~18\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(1),
- cin => \myVirtualToplevel|UART1|Add1~54\,
- sumout => \myVirtualToplevel|UART1|Add1~17_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~18\);
-
--- Location: LABCELL_X16_Y7_N18
-\myVirtualToplevel|UART1|RX_COUNTER~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~6_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|Add1~17_sumout\))) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(1)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001111001111000000111100111100000011110011110000001111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(1),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add1~17_sumout\,
- combout => \myVirtualToplevel|UART1|RX_COUNTER~6_combout\);
-
--- Location: LABCELL_X14_Y7_N18
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(2) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(2),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell_combout\);
-
--- Location: FF_X16_Y7_N19
-\myVirtualToplevel|UART1|RX_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~6_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[2]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(1));
-
--- Location: LABCELL_X17_Y7_N6
-\myVirtualToplevel|UART1|Add1~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~21_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~18\ ))
--- \myVirtualToplevel|UART1|Add1~22\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(2),
- cin => \myVirtualToplevel|UART1|Add1~18\,
- sumout => \myVirtualToplevel|UART1|Add1~21_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~22\);
-
--- Location: LABCELL_X17_Y7_N51
-\myVirtualToplevel|UART1|RX_COUNTER~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~7_combout\ = ( \myVirtualToplevel|UART1|Equal1~4_combout\ & ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(2) ) ) # ( !\myVirtualToplevel|UART1|Equal1~4_combout\ & ( \myVirtualToplevel|UART1|Add1~21_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111110101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(2),
- datac => \myVirtualToplevel|UART1|ALT_INV_Add1~21_sumout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- combout => \myVirtualToplevel|UART1|RX_COUNTER~7_combout\);
-
--- Location: LABCELL_X14_Y7_N51
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2_combout\);
-
--- Location: FF_X14_Y7_N52
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~2_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(3));
-
--- Location: LABCELL_X16_Y7_N42
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell_combout\ = !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(3)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(3),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell_combout\);
-
--- Location: FF_X17_Y7_N53
-\myVirtualToplevel|UART1|RX_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~7_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[3]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(2));
-
--- Location: LABCELL_X17_Y7_N9
-\myVirtualToplevel|UART1|Add1~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~25_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~22\ ))
--- \myVirtualToplevel|UART1|Add1~26\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(3),
- cin => \myVirtualToplevel|UART1|Add1~22\,
- sumout => \myVirtualToplevel|UART1|Add1~25_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~26\);
-
--- Location: LABCELL_X16_Y7_N33
-\myVirtualToplevel|UART1|RX_COUNTER~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~8_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|Add1~25_sumout\)) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & ((!\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(3))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111010001110100011101000111010001110100011101000111010001110100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_Add1~25_sumout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(3),
- combout => \myVirtualToplevel|UART1|RX_COUNTER~8_combout\);
-
--- Location: LABCELL_X14_Y7_N30
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3_combout\);
-
--- Location: FF_X16_Y7_N46
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(4));
-
--- Location: LABCELL_X16_Y7_N45
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell_combout\ = !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(4)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(4),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell_combout\);
-
--- Location: FF_X16_Y7_N34
-\myVirtualToplevel|UART1|RX_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~8_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[4]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(3));
-
--- Location: LABCELL_X17_Y7_N12
-\myVirtualToplevel|UART1|Add1~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~29_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~26\ ))
--- \myVirtualToplevel|UART1|Add1~30\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(4),
- cin => \myVirtualToplevel|UART1|Add1~26\,
- sumout => \myVirtualToplevel|UART1|Add1~29_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~30\);
-
--- Location: LABCELL_X16_Y7_N30
-\myVirtualToplevel|UART1|RX_COUNTER~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~9_combout\ = ( \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(4) & ( (!\myVirtualToplevel|UART1|Equal1~4_combout\ & \myVirtualToplevel|UART1|Add1~29_sumout\) ) ) # ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(4) & (
--- (\myVirtualToplevel|UART1|Add1~29_sumout\) # (\myVirtualToplevel|UART1|Equal1~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011111100111111001111110011111100001100000011000000110000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Add1~29_sumout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(4),
- combout => \myVirtualToplevel|UART1|RX_COUNTER~9_combout\);
-
--- Location: LABCELL_X16_Y7_N51
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(5) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(5),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell_combout\);
-
--- Location: FF_X16_Y7_N31
-\myVirtualToplevel|UART1|RX_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~9_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[5]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(4));
-
--- Location: LABCELL_X17_Y7_N15
-\myVirtualToplevel|UART1|Add1~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~33_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~30\ ))
--- \myVirtualToplevel|UART1|Add1~34\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(5),
- cin => \myVirtualToplevel|UART1|Add1~30\,
- sumout => \myVirtualToplevel|UART1|Add1~33_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~34\);
-
--- Location: LABCELL_X16_Y7_N15
-\myVirtualToplevel|UART1|RX_COUNTER~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~10_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|Add1~33_sumout\))) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & (!\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(5)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010111000101110001011100010111000101110001011100010111000101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(5),
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Add1~33_sumout\,
- combout => \myVirtualToplevel|UART1|RX_COUNTER~10_combout\);
-
--- Location: FF_X14_Y7_N55
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(6));
-
--- Location: FF_X16_Y7_N16
-\myVirtualToplevel|UART1|RX_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~10_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(6),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(5));
-
--- Location: LABCELL_X17_Y7_N18
-\myVirtualToplevel|UART1|Add1~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~37_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~34\ ))
--- \myVirtualToplevel|UART1|Add1~38\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(6),
- cin => \myVirtualToplevel|UART1|Add1~34\,
- sumout => \myVirtualToplevel|UART1|Add1~37_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~38\);
-
--- Location: LABCELL_X16_Y7_N36
-\myVirtualToplevel|UART1|RX_COUNTER~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~11_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|Add1~37_sumout\)) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(6))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000111111000011000011111100001100001111110000110000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Add1~37_sumout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(6),
- combout => \myVirtualToplevel|UART1|RX_COUNTER~11_combout\);
-
--- Location: FF_X16_Y7_N11
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(7));
-
--- Location: FF_X16_Y7_N37
-\myVirtualToplevel|UART1|RX_COUNTER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~11_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(7),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(6));
-
--- Location: LABCELL_X17_Y7_N21
-\myVirtualToplevel|UART1|Add1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~1_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~38\ ))
--- \myVirtualToplevel|UART1|Add1~2\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\,
- cin => \myVirtualToplevel|UART1|Add1~38\,
- sumout => \myVirtualToplevel|UART1|Add1~1_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~2\);
-
--- Location: LABCELL_X16_Y7_N24
-\myVirtualToplevel|UART1|RX_COUNTER~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~2_combout\ = ( \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(7) & ( (\myVirtualToplevel|UART1|Add1~1_sumout\) # (\myVirtualToplevel|UART1|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(7) & (
--- (!\myVirtualToplevel|UART1|Equal1~4_combout\ & \myVirtualToplevel|UART1|Add1~1_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Add1~1_sumout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(7),
- combout => \myVirtualToplevel|UART1|RX_COUNTER~2_combout\);
-
--- Location: LABCELL_X14_Y7_N57
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder_combout\);
-
--- Location: FF_X14_Y7_N58
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[8]~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8));
-
--- Location: FF_X16_Y7_N25
-\myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~2_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER[7]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y7_N24
-\myVirtualToplevel|UART1|Add1~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~5_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~2\ ))
--- \myVirtualToplevel|UART1|Add1~6\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(8),
- cin => \myVirtualToplevel|UART1|Add1~2\,
- sumout => \myVirtualToplevel|UART1|Add1~5_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~6\);
-
--- Location: LABCELL_X16_Y7_N27
-\myVirtualToplevel|UART1|RX_COUNTER~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~3_combout\ = ( \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8) & ( (\myVirtualToplevel|UART1|Add1~5_sumout\) # (\myVirtualToplevel|UART1|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8) & (
--- (!\myVirtualToplevel|UART1|Equal1~4_combout\ & \myVirtualToplevel|UART1|Add1~5_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Add1~5_sumout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(8),
- combout => \myVirtualToplevel|UART1|RX_COUNTER~3_combout\);
-
--- Location: FF_X16_Y8_N16
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(9));
-
--- Location: FF_X16_Y7_N28
-\myVirtualToplevel|UART1|RX_COUNTER[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~3_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(9),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(8));
-
--- Location: LABCELL_X17_Y7_N27
-\myVirtualToplevel|UART1|Add1~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~9_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~6\ ))
--- \myVirtualToplevel|UART1|Add1~10\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(9),
- cin => \myVirtualToplevel|UART1|Add1~6\,
- sumout => \myVirtualToplevel|UART1|Add1~9_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~10\);
-
--- Location: LABCELL_X16_Y7_N21
-\myVirtualToplevel|UART1|RX_COUNTER~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~4_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|Add1~9_sumout\)) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(9))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100011101000111010001110100011101000111010001110100011101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_Add1~9_sumout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(9),
- combout => \myVirtualToplevel|UART1|RX_COUNTER~4_combout\);
-
--- Location: LABCELL_X16_Y7_N6
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(10) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(10),
- combout => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell_combout\);
-
--- Location: FF_X16_Y7_N22
-\myVirtualToplevel|UART1|RX_COUNTER[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~4_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[10]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(9));
-
--- Location: LABCELL_X17_Y7_N30
-\myVirtualToplevel|UART1|Add1~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~13_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~10\ ))
--- \myVirtualToplevel|UART1|Add1~14\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\,
- cin => \myVirtualToplevel|UART1|Add1~10\,
- sumout => \myVirtualToplevel|UART1|Add1~13_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~14\);
-
--- Location: LABCELL_X16_Y7_N12
-\myVirtualToplevel|UART1|RX_COUNTER~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~5_combout\ = ( \myVirtualToplevel|UART1|Add1~13_sumout\ & ( (!\myVirtualToplevel|UART1|Equal1~4_combout\) # (!\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(10)) ) ) # ( !\myVirtualToplevel|UART1|Add1~13_sumout\ & (
--- (\myVirtualToplevel|UART1|Equal1~4_combout\ & !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(10)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001100000011000011111100111111001111110011111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(10),
- dataf => \myVirtualToplevel|UART1|ALT_INV_Add1~13_sumout\,
- combout => \myVirtualToplevel|UART1|RX_COUNTER~5_combout\);
-
--- Location: FF_X16_Y7_N13
-\myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~5_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(11),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER[10]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y7_N33
-\myVirtualToplevel|UART1|Add1~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~41_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~14\ ))
--- \myVirtualToplevel|UART1|Add1~42\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(11),
- cin => \myVirtualToplevel|UART1|Add1~14\,
- sumout => \myVirtualToplevel|UART1|Add1~41_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~42\);
-
--- Location: LABCELL_X16_Y7_N39
-\myVirtualToplevel|UART1|RX_COUNTER~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~12_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|Add1~41_sumout\))) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(11)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001111001111000000111100111100000011110011110000001111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(11),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add1~41_sumout\,
- combout => \myVirtualToplevel|UART1|RX_COUNTER~12_combout\);
-
--- Location: FF_X16_Y7_N40
-\myVirtualToplevel|UART1|RX_COUNTER[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~12_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(12),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(11));
-
--- Location: LABCELL_X17_Y7_N36
-\myVirtualToplevel|UART1|Add1~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~45_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~42\ ))
--- \myVirtualToplevel|UART1|Add1~46\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(12),
- cin => \myVirtualToplevel|UART1|Add1~42\,
- sumout => \myVirtualToplevel|UART1|Add1~45_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~46\);
-
--- Location: LABCELL_X16_Y7_N54
-\myVirtualToplevel|UART1|RX_COUNTER~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~13_combout\ = (!\myVirtualToplevel|UART1|Equal1~4_combout\ & ((\myVirtualToplevel|UART1|Add1~45_sumout\))) # (\myVirtualToplevel|UART1|Equal1~4_combout\ & (\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(12)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001110100011101000111010001110100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(12),
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Add1~45_sumout\,
- combout => \myVirtualToplevel|UART1|RX_COUNTER~13_combout\);
-
--- Location: FF_X16_Y7_N53
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(13));
-
--- Location: FF_X16_Y7_N55
-\myVirtualToplevel|UART1|RX_COUNTER[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~13_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(13),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(12));
-
--- Location: LABCELL_X17_Y7_N39
-\myVirtualToplevel|UART1|Add1~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~57_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~46\ ))
--- \myVirtualToplevel|UART1|Add1~58\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(13),
- cin => \myVirtualToplevel|UART1|Add1~46\,
- sumout => \myVirtualToplevel|UART1|Add1~57_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~58\);
-
--- Location: LABCELL_X16_Y7_N3
-\myVirtualToplevel|UART1|RX_COUNTER~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~16_combout\ = ( \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(13) & ( (\myVirtualToplevel|UART1|Add1~57_sumout\) # (\myVirtualToplevel|UART1|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(13) & (
--- (!\myVirtualToplevel|UART1|Equal1~4_combout\ & \myVirtualToplevel|UART1|Add1~57_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Add1~57_sumout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(13),
- combout => \myVirtualToplevel|UART1|RX_COUNTER~16_combout\);
-
--- Location: FF_X16_Y7_N5
-\myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~16_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE_q\);
-
--- Location: FF_X14_Y7_N46
-\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15));
-
--- Location: FF_X16_Y7_N58
-\myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~17_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y7_N42
-\myVirtualToplevel|UART1|Add1~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~61_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~58\ ))
--- \myVirtualToplevel|UART1|Add1~62\ = CARRY(( \myVirtualToplevel|UART1|RX_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|UART1|Add1~58\,
- sumout => \myVirtualToplevel|UART1|Add1~61_sumout\,
- cout => \myVirtualToplevel|UART1|Add1~62\);
-
--- Location: LABCELL_X16_Y7_N57
-\myVirtualToplevel|UART1|RX_COUNTER~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~17_combout\ = ( \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14) & ( (\myVirtualToplevel|UART1|Add1~61_sumout\) # (\myVirtualToplevel|UART1|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(14) & (
--- (!\myVirtualToplevel|UART1|Equal1~4_combout\ & \myVirtualToplevel|UART1|Add1~61_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Add1~61_sumout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(14),
- combout => \myVirtualToplevel|UART1|RX_COUNTER~17_combout\);
-
--- Location: FF_X16_Y7_N59
-\myVirtualToplevel|UART1|RX_COUNTER[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~17_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(14));
-
--- Location: FF_X16_Y7_N2
-\myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~15_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(1),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y7_N45
-\myVirtualToplevel|UART1|Add1~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add1~49_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add1~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(15),
- cin => \myVirtualToplevel|UART1|Add1~62\,
- sumout => \myVirtualToplevel|UART1|Add1~49_sumout\);
-
--- Location: LABCELL_X12_Y7_N36
-\myVirtualToplevel|UART1|RX_COUNTER~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_COUNTER~14_combout\ = ( \myVirtualToplevel|UART1|RX_COUNTER\(15) & ( \myVirtualToplevel|UART1|Equal1~4_combout\ & ( (!\myVirtualToplevel|UART1|RX_STATE.idle~q\ & ((\myVirtualToplevel|UART1|RXD_SYNC~q\))) #
--- (\myVirtualToplevel|UART1|RX_STATE.idle~q\ & (\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_COUNTER\(15) & ( \myVirtualToplevel|UART1|Equal1~4_combout\ & ( (\myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(15) &
--- \myVirtualToplevel|UART1|RX_STATE.idle~q\) ) ) ) # ( \myVirtualToplevel|UART1|RX_COUNTER\(15) & ( !\myVirtualToplevel|UART1|Equal1~4_combout\ & ( (!\myVirtualToplevel|UART1|RX_STATE.idle~q\ & ((\myVirtualToplevel|UART1|RXD_SYNC~q\))) #
--- (\myVirtualToplevel|UART1|RX_STATE.idle~q\ & (\myVirtualToplevel|UART1|Add1~49_sumout\)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_COUNTER\(15) & ( !\myVirtualToplevel|UART1|Equal1~4_combout\ & ( (\myVirtualToplevel|UART1|Add1~49_sumout\ &
--- \myVirtualToplevel|UART1|RX_STATE.idle~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000111111001100000101000001010000010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK_DIVISOR\(15),
- datab => \myVirtualToplevel|UART1|ALT_INV_Add1~49_sumout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\,
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(15),
- dataf => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- combout => \myVirtualToplevel|UART1|RX_COUNTER~14_combout\);
-
--- Location: FF_X12_Y7_N37
-\myVirtualToplevel|UART1|RX_COUNTER[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~14_combout\,
- ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(15));
-
--- Location: LABCELL_X16_Y7_N48
-\myVirtualToplevel|UART1|Equal1~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal1~3_combout\ = ( !\myVirtualToplevel|UART1|RX_COUNTER\(15) & ( (!\myVirtualToplevel|UART1|RX_COUNTER[13]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_COUNTER\(14) & !\myVirtualToplevel|UART1|RX_COUNTER[0]~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000010000000100000001000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[13]~DUPLICATE_q\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(14),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(15),
- combout => \myVirtualToplevel|UART1|Equal1~3_combout\);
-
--- Location: LABCELL_X17_Y7_N48
-\myVirtualToplevel|UART1|Equal1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal1~1_combout\ = ( !\myVirtualToplevel|UART1|RX_COUNTER\(2) & ( (!\myVirtualToplevel|UART1|RX_COUNTER\(1) & (!\myVirtualToplevel|UART1|RX_COUNTER\(4) & !\myVirtualToplevel|UART1|RX_COUNTER\(3))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(1),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(4),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(3),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(2),
- combout => \myVirtualToplevel|UART1|Equal1~1_combout\);
-
--- Location: LABCELL_X17_Y7_N57
-\myVirtualToplevel|UART1|Equal1~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal1~2_combout\ = ( !\myVirtualToplevel|UART1|RX_COUNTER\(12) & ( (!\myVirtualToplevel|UART1|RX_COUNTER\(11) & (!\myVirtualToplevel|UART1|RX_COUNTER\(5) & !\myVirtualToplevel|UART1|RX_COUNTER\(6))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(11),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(5),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(6),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(12),
- combout => \myVirtualToplevel|UART1|Equal1~2_combout\);
-
--- Location: FF_X16_Y7_N26
-\myVirtualToplevel|UART1|RX_COUNTER[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~2_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(8),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(7));
-
--- Location: FF_X16_Y7_N14
-\myVirtualToplevel|UART1|RX_COUNTER[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_COUNTER~5_combout\,
- asdata => \myVirtualToplevel|UART1|RX_CLOCK_DIVISOR\(11),
- sload => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_COUNTER\(10));
-
--- Location: LABCELL_X16_Y7_N9
-\myVirtualToplevel|UART1|Equal1~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal1~0_combout\ = ( !\myVirtualToplevel|UART1|RX_COUNTER\(9) & ( (!\myVirtualToplevel|UART1|RX_COUNTER\(7) & (!\myVirtualToplevel|UART1|RX_COUNTER\(8) & !\myVirtualToplevel|UART1|RX_COUNTER\(10))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000010000000100000001000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(7),
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(8),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(10),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER\(9),
- combout => \myVirtualToplevel|UART1|Equal1~0_combout\);
-
--- Location: LABCELL_X17_Y7_N54
-\myVirtualToplevel|UART1|Equal1~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal1~4_combout\ = ( \myVirtualToplevel|UART1|Equal1~0_combout\ & ( (\myVirtualToplevel|UART1|Equal1~3_combout\ & (\myVirtualToplevel|UART1|Equal1~1_combout\ & \myVirtualToplevel|UART1|Equal1~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal1~3_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Equal1~1_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Equal1~2_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Equal1~0_combout\,
- combout => \myVirtualToplevel|UART1|Equal1~4_combout\);
-
--- Location: LABCELL_X12_Y7_N18
-\myVirtualToplevel|UART1|RX_CLOCK~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_CLOCK~0_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.idle~q\ & ( \myVirtualToplevel|UART1|Equal1~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Equal1~4_combout\,
- combout => \myVirtualToplevel|UART1|RX_CLOCK~0_combout\);
-
--- Location: FF_X12_Y7_N19
-\myVirtualToplevel|UART1|RX_CLOCK\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_CLOCK~0_combout\,
- ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_CLOCK~q\);
-
--- Location: LABCELL_X14_Y7_N42
-\myVirtualToplevel|UART1|RX_STATE.stop~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_STATE.stop~0_combout\ = ( \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\ & ( \myVirtualToplevel|UART1|RX_STATE.idle~q\ & ( \myVirtualToplevel|UART1|RX_CLOCK~q\ ) ) ) # ( \myVirtualToplevel|UART1|RX_COUNTER[0]~1_combout\ & (
--- !\myVirtualToplevel|UART1|RX_STATE.idle~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\,
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_COUNTER[0]~1_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.idle~q\,
- combout => \myVirtualToplevel|UART1|RX_STATE.stop~0_combout\);
-
--- Location: LABCELL_X16_Y6_N39
-\myVirtualToplevel|UART1|RX_STATE.stop~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_STATE.stop~1_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.stop~q\ & ( (!\myVirtualToplevel|UART1|RX_STATE.stop~0_combout\) # (\myVirtualToplevel|UART1|RX_STATE.bits~q\) ) ) # ( !\myVirtualToplevel|UART1|RX_STATE.stop~q\ & (
--- (\myVirtualToplevel|UART1|RX_STATE.bits~q\ & (\myVirtualToplevel|UART1|RX_BUFFER\(0) & !\myVirtualToplevel|UART1|RX_ENABLE~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000000000000110000000010111011101110111011101110111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~0_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.bits~q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(0),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\,
- combout => \myVirtualToplevel|UART1|RX_STATE.stop~1_combout\);
-
--- Location: FF_X12_Y6_N37
-\myVirtualToplevel|UART1|RX_STATE.stop\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_STATE.stop~1_combout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_STATE.stop~q\);
-
--- Location: LABCELL_X16_Y6_N33
-\myVirtualToplevel|UART1|RX_INTR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_INTR~0_combout\ = ( \myVirtualToplevel|UART1|RXD_SYNC~q\ & ( (\myVirtualToplevel|UART1|RX_STATE.stop~q\ & \myVirtualToplevel|UART1|RX_CLOCK~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000101000001010000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\,
- combout => \myVirtualToplevel|UART1|RX_INTR~0_combout\);
-
--- Location: LABCELL_X14_Y7_N9
-\myVirtualToplevel|UART1|RX_ENABLE_FIFO~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_ENABLE_FIFO~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1),
- combout => \myVirtualToplevel|UART1|RX_ENABLE_FIFO~0_combout\);
-
--- Location: FF_X14_Y7_N10
-\myVirtualToplevel|UART1|RX_ENABLE_FIFO\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_ENABLE_FIFO~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_ENABLE~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\);
-
--- Location: MLABCELL_X13_Y5_N57
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1_combout\ = !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0),
- combout => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1_combout\);
-
--- Location: MLABCELL_X13_Y7_N30
-\myVirtualToplevel|UART1|Add3~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add3~5_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|UART1|Add3~6\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(0),
- cin => GND,
- sumout => \myVirtualToplevel|UART1|Add3~5_sumout\,
- cout => \myVirtualToplevel|UART1|Add3~6\);
-
--- Location: MLABCELL_X13_Y9_N6
-\myVirtualToplevel|UART1|RX_DATA_READY~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA_READY~0_combout\ = ( \myVirtualToplevel|UART1|Equal7~0_combout\ & ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\,
- datae => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|RX_DATA_READY~0_combout\);
-
--- Location: LABCELL_X16_Y6_N42
-\myVirtualToplevel|UART1|RX_DATA_READY~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA_READY~1_combout\ = ( \myVirtualToplevel|UART1|RX_DATA_READY~0_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA_READY~q\ & ((!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & ((!\myVirtualToplevel|UART1|Equal2~4_combout\))) #
--- (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & (\myVirtualToplevel|UART1|RX_INTR~0_combout\)))) ) ) # ( !\myVirtualToplevel|UART1|RX_DATA_READY~0_combout\ & ( ((!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & ((!\myVirtualToplevel|UART1|Equal2~4_combout\)))
--- # (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & (\myVirtualToplevel|UART1|RX_INTR~0_combout\))) # (\myVirtualToplevel|UART1|RX_DATA_READY~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1101000111111111110100011111111111010001000000001101000100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Equal2~4_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~0_combout\,
- combout => \myVirtualToplevel|UART1|RX_DATA_READY~1_combout\);
-
--- Location: FF_X16_Y6_N44
-\myVirtualToplevel|UART1|RX_DATA_READY\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_DATA_READY~1_combout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_DATA_READY~q\);
-
--- Location: LABCELL_X16_Y6_N30
-\myVirtualToplevel|UART1|process_3~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|process_3~0_combout\ = ( !\myVirtualToplevel|UART1|RX_DATA_READY~q\ & ( !\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~q\,
- combout => \myVirtualToplevel|UART1|process_3~0_combout\);
-
--- Location: MLABCELL_X13_Y5_N36
-\myVirtualToplevel|UART1|Add4~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add4~9_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~14\ ))
--- \myVirtualToplevel|UART1|Add4~10\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3),
- cin => \myVirtualToplevel|UART1|Add4~14\,
- sumout => \myVirtualToplevel|UART1|Add4~9_sumout\,
- cout => \myVirtualToplevel|UART1|Add4~10\);
-
--- Location: MLABCELL_X13_Y5_N39
-\myVirtualToplevel|UART1|Add4~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add4~1_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~10\ ))
--- \myVirtualToplevel|UART1|Add4~2\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4),
- cin => \myVirtualToplevel|UART1|Add4~10\,
- sumout => \myVirtualToplevel|UART1|Add4~1_sumout\,
- cout => \myVirtualToplevel|UART1|Add4~2\);
-
--- Location: FF_X13_Y5_N41
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add4~1_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4));
-
--- Location: MLABCELL_X13_Y5_N42
-\myVirtualToplevel|UART1|Add4~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add4~21_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~2\ ))
--- \myVirtualToplevel|UART1|Add4~22\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(5),
- cin => \myVirtualToplevel|UART1|Add4~2\,
- sumout => \myVirtualToplevel|UART1|Add4~21_sumout\,
- cout => \myVirtualToplevel|UART1|Add4~22\);
-
--- Location: FF_X13_Y5_N43
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add4~21_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5));
-
--- Location: MLABCELL_X13_Y5_N45
-\myVirtualToplevel|UART1|Add4~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add4~17_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~22\ ))
--- \myVirtualToplevel|UART1|Add4~18\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6),
- cin => \myVirtualToplevel|UART1|Add4~22\,
- sumout => \myVirtualToplevel|UART1|Add4~17_sumout\,
- cout => \myVirtualToplevel|UART1|Add4~18\);
-
--- Location: FF_X13_Y5_N46
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add4~17_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6));
-
--- Location: MLABCELL_X13_Y7_N45
-\myVirtualToplevel|UART1|Add3~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add3~25_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~2\ ))
--- \myVirtualToplevel|UART1|Add3~26\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5),
- cin => \myVirtualToplevel|UART1|Add3~2\,
- sumout => \myVirtualToplevel|UART1|Add3~25_sumout\,
- cout => \myVirtualToplevel|UART1|Add3~26\);
-
--- Location: MLABCELL_X13_Y7_N48
-\myVirtualToplevel|UART1|Add3~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add3~21_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~26\ ))
--- \myVirtualToplevel|UART1|Add3~22\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6),
- cin => \myVirtualToplevel|UART1|Add3~26\,
- sumout => \myVirtualToplevel|UART1|Add3~21_sumout\,
- cout => \myVirtualToplevel|UART1|Add3~22\);
-
--- Location: FF_X13_Y7_N50
-\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add3~21_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6));
-
--- Location: LABCELL_X16_Y5_N12
-\myVirtualToplevel|UART1|Equal2~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal2~2_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) & ( (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6)) ) ) ) # (
--- !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) & ( (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) & \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6)) ) ) ) # ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & (
--- !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) & ( (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) & !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) & (
--- (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) & !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000010100000010100000101000000001010000010100000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6),
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6),
- combout => \myVirtualToplevel|UART1|Equal2~2_combout\);
-
--- Location: MLABCELL_X13_Y5_N30
-\myVirtualToplevel|UART1|Add4~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add4~5_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) ) + ( !VCC ))
--- \myVirtualToplevel|UART1|Add4~6\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110011001100110000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1),
- cin => GND,
- sumout => \myVirtualToplevel|UART1|Add4~5_sumout\,
- cout => \myVirtualToplevel|UART1|Add4~6\);
-
--- Location: FF_X13_Y5_N31
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add4~5_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1));
-
--- Location: FF_X13_Y7_N28
-\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~5_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y5_N54
-\myVirtualToplevel|UART1|Equal2~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal2~0_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1)))) )
--- ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100001100000000110000110000000000000000110000110000000011000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0),
- combout => \myVirtualToplevel|UART1|Equal2~0_combout\);
-
--- Location: MLABCELL_X13_Y7_N51
-\myVirtualToplevel|UART1|Add3~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add3~29_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7),
- cin => \myVirtualToplevel|UART1|Add3~22\,
- sumout => \myVirtualToplevel|UART1|Add3~29_sumout\);
-
--- Location: FF_X13_Y7_N53
-\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add3~29_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7));
-
--- Location: MLABCELL_X13_Y5_N48
-\myVirtualToplevel|UART1|Add4~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add4~25_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7),
- cin => \myVirtualToplevel|UART1|Add4~18\,
- sumout => \myVirtualToplevel|UART1|Add4~25_sumout\);
-
--- Location: FF_X14_Y5_N19
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add4~25_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7));
-
--- Location: LABCELL_X16_Y5_N54
-\myVirtualToplevel|UART1|Equal2~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal2~3_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & ( (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) & \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7)) ) ) ) # (
--- !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) & \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7)) ) ) ) # ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) & (
--- !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & ( (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) & !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) & ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & (
--- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) & !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000010100000010100000101000000001010000010100000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(5),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7),
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7),
- combout => \myVirtualToplevel|UART1|Equal2~3_combout\);
-
--- Location: LABCELL_X16_Y6_N18
-\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\ = ( \myVirtualToplevel|UART1|Equal2~0_combout\ & ( \myVirtualToplevel|UART1|Equal2~3_combout\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & (\myVirtualToplevel|UART1|process_3~0_combout\ &
--- ((!\myVirtualToplevel|UART1|Equal2~2_combout\) # (!\myVirtualToplevel|UART1|Equal2~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|UART1|Equal2~0_combout\ & ( \myVirtualToplevel|UART1|Equal2~3_combout\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ &
--- \myVirtualToplevel|UART1|process_3~0_combout\) ) ) ) # ( \myVirtualToplevel|UART1|Equal2~0_combout\ & ( !\myVirtualToplevel|UART1|Equal2~3_combout\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & \myVirtualToplevel|UART1|process_3~0_combout\) ) ) ) # (
--- !\myVirtualToplevel|UART1|Equal2~0_combout\ & ( !\myVirtualToplevel|UART1|Equal2~3_combout\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & \myVirtualToplevel|UART1|process_3~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000100010001000100010001000100010001000100010001000100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- datab => \myVirtualToplevel|UART1|ALT_INV_process_3~0_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Equal2~2_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Equal2~1_combout\,
- datae => \myVirtualToplevel|UART1|ALT_INV_Equal2~0_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Equal2~3_combout\,
- combout => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\);
-
--- Location: FF_X13_Y7_N29
-\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~5_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(0));
-
--- Location: MLABCELL_X13_Y7_N33
-\myVirtualToplevel|UART1|Add3~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add3~9_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~6\ ))
--- \myVirtualToplevel|UART1|Add3~10\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1),
- cin => \myVirtualToplevel|UART1|Add3~6\,
- sumout => \myVirtualToplevel|UART1|Add3~9_sumout\,
- cout => \myVirtualToplevel|UART1|Add3~10\);
-
--- Location: FF_X13_Y7_N59
-\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~9_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1));
-
--- Location: MLABCELL_X13_Y7_N36
-\myVirtualToplevel|UART1|Add3~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add3~17_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~10\ ))
--- \myVirtualToplevel|UART1|Add3~18\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2),
- cin => \myVirtualToplevel|UART1|Add3~10\,
- sumout => \myVirtualToplevel|UART1|Add3~17_sumout\,
- cout => \myVirtualToplevel|UART1|Add3~18\);
-
--- Location: FF_X13_Y7_N38
-\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add3~17_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2));
-
--- Location: MLABCELL_X13_Y7_N39
-\myVirtualToplevel|UART1|Add3~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add3~13_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~18\ ))
--- \myVirtualToplevel|UART1|Add3~14\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3),
- cin => \myVirtualToplevel|UART1|Add3~18\,
- sumout => \myVirtualToplevel|UART1|Add3~13_sumout\,
- cout => \myVirtualToplevel|UART1|Add3~14\);
-
--- Location: FF_X13_Y7_N41
-\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add3~13_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3));
-
--- Location: MLABCELL_X13_Y7_N42
-\myVirtualToplevel|UART1|Add3~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add3~1_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~14\ ))
--- \myVirtualToplevel|UART1|Add3~2\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add3~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4),
- cin => \myVirtualToplevel|UART1|Add3~14\,
- sumout => \myVirtualToplevel|UART1|Add3~1_sumout\,
- cout => \myVirtualToplevel|UART1|Add3~2\);
-
--- Location: FF_X13_Y7_N44
-\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add3~1_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4));
-
--- Location: FF_X13_Y7_N47
-\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add3~25_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5));
-
--- Location: LABCELL_X14_Y5_N30
-\myVirtualToplevel|UART1|Add2~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add2~22\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\,
- cin => GND,
- cout => \myVirtualToplevel|UART1|Add2~22\);
-
--- Location: LABCELL_X14_Y5_N33
-\myVirtualToplevel|UART1|Add2~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add2~25_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~22\ ))
--- \myVirtualToplevel|UART1|Add2~26\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1),
- cin => \myVirtualToplevel|UART1|Add2~22\,
- sumout => \myVirtualToplevel|UART1|Add2~25_sumout\,
- cout => \myVirtualToplevel|UART1|Add2~26\);
-
--- Location: LABCELL_X14_Y5_N36
-\myVirtualToplevel|UART1|Add2~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add2~29_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~26\ ))
--- \myVirtualToplevel|UART1|Add2~30\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2),
- cin => \myVirtualToplevel|UART1|Add2~26\,
- sumout => \myVirtualToplevel|UART1|Add2~29_sumout\,
- cout => \myVirtualToplevel|UART1|Add2~30\);
-
--- Location: LABCELL_X14_Y5_N39
-\myVirtualToplevel|UART1|Add2~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add2~9_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~30\ ))
--- \myVirtualToplevel|UART1|Add2~10\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3),
- cin => \myVirtualToplevel|UART1|Add2~30\,
- sumout => \myVirtualToplevel|UART1|Add2~9_sumout\,
- cout => \myVirtualToplevel|UART1|Add2~10\);
-
--- Location: LABCELL_X14_Y5_N42
-\myVirtualToplevel|UART1|Add2~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add2~13_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~10\ ))
--- \myVirtualToplevel|UART1|Add2~14\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4),
- cin => \myVirtualToplevel|UART1|Add2~10\,
- sumout => \myVirtualToplevel|UART1|Add2~13_sumout\,
- cout => \myVirtualToplevel|UART1|Add2~14\);
-
--- Location: LABCELL_X14_Y5_N45
-\myVirtualToplevel|UART1|Add2~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add2~17_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~14\ ))
--- \myVirtualToplevel|UART1|Add2~18\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5),
- cin => \myVirtualToplevel|UART1|Add2~14\,
- sumout => \myVirtualToplevel|UART1|Add2~17_sumout\,
- cout => \myVirtualToplevel|UART1|Add2~18\);
-
--- Location: FF_X13_Y5_N44
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add4~21_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y5_N24
-\myVirtualToplevel|UART1|Equal3~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal3~0_combout\ = ( \myVirtualToplevel|UART1|Add2~13_sumout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) & ( (!\myVirtualToplevel|UART1|Add2~17_sumout\ & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|UART1|Add2~9_sumout\ $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3))))) # (\myVirtualToplevel|UART1|Add2~17_sumout\ & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|Add2~9_sumout\ $
--- (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3))))) ) ) ) # ( !\myVirtualToplevel|UART1|Add2~13_sumout\ & ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) & ( (!\myVirtualToplevel|UART1|Add2~17_sumout\ &
--- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|Add2~9_sumout\ $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3))))) # (\myVirtualToplevel|UART1|Add2~17_sumout\ &
--- (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|Add2~9_sumout\ $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1001000000001001000000000000000000000000000000001001000000001001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_Add2~17_sumout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[5]~DUPLICATE_q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Add2~9_sumout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3),
- datae => \myVirtualToplevel|UART1|ALT_INV_Add2~13_sumout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4),
- combout => \myVirtualToplevel|UART1|Equal3~0_combout\);
-
--- Location: LABCELL_X14_Y5_N48
-\myVirtualToplevel|UART1|Add2~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add2~1_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~18\ ))
--- \myVirtualToplevel|UART1|Add2~2\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6),
- cin => \myVirtualToplevel|UART1|Add2~18\,
- sumout => \myVirtualToplevel|UART1|Add2~1_sumout\,
- cout => \myVirtualToplevel|UART1|Add2~2\);
-
--- Location: LABCELL_X14_Y5_N51
-\myVirtualToplevel|UART1|Add2~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add2~5_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add2~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7),
- cin => \myVirtualToplevel|UART1|Add2~2\,
- sumout => \myVirtualToplevel|UART1|Add2~5_sumout\);
-
--- Location: LABCELL_X14_Y5_N21
-\myVirtualToplevel|UART1|Equal3~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal3~1_combout\ = ( \myVirtualToplevel|UART1|Add2~29_sumout\ & ( \myVirtualToplevel|UART1|Add2~25_sumout\ & ( (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) &
--- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|UART1|Add2~29_sumout\ & ( \myVirtualToplevel|UART1|Add2~25_sumout\ & (
--- (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # (
--- \myVirtualToplevel|UART1|Add2~29_sumout\ & ( !\myVirtualToplevel|UART1|Add2~25_sumout\ & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) $
--- (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|UART1|Add2~29_sumout\ & ( !\myVirtualToplevel|UART1|Add2~25_sumout\ & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) &
--- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000010000000000000100000100000010000010000000000000100000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1),
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\,
- datae => \myVirtualToplevel|UART1|ALT_INV_Add2~29_sumout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Add2~25_sumout\,
- combout => \myVirtualToplevel|UART1|Equal3~1_combout\);
-
--- Location: MLABCELL_X13_Y5_N18
-\myVirtualToplevel|UART1|Equal3~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal3~2_combout\ = ( \myVirtualToplevel|UART1|Equal3~1_combout\ & ( \myVirtualToplevel|UART1|Add2~1_sumout\ & ( (\myVirtualToplevel|UART1|Equal3~0_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) &
--- (!\myVirtualToplevel|UART1|Add2~5_sumout\ $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7))))) ) ) ) # ( \myVirtualToplevel|UART1|Equal3~1_combout\ & ( !\myVirtualToplevel|UART1|Add2~1_sumout\ & ( (\myVirtualToplevel|UART1|Equal3~0_combout\ &
--- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART1|Add2~5_sumout\ $ (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010000000000010000000000000000000001000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_Equal3~0_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6),
- datac => \myVirtualToplevel|UART1|ALT_INV_Add2~5_sumout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7),
- datae => \myVirtualToplevel|UART1|ALT_INV_Equal3~1_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Add2~1_sumout\,
- combout => \myVirtualToplevel|UART1|Equal3~2_combout\);
-
--- Location: LABCELL_X14_Y5_N27
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\ = ( \myVirtualToplevel|UART1|RX_INTR~0_combout\ & ( (!\myVirtualToplevel|UART1|Equal3~2_combout\ & (!\myVirtualToplevel|UART1|RX_ENABLE~q\ & !\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011000000000000001100000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal3~2_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\,
- combout => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\);
-
--- Location: FF_X13_Y5_N52
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~1_combout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0));
-
--- Location: MLABCELL_X13_Y5_N33
-\myVirtualToplevel|UART1|Add4~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add4~13_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~6\ ))
--- \myVirtualToplevel|UART1|Add4~14\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add4~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2),
- cin => \myVirtualToplevel|UART1|Add4~6\,
- sumout => \myVirtualToplevel|UART1|Add4~13_sumout\,
- cout => \myVirtualToplevel|UART1|Add4~14\);
-
--- Location: FF_X13_Y5_N34
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add4~13_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2));
-
--- Location: FF_X13_Y5_N37
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add4~9_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3));
-
--- Location: FF_X13_Y5_N40
-\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add4~1_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y5_N24
-\myVirtualToplevel|UART1|Equal2~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal2~1_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) & ( (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ $ (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4)))) )
--- ) # ( !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\ $ (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000001010101000000000101001010000000001010101000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3),
- combout => \myVirtualToplevel|UART1|Equal2~1_combout\);
-
--- Location: LABCELL_X16_Y6_N54
-\myVirtualToplevel|UART1|Equal2~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal2~4_combout\ = ( \myVirtualToplevel|UART1|Equal2~3_combout\ & ( (\myVirtualToplevel|UART1|Equal2~1_combout\ & (\myVirtualToplevel|UART1|Equal2~2_combout\ & \myVirtualToplevel|UART1|Equal2~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal2~1_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Equal2~2_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Equal2~0_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Equal2~3_combout\,
- combout => \myVirtualToplevel|UART1|Equal2~4_combout\);
-
--- Location: LABCELL_X16_Y6_N15
-\myVirtualToplevel|UART1|RX_DATA[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ = ( !\myVirtualToplevel|UART1|RX_DATA_READY~q\ & ( (!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ & ((!\myVirtualToplevel|UART1|Equal2~4_combout\))) # (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\ &
--- (\myVirtualToplevel|UART1|RX_INTR~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1101110100010001110111010001000100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Equal2~4_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~q\,
- combout => \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\);
-
--- Location: MLABCELL_X13_Y7_N54
-\myVirtualToplevel|UART1|RX_FIFO~31\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO~31_combout\ = ( \myVirtualToplevel|UART1|RX_STATE.stop~q\ & ( \myVirtualToplevel|UART1|RXD_SYNC~q\ & ( (\myVirtualToplevel|UART1|RX_CLOCK~q\ & (\myVirtualToplevel|UART1|RX_RESET~q\ & (!\myVirtualToplevel|UART1|RX_ENABLE~q\
--- & !\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000001000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_CLOCK~q\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_RESET~q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\,
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_STATE.stop~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RXD_SYNC~q\,
- combout => \myVirtualToplevel|UART1|RX_FIFO~31_combout\);
-
--- Location: MLABCELL_X13_Y5_N15
-\myVirtualToplevel|UART1|Equal3~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal3~3_combout\ = ( \myVirtualToplevel|UART1|Add2~1_sumout\ & ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) ) ) # ( !\myVirtualToplevel|UART1|Add2~1_sumout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111111110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6),
- dataf => \myVirtualToplevel|UART1|ALT_INV_Add2~1_sumout\,
- combout => \myVirtualToplevel|UART1|Equal3~3_combout\);
-
--- Location: MLABCELL_X13_Y5_N6
-\myVirtualToplevel|UART1|RX_FIFO~32\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO~32_combout\ = ( \myVirtualToplevel|UART1|Equal3~1_combout\ & ( \myVirtualToplevel|UART1|Add2~5_sumout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~31_combout\ & ((!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7)) #
--- ((!\myVirtualToplevel|UART1|Equal3~0_combout\) # (\myVirtualToplevel|UART1|Equal3~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|UART1|Equal3~1_combout\ & ( \myVirtualToplevel|UART1|Add2~5_sumout\ & ( \myVirtualToplevel|UART1|RX_FIFO~31_combout\ ) ) ) # (
--- \myVirtualToplevel|UART1|Equal3~1_combout\ & ( !\myVirtualToplevel|UART1|Add2~5_sumout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~31_combout\ & (((!\myVirtualToplevel|UART1|Equal3~0_combout\) # (\myVirtualToplevel|UART1|Equal3~3_combout\)) #
--- (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7)))) ) ) ) # ( !\myVirtualToplevel|UART1|Equal3~1_combout\ & ( !\myVirtualToplevel|UART1|Add2~5_sumout\ & ( \myVirtualToplevel|UART1|RX_FIFO~31_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010100010101010101010101010101010101010001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~31_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7),
- datac => \myVirtualToplevel|UART1|ALT_INV_Equal3~0_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Equal3~3_combout\,
- datae => \myVirtualToplevel|UART1|ALT_INV_Equal3~1_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Add2~5_sumout\,
- combout => \myVirtualToplevel|UART1|RX_FIFO~32_combout\);
-
--- Location: FF_X14_Y6_N2
-\myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector8~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER[4]~DUPLICATE_q\);
-
--- Location: FF_X14_Y6_N4
-\myVirtualToplevel|UART1|RX_BUFFER[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector7~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER[5]~DUPLICATE_q\);
-
--- Location: FF_X14_Y6_N10
-\myVirtualToplevel|UART1|RX_BUFFER[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Selector5~0_combout\,
- ena => \myVirtualToplevel|UART1|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_BUFFER\(7));
-
--- Location: M10K_X11_Y6_N0
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- logical_ram_name => "zpu_soc:myVirtualToplevel|uart:UART1|altsyncram:RX_FIFO_rtl_0|altsyncram_1jo1:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 8,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 40,
- port_a_first_address => 0,
- port_a_first_bit_number => 0,
- port_a_last_address => 255,
- port_a_logical_ram_depth => 256,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 8,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 40,
- port_b_first_address => 0,
- port_b_first_bit_number => 0,
- port_b_last_address => 255,
- port_b_logical_ram_depth => 256,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|UART1|RX_FIFO~32_combout\,
- portbre => VCC,
- portbaddrstall => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);
-
--- Location: LABCELL_X14_Y6_N27
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder_combout\ = \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[7]~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder_combout\);
-
--- Location: FF_X14_Y6_N28
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[23]~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(23));
-
--- Location: FF_X16_Y5_N46
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(15));
-
--- Location: FF_X16_Y5_N20
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(13));
-
--- Location: FF_X16_Y5_N17
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(11));
-
--- Location: FF_X16_Y5_N5
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~21_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(14));
-
--- Location: FF_X16_Y5_N53
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~25_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(12));
-
--- Location: LABCELL_X16_Y5_N3
-\myVirtualToplevel|UART1|RX_FIFO~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO~26_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(12) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(11) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(13) $
--- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(14)))) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(12) & ( (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(11) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(13) $
--- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(14)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000001010000101000000101000000001010000001010000101000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(13),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(11),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(14),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(12),
- combout => \myVirtualToplevel|UART1|RX_FIFO~26_combout\);
-
--- Location: FF_X16_Y5_N2
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~29_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(16));
-
--- Location: FF_X14_Y5_N7
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[4]~DUPLICATE_q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(9));
-
--- Location: FF_X13_Y5_N5
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_FIFO~32_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0));
-
--- Location: FF_X13_Y5_N28
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~5_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2));
-
--- Location: FF_X13_Y5_N23
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~9_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4));
-
--- Location: FF_X13_Y5_N2
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3));
-
--- Location: FF_X13_Y5_N11
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1));
-
--- Location: MLABCELL_X13_Y5_N0
-\myVirtualToplevel|UART1|RX_FIFO~27\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO~27_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3) & ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0) &
--- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2) & \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3) & ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1) & (
--- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0) & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2) & !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4))) ) ) ) # ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3) & (
--- !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2) & \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4))) ) ) ) # (
--- !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(3) & ( !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(1) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(0) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(2) &
--- !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(4))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000001000000000001000000010000010000000100000000000100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(0),
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(2),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(4),
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(3),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(1),
- combout => \myVirtualToplevel|UART1|RX_FIFO~27_combout\);
-
--- Location: FF_X14_Y5_N59
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~1_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(10));
-
--- Location: FF_X16_Y5_N59
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(7));
-
--- Location: FF_X16_Y5_N28
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~17_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(6));
-
--- Location: FF_X16_Y5_N11
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|Add3~13_sumout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(8));
-
--- Location: FF_X16_Y5_N14
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(5));
-
--- Location: LABCELL_X16_Y5_N9
-\myVirtualToplevel|UART1|RX_FIFO~28\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO~28_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(5) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(6) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(7) $
--- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(8)))) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(5) & ( (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(6) & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(7) $
--- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(8)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000110000110000000011000000001100000000110000110000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(7),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(6),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(8),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(5),
- combout => \myVirtualToplevel|UART1|RX_FIFO~28_combout\);
-
--- Location: LABCELL_X14_Y5_N57
-\myVirtualToplevel|UART1|RX_FIFO~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO~29_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO~28_combout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~27_combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(9) $ (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(10))))
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001010000001010000101000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(9),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~27_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(10),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~28_combout\,
- combout => \myVirtualToplevel|UART1|RX_FIFO~29_combout\);
-
--- Location: LABCELL_X16_Y5_N0
-\myVirtualToplevel|UART1|RX_FIFO~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO~30_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO~29_combout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~26_combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(15) $ (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(16))))
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001100000000110000110000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(15),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~26_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(16),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~29_combout\,
- combout => \myVirtualToplevel|UART1|RX_FIFO~30_combout\);
-
--- Location: FF_X16_Y6_N43
-\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_DATA_READY~1_combout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\);
-
--- Location: LABCELL_X16_Y6_N3
-\myVirtualToplevel|UART1|RX_DATA[0]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ = ( \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & ( !\myVirtualToplevel|UART1|RX_FIFO~30_combout\ ) ) # ( !\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|UART1|RX_FIFO~30_combout\ & ((!\myVirtualToplevel|UART1|RX_INTR~0_combout\) # (!\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000010100000111100001010000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~30_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\);
-
--- Location: MLABCELL_X13_Y5_N12
-\myVirtualToplevel|UART1|RX_FIFO~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO~33_combout\ = ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) &
--- !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR[5]~DUPLICATE_q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4),
- combout => \myVirtualToplevel|UART1|RX_FIFO~33_combout\);
-
--- Location: MLABCELL_X13_Y6_N48
-\myVirtualToplevel|UART1|RX_FIFO~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO~34_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO~32_combout\ & ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & (\myVirtualToplevel|UART1|RX_FIFO~33_combout\ &
--- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) & !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0),
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~33_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1),
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~32_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6),
- combout => \myVirtualToplevel|UART1|RX_FIFO~34_combout\);
-
--- Location: FF_X14_Y6_N13
-\myVirtualToplevel|UART1|RX_FIFO~24\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO~24_q\);
-
--- Location: LABCELL_X16_Y6_N48
-\myVirtualToplevel|UART1|RX_FIFO~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO~35_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\ ) # ( !\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~0_combout\ & ( \myVirtualToplevel|UART1|RX_FIFO~17_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~17_q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\,
- combout => \myVirtualToplevel|UART1|RX_FIFO~35_combout\);
-
--- Location: FF_X16_Y6_N49
-\myVirtualToplevel|UART1|RX_FIFO~17\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_FIFO~35_combout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO~17_q\);
-
--- Location: LABCELL_X16_Y6_N51
-\myVirtualToplevel|UART1|RX_DATA[0]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ = ( \myVirtualToplevel|UART1|RX_INTR~0_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & (((!\myVirtualToplevel|UART1|RX_FIFO~17_q\ & !\myVirtualToplevel|UART1|RX_FIFO~30_combout\)) #
--- (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\))) # (\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO~17_q\ & (!\myVirtualToplevel|UART1|RX_FIFO~30_combout\))) ) ) # ( !\myVirtualToplevel|UART1|RX_INTR~0_combout\ & (
--- (!\myVirtualToplevel|UART1|RX_FIFO~17_q\ & !\myVirtualToplevel|UART1|RX_FIFO~30_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000011000000110000001100000011000000111010101100000011101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~17_q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~30_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\,
- combout => \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\);
-
--- Location: LABCELL_X14_Y6_N12
-\myVirtualToplevel|UART1|RX_DATA~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA~8_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) # (\myVirtualToplevel|UART1|RX_FIFO~24_q\) ) ) ) #
--- ( !\myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & \myVirtualToplevel|UART1|RX_FIFO~24_q\) ) ) ) # (
--- \myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(23)))) #
--- (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_BUFFER[7]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & (
--- (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(23)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a6\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011010100110101001101010011010100000000000011111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(23),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~24_q\,
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER[7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\,
- combout => \myVirtualToplevel|UART1|RX_DATA~8_combout\);
-
--- Location: MLABCELL_X13_Y6_N36
-\myVirtualToplevel|UART1|RX_DATA[6]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA[6]~9_combout\ = ( \myVirtualToplevel|UART1|RX_DATA~8_combout\ & ( ((\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\)) # (\myVirtualToplevel|UART1|RX_DATA\(6)) ) ) # (
--- !\myVirtualToplevel|UART1|RX_DATA~8_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA\(6) & ((!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(6),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~8_combout\,
- combout => \myVirtualToplevel|UART1|RX_DATA[6]~9_combout\);
-
--- Location: FF_X13_Y6_N37
-\myVirtualToplevel|UART1|RX_DATA[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_DATA[6]~9_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_DATA\(6));
-
--- Location: LABCELL_X14_Y10_N39
-\myVirtualToplevel|IO_DATA_READ~47\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~47_combout\ = ( \myVirtualToplevel|UART1|RX_DATA\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (!\myVirtualToplevel|UART1|RX_ENABLE~q\))) ) ) # (
--- !\myVirtualToplevel|UART1|RX_DATA\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|UART1|RX_ENABLE~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000000000000010100000000010101010101000001010101010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(6),
- combout => \myVirtualToplevel|IO_DATA_READ~47_combout\);
-
--- Location: LABCELL_X12_Y9_N0
-\myVirtualToplevel|UART0|RX_ENABLE~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_ENABLE~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- combout => \myVirtualToplevel|UART0|RX_ENABLE~0_combout\);
-
--- Location: FF_X12_Y9_N2
-\myVirtualToplevel|UART0|RX_ENABLE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_ENABLE~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_ENABLE~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_ENABLE~q\);
-
--- Location: LABCELL_X12_Y9_N54
-\myVirtualToplevel|UART0|RX_RESET~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_RESET~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) #
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( !\myVirtualToplevel|UART0_CS~combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( !\myVirtualToplevel|UART0_CS~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111111110101111101011111010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\,
- combout => \myVirtualToplevel|UART0|RX_RESET~0_combout\);
-
--- Location: FF_X12_Y9_N56
-\myVirtualToplevel|UART0|RX_RESET\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_RESET~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_RESET~q\);
-
--- Location: LABCELL_X10_Y6_N15
-\myVirtualToplevel|UART0|RX_DATA[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ = ( !\myVirtualToplevel|UART0|RX_ENABLE~q\ & ( \myVirtualToplevel|UART0|RX_RESET~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_RESET~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- combout => \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\);
-
--- Location: FF_X9_Y5_N29
-\myVirtualToplevel|UART0|RXD_SYNC2\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \UART_RX_0~input_o\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RXD_SYNC2~q\);
-
--- Location: FF_X9_Y5_N11
-\myVirtualToplevel|UART0|RXD_SYNC\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RXD_SYNC2~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RXD_SYNC~q\);
-
--- Location: LABCELL_X10_Y4_N51
-\myVirtualToplevel|UART0|Selector6~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Selector6~0_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(7) & ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(7),
- combout => \myVirtualToplevel|UART0|Selector6~0_combout\);
-
--- Location: LABCELL_X7_Y7_N30
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5_combout\);
-
--- Location: LABCELL_X12_Y9_N39
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\ = ( \myVirtualToplevel|UART0_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000001000000010000000100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\,
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\);
-
--- Location: FF_X7_Y7_N31
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[0]~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(0));
-
--- Location: LABCELL_X7_Y7_N12
-\myVirtualToplevel|UART0|RX_COUNTER~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~15_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(0) & ( (!\myVirtualToplevel|UART0|Equal1~4_combout\ & !\myVirtualToplevel|UART0|RX_COUNTER\(0)) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(0) & (
--- (!\myVirtualToplevel|UART0|RX_COUNTER\(0)) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100110011111111110011001111001100000000001100110000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(0),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(0),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~15_combout\);
-
--- Location: FF_X7_Y7_N35
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(1));
-
--- Location: MLABCELL_X9_Y5_N33
-\myVirtualToplevel|UART0|RX_COUNTER[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\ = ( \myVirtualToplevel|UART0|RXD_SYNC~q\ & ( (!\myVirtualToplevel|UART0|RX_ENABLE~q\ & \myVirtualToplevel|UART0|RX_STATE.idle~q\) ) ) # ( !\myVirtualToplevel|UART0|RXD_SYNC~q\ & (
--- !\myVirtualToplevel|UART0|RX_ENABLE~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101000001010000010100000101000001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\,
- combout => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\);
-
--- Location: FF_X7_Y7_N13
-\myVirtualToplevel|UART0|RX_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~15_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(1),
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(0));
-
--- Location: MLABCELL_X9_Y7_N0
-\myVirtualToplevel|UART0|Add1~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~54\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(0),
- cin => GND,
- cout => \myVirtualToplevel|UART0|Add1~54\);
-
--- Location: MLABCELL_X9_Y7_N3
-\myVirtualToplevel|UART0|Add1~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~17_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~54\ ))
--- \myVirtualToplevel|UART0|Add1~18\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(1),
- cin => \myVirtualToplevel|UART0|Add1~54\,
- sumout => \myVirtualToplevel|UART0|Add1~17_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~18\);
-
--- Location: LABCELL_X7_Y7_N15
-\myVirtualToplevel|UART0|RX_COUNTER~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~6_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(1) & ( (\myVirtualToplevel|UART0|Equal1~4_combout\) # (\myVirtualToplevel|UART0|Add1~17_sumout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(1) & (
--- (\myVirtualToplevel|UART0|Add1~17_sumout\ & !\myVirtualToplevel|UART0|Equal1~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010001000100010001000100010001110111011101110111011101110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Add1~17_sumout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(1),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~6_combout\);
-
--- Location: LABCELL_X7_Y7_N27
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1_combout\);
-
--- Location: FF_X7_Y7_N28
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(2));
-
--- Location: LABCELL_X7_Y7_N42
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell_combout\ = !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(2)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(2),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell_combout\);
-
--- Location: FF_X7_Y7_N16
-\myVirtualToplevel|UART0|RX_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~6_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[2]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(1));
-
--- Location: MLABCELL_X9_Y7_N6
-\myVirtualToplevel|UART0|Add1~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~21_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~18\ ))
--- \myVirtualToplevel|UART0|Add1~22\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(2),
- cin => \myVirtualToplevel|UART0|Add1~18\,
- sumout => \myVirtualToplevel|UART0|Add1~21_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~22\);
-
--- Location: LABCELL_X7_Y7_N45
-\myVirtualToplevel|UART0|RX_COUNTER~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~7_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(2) & ( (\myVirtualToplevel|UART0|Add1~21_sumout\ & !\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(2) & (
--- (\myVirtualToplevel|UART0|Equal1~4_combout\) # (\myVirtualToplevel|UART0|Add1~21_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101111101011111010111110101111101010000010100000101000001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Add1~21_sumout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(2),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~7_combout\);
-
--- Location: LABCELL_X7_Y7_N54
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2_combout\);
-
--- Location: FF_X7_Y7_N55
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~2_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(3));
-
--- Location: LABCELL_X7_Y7_N3
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell_combout\ = !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(3)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(3),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell_combout\);
-
--- Location: FF_X7_Y7_N46
-\myVirtualToplevel|UART0|RX_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~7_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[3]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(2));
-
--- Location: MLABCELL_X9_Y7_N9
-\myVirtualToplevel|UART0|Add1~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~25_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~22\ ))
--- \myVirtualToplevel|UART0|Add1~26\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(3),
- cin => \myVirtualToplevel|UART0|Add1~22\,
- sumout => \myVirtualToplevel|UART0|Add1~25_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~26\);
-
--- Location: LABCELL_X7_Y7_N0
-\myVirtualToplevel|UART0|RX_COUNTER~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~8_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(3) & ( (\myVirtualToplevel|UART0|Add1~25_sumout\ & !\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(3) & (
--- (\myVirtualToplevel|UART0|Equal1~4_combout\) # (\myVirtualToplevel|UART0|Add1~25_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111111111111000011111111111100001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_Add1~25_sumout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(3),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~8_combout\);
-
--- Location: LABCELL_X7_Y7_N57
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3_combout\);
-
--- Location: FF_X7_Y7_N59
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(4));
-
--- Location: LABCELL_X7_Y7_N9
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell_combout\ = !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(4)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(4),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell_combout\);
-
--- Location: FF_X7_Y7_N1
-\myVirtualToplevel|UART0|RX_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~8_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[4]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(3));
-
--- Location: MLABCELL_X9_Y7_N12
-\myVirtualToplevel|UART0|Add1~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~29_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~26\ ))
--- \myVirtualToplevel|UART0|Add1~30\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(4),
- cin => \myVirtualToplevel|UART0|Add1~26\,
- sumout => \myVirtualToplevel|UART0|Add1~29_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~30\);
-
--- Location: LABCELL_X7_Y7_N6
-\myVirtualToplevel|UART0|RX_COUNTER~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~9_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(4) & ( (\myVirtualToplevel|UART0|Add1~29_sumout\ & !\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(4) & (
--- (\myVirtualToplevel|UART0|Equal1~4_combout\) # (\myVirtualToplevel|UART0|Add1~29_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111111111111000011111111111100001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_Add1~29_sumout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(4),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~9_combout\);
-
--- Location: LABCELL_X10_Y7_N24
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4_combout\);
-
--- Location: FF_X10_Y7_N25
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(5));
-
--- Location: LABCELL_X7_Y7_N24
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(5) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(5),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell_combout\);
-
--- Location: FF_X7_Y7_N8
-\myVirtualToplevel|UART0|RX_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~9_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[5]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(4));
-
--- Location: MLABCELL_X9_Y7_N48
-\myVirtualToplevel|UART0|Equal1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal1~1_combout\ = ( !\myVirtualToplevel|UART0|RX_COUNTER\(1) & ( (!\myVirtualToplevel|UART0|RX_COUNTER\(3) & (!\myVirtualToplevel|UART0|RX_COUNTER\(4) & !\myVirtualToplevel|UART0|RX_COUNTER\(2))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(3),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(4),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(2),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(1),
- combout => \myVirtualToplevel|UART0|Equal1~1_combout\);
-
--- Location: FF_X10_Y7_N11
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(9));
-
--- Location: FF_X10_Y7_N14
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(7));
-
--- Location: MLABCELL_X9_Y7_N15
-\myVirtualToplevel|UART0|Add1~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~33_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~30\ ))
--- \myVirtualToplevel|UART0|Add1~34\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(5),
- cin => \myVirtualToplevel|UART0|Add1~30\,
- sumout => \myVirtualToplevel|UART0|Add1~33_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~34\);
-
--- Location: LABCELL_X10_Y7_N21
-\myVirtualToplevel|UART0|RX_COUNTER~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~10_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(5) & ( (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~33_sumout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(5) & (
--- (\myVirtualToplevel|UART0|Add1~33_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011111100111111001111110011111100001100000011000000110000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Add1~33_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(5),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~10_combout\);
-
--- Location: FF_X10_Y7_N16
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(6));
-
--- Location: FF_X10_Y7_N23
-\myVirtualToplevel|UART0|RX_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~10_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(6),
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(5));
-
--- Location: MLABCELL_X9_Y7_N18
-\myVirtualToplevel|UART0|Add1~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~37_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~34\ ))
--- \myVirtualToplevel|UART0|Add1~38\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(6),
- cin => \myVirtualToplevel|UART0|Add1~34\,
- sumout => \myVirtualToplevel|UART0|Add1~37_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~38\);
-
--- Location: LABCELL_X10_Y7_N18
-\myVirtualToplevel|UART0|RX_COUNTER~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~11_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(6) & ( (\myVirtualToplevel|UART0|Add1~37_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(6) & (
--- (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~37_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Add1~37_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(6),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~11_combout\);
-
--- Location: FF_X10_Y7_N20
-\myVirtualToplevel|UART0|RX_COUNTER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~11_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(7),
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(6));
-
--- Location: MLABCELL_X9_Y7_N21
-\myVirtualToplevel|UART0|Add1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~1_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~38\ ))
--- \myVirtualToplevel|UART0|Add1~2\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[7]~DUPLICATE_q\,
- cin => \myVirtualToplevel|UART0|Add1~38\,
- sumout => \myVirtualToplevel|UART0|Add1~1_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~2\);
-
--- Location: LABCELL_X10_Y7_N39
-\myVirtualToplevel|UART0|RX_COUNTER~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~2_combout\ = (!\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|Add1~1_sumout\))) # (\myVirtualToplevel|UART0|Equal1~4_combout\ & (\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(7)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001111001111000000111100111100000011110011110000001111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(7),
- datad => \myVirtualToplevel|UART0|ALT_INV_Add1~1_sumout\,
- combout => \myVirtualToplevel|UART0|RX_COUNTER~2_combout\);
-
--- Location: FF_X10_Y7_N7
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8));
-
--- Location: FF_X10_Y7_N40
-\myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~2_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8),
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER[7]~DUPLICATE_q\);
-
--- Location: MLABCELL_X9_Y7_N24
-\myVirtualToplevel|UART0|Add1~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~5_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~2\ ))
--- \myVirtualToplevel|UART0|Add1~6\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(8),
- cin => \myVirtualToplevel|UART0|Add1~2\,
- sumout => \myVirtualToplevel|UART0|Add1~5_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~6\);
-
--- Location: LABCELL_X10_Y7_N36
-\myVirtualToplevel|UART0|RX_COUNTER~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~3_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8) & ( (\myVirtualToplevel|UART0|Add1~5_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8) & (
--- (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~5_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Add1~5_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(8),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~3_combout\);
-
--- Location: FF_X10_Y7_N38
-\myVirtualToplevel|UART0|RX_COUNTER[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~3_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(9),
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(8));
-
--- Location: MLABCELL_X9_Y7_N27
-\myVirtualToplevel|UART0|Add1~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~9_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~6\ ))
--- \myVirtualToplevel|UART0|Add1~10\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(9),
- cin => \myVirtualToplevel|UART0|Add1~6\,
- sumout => \myVirtualToplevel|UART0|Add1~9_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~10\);
-
--- Location: LABCELL_X10_Y7_N54
-\myVirtualToplevel|UART0|RX_COUNTER~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~4_combout\ = (!\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|Add1~9_sumout\))) # (\myVirtualToplevel|UART0|Equal1~4_combout\ & (\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(9)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100110011000011110011001100001111001100110000111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(9),
- datac => \myVirtualToplevel|UART0|ALT_INV_Add1~9_sumout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- combout => \myVirtualToplevel|UART0|RX_COUNTER~4_combout\);
-
--- Location: LABCELL_X10_Y7_N27
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0_combout\);
-
--- Location: FF_X10_Y7_N28
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(10));
-
--- Location: LABCELL_X10_Y7_N9
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell_combout\ = !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(10)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(10),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell_combout\);
-
--- Location: FF_X10_Y7_N56
-\myVirtualToplevel|UART0|RX_COUNTER[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~4_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[10]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(9));
-
--- Location: MLABCELL_X9_Y7_N30
-\myVirtualToplevel|UART0|Add1~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~13_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~10\ ))
--- \myVirtualToplevel|UART0|Add1~14\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[10]~DUPLICATE_q\,
- cin => \myVirtualToplevel|UART0|Add1~10\,
- sumout => \myVirtualToplevel|UART0|Add1~13_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~14\);
-
--- Location: LABCELL_X10_Y7_N3
-\myVirtualToplevel|UART0|RX_COUNTER~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~5_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(10) & ( (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~13_sumout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(10) & (
--- (\myVirtualToplevel|UART0|Add1~13_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011111100111111001111110011111100001100000011000000110000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Add1~13_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(10),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~5_combout\);
-
--- Location: LABCELL_X10_Y7_N42
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder_combout\);
-
--- Location: FF_X10_Y7_N43
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[11]~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11));
-
--- Location: FF_X10_Y7_N4
-\myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~5_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11),
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER[10]~DUPLICATE_q\);
-
--- Location: MLABCELL_X9_Y7_N33
-\myVirtualToplevel|UART0|Add1~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~41_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~14\ ))
--- \myVirtualToplevel|UART0|Add1~42\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(11),
- cin => \myVirtualToplevel|UART0|Add1~14\,
- sumout => \myVirtualToplevel|UART0|Add1~41_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~42\);
-
--- Location: LABCELL_X10_Y7_N0
-\myVirtualToplevel|UART0|RX_COUNTER~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~12_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11) & ( (\myVirtualToplevel|UART0|Add1~41_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11) & (
--- (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~41_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Add1~41_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(11),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~12_combout\);
-
--- Location: LABCELL_X10_Y7_N45
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(12),
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder_combout\);
-
--- Location: FF_X10_Y7_N47
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~DUPLICATE_q\);
-
--- Location: FF_X10_Y7_N2
-\myVirtualToplevel|UART0|RX_COUNTER[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~12_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~DUPLICATE_q\,
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(11));
-
--- Location: MLABCELL_X9_Y7_N36
-\myVirtualToplevel|UART0|Add1~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~45_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~42\ ))
--- \myVirtualToplevel|UART0|Add1~46\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(12),
- cin => \myVirtualToplevel|UART0|Add1~42\,
- sumout => \myVirtualToplevel|UART0|Add1~45_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~46\);
-
--- Location: FF_X10_Y7_N46
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[12]~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(12));
-
--- Location: LABCELL_X10_Y7_N51
-\myVirtualToplevel|UART0|RX_COUNTER~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~13_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(12) & ( (\myVirtualToplevel|UART0|Equal1~4_combout\) # (\myVirtualToplevel|UART0|Add1~45_sumout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(12) & (
--- (\myVirtualToplevel|UART0|Add1~45_sumout\ & !\myVirtualToplevel|UART0|Equal1~4_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_Add1~45_sumout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(12),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~13_combout\);
-
--- Location: FF_X7_Y7_N49
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]~DUPLICATE_q\);
-
--- Location: FF_X10_Y7_N53
-\myVirtualToplevel|UART0|RX_COUNTER[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~13_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]~DUPLICATE_q\,
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(12));
-
--- Location: MLABCELL_X9_Y7_N39
-\myVirtualToplevel|UART0|Add1~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~57_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~46\ ))
--- \myVirtualToplevel|UART0|Add1~58\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(13) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(13),
- cin => \myVirtualToplevel|UART0|Add1~46\,
- sumout => \myVirtualToplevel|UART0|Add1~57_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~58\);
-
--- Location: FF_X7_Y7_N50
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(13));
-
--- Location: LABCELL_X7_Y7_N36
-\myVirtualToplevel|UART0|RX_COUNTER~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~16_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(13) & ( (\myVirtualToplevel|UART0|Add1~57_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(13) & (
--- (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~57_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001100000000001100110000110011111111110011001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Add1~57_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(13),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~16_combout\);
-
--- Location: LABCELL_X7_Y7_N18
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[14]~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder_combout\);
-
--- Location: FF_X7_Y7_N19
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[14]~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(14));
-
--- Location: FF_X7_Y7_N37
-\myVirtualToplevel|UART0|RX_COUNTER[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~16_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(14),
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(13));
-
--- Location: MLABCELL_X9_Y7_N42
-\myVirtualToplevel|UART0|Add1~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~61_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~58\ ))
--- \myVirtualToplevel|UART0|Add1~62\ = CARRY(( \myVirtualToplevel|UART0|RX_COUNTER\(14) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(14),
- cin => \myVirtualToplevel|UART0|Add1~58\,
- sumout => \myVirtualToplevel|UART0|Add1~61_sumout\,
- cout => \myVirtualToplevel|UART0|Add1~62\);
-
--- Location: LABCELL_X7_Y7_N39
-\myVirtualToplevel|UART0|RX_COUNTER~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~17_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(14) & ( (\myVirtualToplevel|UART0|Add1~61_sumout\) # (\myVirtualToplevel|UART0|Equal1~4_combout\) ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(14) & (
--- (!\myVirtualToplevel|UART0|Equal1~4_combout\ & \myVirtualToplevel|UART0|Add1~61_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Add1~61_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(14),
- combout => \myVirtualToplevel|UART0|RX_COUNTER~17_combout\);
-
--- Location: FF_X7_Y7_N52
-\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15));
-
--- Location: FF_X7_Y7_N40
-\myVirtualToplevel|UART0|RX_COUNTER[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~17_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15),
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(14));
-
--- Location: MLABCELL_X9_Y7_N45
-\myVirtualToplevel|UART0|Add1~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add1~49_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add1~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(15),
- cin => \myVirtualToplevel|UART0|Add1~62\,
- sumout => \myVirtualToplevel|UART0|Add1~49_sumout\);
-
--- Location: MLABCELL_X9_Y5_N6
-\myVirtualToplevel|UART0|RX_COUNTER~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_COUNTER~14_combout\ = ( \myVirtualToplevel|UART0|RX_COUNTER\(15) & ( \myVirtualToplevel|UART0|RXD_SYNC~q\ & ( (!\myVirtualToplevel|UART0|RX_STATE.idle~q\) # ((!\myVirtualToplevel|UART0|Equal1~4_combout\ &
--- (\myVirtualToplevel|UART0|Add1~49_sumout\)) # (\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15))))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_COUNTER\(15) & ( \myVirtualToplevel|UART0|RXD_SYNC~q\ & (
--- (\myVirtualToplevel|UART0|RX_STATE.idle~q\ & ((!\myVirtualToplevel|UART0|Equal1~4_combout\ & (\myVirtualToplevel|UART0|Add1~49_sumout\)) # (\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15)))))) ) ) ) # (
--- \myVirtualToplevel|UART0|RX_COUNTER\(15) & ( !\myVirtualToplevel|UART0|RXD_SYNC~q\ & ( (\myVirtualToplevel|UART0|RX_STATE.idle~q\ & ((!\myVirtualToplevel|UART0|Equal1~4_combout\ & (\myVirtualToplevel|UART0|Add1~49_sumout\)) #
--- (\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15)))))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_COUNTER\(15) & ( !\myVirtualToplevel|UART0|RXD_SYNC~q\ & ( (\myVirtualToplevel|UART0|RX_STATE.idle~q\ &
--- ((!\myVirtualToplevel|UART0|Equal1~4_combout\ & (\myVirtualToplevel|UART0|Add1~49_sumout\)) # (\myVirtualToplevel|UART0|Equal1~4_combout\ & ((\myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(15)))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000111000000000100011100000000010001111111111101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Add1~49_sumout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK_DIVISOR\(15),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(15),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\,
- combout => \myVirtualToplevel|UART0|RX_COUNTER~14_combout\);
-
--- Location: FF_X9_Y5_N7
-\myVirtualToplevel|UART0|RX_COUNTER[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~14_combout\,
- ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(15));
-
--- Location: MLABCELL_X9_Y7_N57
-\myVirtualToplevel|UART0|Equal1~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal1~3_combout\ = ( !\myVirtualToplevel|UART0|RX_COUNTER\(14) & ( (!\myVirtualToplevel|UART0|RX_COUNTER\(0) & (!\myVirtualToplevel|UART0|RX_COUNTER\(15) & !\myVirtualToplevel|UART0|RX_COUNTER\(13))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(0),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(15),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(13),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(14),
- combout => \myVirtualToplevel|UART0|Equal1~3_combout\);
-
--- Location: MLABCELL_X9_Y7_N54
-\myVirtualToplevel|UART0|Equal1~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal1~2_combout\ = ( !\myVirtualToplevel|UART0|RX_COUNTER\(12) & ( (!\myVirtualToplevel|UART0|RX_COUNTER\(6) & (!\myVirtualToplevel|UART0|RX_COUNTER\(11) & !\myVirtualToplevel|UART0|RX_COUNTER\(5))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(6),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(11),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(5),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(12),
- combout => \myVirtualToplevel|UART0|Equal1~2_combout\);
-
--- Location: FF_X10_Y7_N41
-\myVirtualToplevel|UART0|RX_COUNTER[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~2_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(8),
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(7));
-
--- Location: FF_X10_Y7_N5
-\myVirtualToplevel|UART0|RX_COUNTER[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_COUNTER~5_combout\,
- asdata => \myVirtualToplevel|UART0|RX_CLOCK_DIVISOR\(11),
- sload => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- ena => \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_COUNTER\(10));
-
--- Location: LABCELL_X10_Y7_N48
-\myVirtualToplevel|UART0|Equal1~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal1~0_combout\ = (!\myVirtualToplevel|UART0|RX_COUNTER\(9) & (!\myVirtualToplevel|UART0|RX_COUNTER\(7) & (!\myVirtualToplevel|UART0|RX_COUNTER\(8) & !\myVirtualToplevel|UART0|RX_COUNTER\(10))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000100000000000000010000000000000001000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(9),
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(7),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(8),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER\(10),
- combout => \myVirtualToplevel|UART0|Equal1~0_combout\);
-
--- Location: MLABCELL_X9_Y7_N51
-\myVirtualToplevel|UART0|Equal1~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal1~4_combout\ = ( \myVirtualToplevel|UART0|Equal1~0_combout\ & ( (\myVirtualToplevel|UART0|Equal1~1_combout\ & (\myVirtualToplevel|UART0|Equal1~3_combout\ & \myVirtualToplevel|UART0|Equal1~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Equal1~1_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Equal1~3_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~2_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_Equal1~0_combout\,
- combout => \myVirtualToplevel|UART0|Equal1~4_combout\);
-
--- Location: MLABCELL_X9_Y5_N30
-\myVirtualToplevel|UART0|RX_CLOCK~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_CLOCK~0_combout\ = (\myVirtualToplevel|UART0|RX_STATE.idle~q\ & \myVirtualToplevel|UART0|Equal1~4_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000000000011001100000000001100110000000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Equal1~4_combout\,
- combout => \myVirtualToplevel|UART0|RX_CLOCK~0_combout\);
-
--- Location: FF_X9_Y5_N32
-\myVirtualToplevel|UART0|RX_CLOCK\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK~0_combout\,
- ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK~q\);
-
--- Location: MLABCELL_X9_Y5_N15
-\myVirtualToplevel|UART0|RX_BUFFER[1]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK~q\ & ( (\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART0|RX_STATE.start~q\ & !\myVirtualToplevel|UART0|RXD_SYNC~q\)) #
--- (\myVirtualToplevel|UART0|RX_STATE.bits~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000100000011110000010000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~q\,
- combout => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\);
-
--- Location: FF_X10_Y4_N53
-\myVirtualToplevel|UART0|RX_BUFFER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector6~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER\(6));
-
--- Location: LABCELL_X10_Y4_N48
-\myVirtualToplevel|UART0|Selector7~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Selector7~0_combout\ = (\myVirtualToplevel|UART0|RX_STATE.bits~q\ & \myVirtualToplevel|UART0|RX_BUFFER\(6))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000110000001100000011000000110000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(6),
- combout => \myVirtualToplevel|UART0|Selector7~0_combout\);
-
--- Location: FF_X10_Y4_N50
-\myVirtualToplevel|UART0|RX_BUFFER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector7~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER\(5));
-
--- Location: LABCELL_X10_Y4_N6
-\myVirtualToplevel|UART0|Selector8~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Selector8~0_combout\ = (\myVirtualToplevel|UART0|RX_STATE.bits~q\ & \myVirtualToplevel|UART0|RX_BUFFER\(5))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000110000001100000011000000110000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(5),
- combout => \myVirtualToplevel|UART0|Selector8~0_combout\);
-
--- Location: FF_X10_Y4_N8
-\myVirtualToplevel|UART0|RX_BUFFER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector8~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER\(4));
-
--- Location: LABCELL_X10_Y4_N9
-\myVirtualToplevel|UART0|Selector9~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Selector9~0_combout\ = (\myVirtualToplevel|UART0|RX_STATE.bits~q\ & \myVirtualToplevel|UART0|RX_BUFFER\(4))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000110000001100000011000000110000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(4),
- combout => \myVirtualToplevel|UART0|Selector9~0_combout\);
-
--- Location: FF_X10_Y4_N10
-\myVirtualToplevel|UART0|RX_BUFFER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector9~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER\(3));
-
--- Location: LABCELL_X10_Y4_N12
-\myVirtualToplevel|UART0|Selector10~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Selector10~0_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(3) & ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(3),
- combout => \myVirtualToplevel|UART0|Selector10~0_combout\);
-
--- Location: FF_X10_Y4_N13
-\myVirtualToplevel|UART0|RX_BUFFER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector10~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER\(2));
-
--- Location: LABCELL_X10_Y4_N3
-\myVirtualToplevel|UART0|Selector11~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Selector11~0_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(2) & ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(2),
- combout => \myVirtualToplevel|UART0|Selector11~0_combout\);
-
--- Location: FF_X10_Y4_N4
-\myVirtualToplevel|UART0|RX_BUFFER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector11~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER\(1));
-
--- Location: LABCELL_X10_Y4_N36
-\myVirtualToplevel|UART0|Selector12~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Selector12~0_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(1) & ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(1),
- combout => \myVirtualToplevel|UART0|Selector12~0_combout\);
-
--- Location: FF_X10_Y4_N38
-\myVirtualToplevel|UART0|RX_BUFFER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector12~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER\(0));
-
--- Location: FF_X9_Y5_N31
-\myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_CLOCK~0_combout\,
- ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\);
-
--- Location: MLABCELL_X9_Y5_N18
-\myVirtualToplevel|UART0|RX_STATE.stop~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\ & ( \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\ ) ) # ( !\myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|UART0|RX_STATE.idle~q\ & \myVirtualToplevel|UART0|RX_COUNTER[0]~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_COUNTER[0]~1_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\);
-
--- Location: MLABCELL_X9_Y5_N48
-\myVirtualToplevel|UART0|RX_STATE.stop~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_STATE.stop~1_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( (\myVirtualToplevel|UART0|RX_STATE.bits~q\ & (((\myVirtualToplevel|UART0|RX_BUFFER\(0) & !\myVirtualToplevel|UART0|RX_ENABLE~q\)) #
--- (\myVirtualToplevel|UART0|RX_STATE.stop~q\))) ) ) # ( !\myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( ((\myVirtualToplevel|UART0|RX_STATE.bits~q\ & (\myVirtualToplevel|UART0|RX_BUFFER\(0) & !\myVirtualToplevel|UART0|RX_ENABLE~q\))) #
--- (\myVirtualToplevel|UART0|RX_STATE.stop~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000011111111000100001111111100010000010101010001000001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(0),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~0_combout\,
- combout => \myVirtualToplevel|UART0|RX_STATE.stop~1_combout\);
-
--- Location: FF_X9_Y5_N50
-\myVirtualToplevel|UART0|RX_STATE.stop\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_STATE.stop~1_combout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_STATE.stop~q\);
-
--- Location: MLABCELL_X9_Y5_N51
-\myVirtualToplevel|UART0|RX_STATE.stop~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( (!\myVirtualToplevel|UART0|RX_STATE.bits~q\) # ((\myVirtualToplevel|UART0|RX_BUFFER\(0) & !\myVirtualToplevel|UART0|RX_ENABLE~q\)) ) ) # (
--- !\myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( (\myVirtualToplevel|UART0|RX_STATE.bits~q\ & (\myVirtualToplevel|UART0|RX_BUFFER\(0) & !\myVirtualToplevel|UART0|RX_ENABLE~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100000000000100010000000010111011101010101011101110101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(0),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~0_combout\,
- combout => \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\);
-
--- Location: MLABCELL_X9_Y5_N12
-\myVirtualToplevel|UART0|RX_STATE.idle~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_STATE.idle~0_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ & ( (!\myVirtualToplevel|UART0|RX_STATE.start~q\ & ((!\myVirtualToplevel|UART0|RX_STATE.stop~q\))) # (\myVirtualToplevel|UART0|RX_STATE.start~q\ &
--- (!\myVirtualToplevel|UART0|RXD_SYNC~q\)) ) ) # ( !\myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ & ( \myVirtualToplevel|UART0|RX_STATE.idle~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111111100100111001001110010011100100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~2_combout\,
- combout => \myVirtualToplevel|UART0|RX_STATE.idle~0_combout\);
-
--- Location: FF_X9_Y5_N14
-\myVirtualToplevel|UART0|RX_STATE.idle\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_STATE.idle~0_combout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_STATE.idle~q\);
-
--- Location: MLABCELL_X9_Y5_N21
-\myVirtualToplevel|UART0|RX_STATE.start~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_STATE.start~0_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ & ( !\myVirtualToplevel|UART0|RX_STATE.idle~q\ ) ) # ( !\myVirtualToplevel|UART0|RX_STATE.stop~2_combout\ & (
--- \myVirtualToplevel|UART0|RX_STATE.start~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111111110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.idle~q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~2_combout\,
- combout => \myVirtualToplevel|UART0|RX_STATE.start~0_combout\);
-
--- Location: FF_X9_Y5_N23
-\myVirtualToplevel|UART0|RX_STATE.start\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_STATE.start~0_combout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_STATE.start~q\);
-
--- Location: MLABCELL_X9_Y5_N54
-\myVirtualToplevel|UART0|RX_STATE.bits~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_STATE.bits~0_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ & ( \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( ((!\myVirtualToplevel|UART0|RX_BUFFER\(0)) # ((!\myVirtualToplevel|UART0|RXD_SYNC~q\ &
--- \myVirtualToplevel|UART0|RX_STATE.start~q\))) # (\myVirtualToplevel|UART0|RX_ENABLE~q\) ) ) ) # ( !\myVirtualToplevel|UART0|RX_STATE.bits~q\ & ( \myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( (!\myVirtualToplevel|UART0|RXD_SYNC~q\ &
--- \myVirtualToplevel|UART0|RX_STATE.start~q\) ) ) ) # ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ & ( !\myVirtualToplevel|UART0|RX_STATE.stop~0_combout\ & ( ((!\myVirtualToplevel|UART0|RX_BUFFER\(0)) # ((!\myVirtualToplevel|UART0|RXD_SYNC~q\ &
--- \myVirtualToplevel|UART0|RX_STATE.start~q\))) # (\myVirtualToplevel|UART0|RX_ENABLE~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111110101110100001100000011001111111101011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.start~q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(0),
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~0_combout\,
- combout => \myVirtualToplevel|UART0|RX_STATE.bits~0_combout\);
-
--- Location: FF_X9_Y5_N56
-\myVirtualToplevel|UART0|RX_STATE.bits\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_STATE.bits~0_combout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_STATE.bits~q\);
-
--- Location: LABCELL_X10_Y4_N39
-\myVirtualToplevel|UART0|Selector4~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Selector4~0_combout\ = (!\myVirtualToplevel|UART0|RX_STATE.bits~q\) # (\myVirtualToplevel|UART0|RXD_SYNC~q\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011111111110011001111111111001100111111111100110011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\,
- combout => \myVirtualToplevel|UART0|Selector4~0_combout\);
-
--- Location: FF_X10_Y4_N40
-\myVirtualToplevel|UART0|RX_BUFFER[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector4~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER\(8));
-
--- Location: LABCELL_X10_Y4_N57
-\myVirtualToplevel|UART0|Selector5~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Selector5~0_combout\ = ( \myVirtualToplevel|UART0|RX_STATE.bits~q\ & ( \myVirtualToplevel|UART0|RX_BUFFER\(8) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.bits~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(8),
- combout => \myVirtualToplevel|UART0|Selector5~0_combout\);
-
--- Location: FF_X10_Y4_N58
-\myVirtualToplevel|UART0|RX_BUFFER[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector5~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER\(7));
-
--- Location: FF_X10_Y5_N2
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_BUFFER\(7),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(23));
-
--- Location: LABCELL_X12_Y5_N24
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1_combout\ = !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(0),
- combout => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1_combout\);
-
--- Location: MLABCELL_X9_Y5_N45
-\myVirtualToplevel|UART0|RX_INTR~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_INTR~0_combout\ = ( \myVirtualToplevel|UART0|RX_CLOCK~DUPLICATE_q\ & ( (\myVirtualToplevel|UART0|RX_STATE.stop~q\ & \myVirtualToplevel|UART0|RXD_SYNC~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000101000001010000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART0|RX_INTR~0_combout\);
-
--- Location: LABCELL_X12_Y5_N0
-\myVirtualToplevel|UART0|Add3~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add3~5_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|UART0|Add3~6\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\,
- cin => GND,
- sumout => \myVirtualToplevel|UART0|Add3~5_sumout\,
- cout => \myVirtualToplevel|UART0|Add3~6\);
-
--- Location: LABCELL_X12_Y5_N30
-\myVirtualToplevel|UART0|Add4~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add4~5_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0) ) + ( !VCC ))
--- \myVirtualToplevel|UART0|Add4~6\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0) ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(0),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1),
- cin => GND,
- sumout => \myVirtualToplevel|UART0|Add4~5_sumout\,
- cout => \myVirtualToplevel|UART0|Add4~6\);
-
--- Location: FF_X12_Y5_N32
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add4~5_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1));
-
--- Location: LABCELL_X12_Y5_N33
-\myVirtualToplevel|UART0|Add4~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add4~21_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~6\ ))
--- \myVirtualToplevel|UART0|Add4~22\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2),
- cin => \myVirtualToplevel|UART0|Add4~6\,
- sumout => \myVirtualToplevel|UART0|Add4~21_sumout\,
- cout => \myVirtualToplevel|UART0|Add4~22\);
-
--- Location: FF_X12_Y5_N35
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add4~21_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2));
-
--- Location: LABCELL_X12_Y5_N36
-\myVirtualToplevel|UART0|Add4~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add4~9_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~22\ ))
--- \myVirtualToplevel|UART0|Add4~10\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3),
- cin => \myVirtualToplevel|UART0|Add4~22\,
- sumout => \myVirtualToplevel|UART0|Add4~9_sumout\,
- cout => \myVirtualToplevel|UART0|Add4~10\);
-
--- Location: FF_X12_Y5_N38
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add4~9_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3));
-
--- Location: LABCELL_X12_Y5_N39
-\myVirtualToplevel|UART0|Add4~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add4~1_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~10\ ))
--- \myVirtualToplevel|UART0|Add4~2\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4),
- cin => \myVirtualToplevel|UART0|Add4~10\,
- sumout => \myVirtualToplevel|UART0|Add4~1_sumout\,
- cout => \myVirtualToplevel|UART0|Add4~2\);
-
--- Location: FF_X12_Y5_N40
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add4~1_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4));
-
--- Location: LABCELL_X12_Y5_N42
-\myVirtualToplevel|UART0|Add4~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add4~25_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~2\ ))
--- \myVirtualToplevel|UART0|Add4~26\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5),
- cin => \myVirtualToplevel|UART0|Add4~2\,
- sumout => \myVirtualToplevel|UART0|Add4~25_sumout\,
- cout => \myVirtualToplevel|UART0|Add4~26\);
-
--- Location: FF_X12_Y5_N44
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add4~25_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5));
-
--- Location: LABCELL_X12_Y5_N45
-\myVirtualToplevel|UART0|Add4~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add4~13_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~26\ ))
--- \myVirtualToplevel|UART0|Add4~14\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6),
- cin => \myVirtualToplevel|UART0|Add4~26\,
- sumout => \myVirtualToplevel|UART0|Add4~13_sumout\,
- cout => \myVirtualToplevel|UART0|Add4~14\);
-
--- Location: FF_X12_Y5_N47
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add4~13_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6));
-
--- Location: LABCELL_X12_Y5_N48
-\myVirtualToplevel|UART0|Add4~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add4~17_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add4~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7),
- cin => \myVirtualToplevel|UART0|Add4~14\,
- sumout => \myVirtualToplevel|UART0|Add4~17_sumout\);
-
--- Location: FF_X12_Y5_N49
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add4~17_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7));
-
--- Location: LABCELL_X12_Y5_N3
-\myVirtualToplevel|UART0|Add3~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add3~9_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~6\ ))
--- \myVirtualToplevel|UART0|Add3~10\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1),
- cin => \myVirtualToplevel|UART0|Add3~6\,
- sumout => \myVirtualToplevel|UART0|Add3~9_sumout\,
- cout => \myVirtualToplevel|UART0|Add3~10\);
-
--- Location: LABCELL_X12_Y5_N6
-\myVirtualToplevel|UART0|Add3~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add3~25_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~10\ ))
--- \myVirtualToplevel|UART0|Add3~26\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2),
- cin => \myVirtualToplevel|UART0|Add3~10\,
- sumout => \myVirtualToplevel|UART0|Add3~25_sumout\,
- cout => \myVirtualToplevel|UART0|Add3~26\);
-
--- Location: FF_X12_Y5_N8
-\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add3~25_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2));
-
--- Location: LABCELL_X12_Y5_N9
-\myVirtualToplevel|UART0|Add3~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add3~13_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~26\ ))
--- \myVirtualToplevel|UART0|Add3~14\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3),
- cin => \myVirtualToplevel|UART0|Add3~26\,
- sumout => \myVirtualToplevel|UART0|Add3~13_sumout\,
- cout => \myVirtualToplevel|UART0|Add3~14\);
-
--- Location: FF_X12_Y5_N11
-\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add3~13_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3));
-
--- Location: LABCELL_X12_Y5_N12
-\myVirtualToplevel|UART0|Add3~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add3~1_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~14\ ))
--- \myVirtualToplevel|UART0|Add3~2\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4),
- cin => \myVirtualToplevel|UART0|Add3~14\,
- sumout => \myVirtualToplevel|UART0|Add3~1_sumout\,
- cout => \myVirtualToplevel|UART0|Add3~2\);
-
--- Location: FF_X10_Y6_N19
-\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~1_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4));
-
--- Location: LABCELL_X12_Y5_N15
-\myVirtualToplevel|UART0|Add3~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add3~29_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~2\ ))
--- \myVirtualToplevel|UART0|Add3~30\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5),
- cin => \myVirtualToplevel|UART0|Add3~2\,
- sumout => \myVirtualToplevel|UART0|Add3~29_sumout\,
- cout => \myVirtualToplevel|UART0|Add3~30\);
-
--- Location: FF_X12_Y5_N17
-\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add3~29_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5));
-
--- Location: LABCELL_X12_Y5_N18
-\myVirtualToplevel|UART0|Add3~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add3~17_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~30\ ))
--- \myVirtualToplevel|UART0|Add3~18\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6),
- cin => \myVirtualToplevel|UART0|Add3~30\,
- sumout => \myVirtualToplevel|UART0|Add3~17_sumout\,
- cout => \myVirtualToplevel|UART0|Add3~18\);
-
--- Location: FF_X12_Y5_N20
-\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add3~17_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6));
-
--- Location: LABCELL_X12_Y5_N21
-\myVirtualToplevel|UART0|Add3~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add3~21_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add3~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7),
- cin => \myVirtualToplevel|UART0|Add3~18\,
- sumout => \myVirtualToplevel|UART0|Add3~21_sumout\);
-
--- Location: FF_X12_Y5_N23
-\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add3~21_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7));
-
--- Location: LABCELL_X10_Y6_N54
-\myVirtualToplevel|UART0|Equal2~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal2~2_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & ( (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7)))) ) ) # (
--- !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & ( (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000110000110000000011000000001100000000110000110000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6),
- combout => \myVirtualToplevel|UART0|Equal2~2_combout\);
-
--- Location: LABCELL_X12_Y6_N45
-\myVirtualToplevel|UART0|Equal2~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal2~1_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & ( (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4)))) ) ) # (
--- !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & ( (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010010100000000101001010000000000000000101001010000000010100101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3),
- combout => \myVirtualToplevel|UART0|Equal2~1_combout\);
-
--- Location: FF_X12_Y5_N58
-\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~5_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0));
-
--- Location: FF_X12_Y5_N25
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1_combout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y6_N42
-\myVirtualToplevel|UART0|Equal2~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal2~0_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1)))) )
--- ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100001100000000110000110000000000000000110000110000000011000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART0|Equal2~0_combout\);
-
--- Location: LABCELL_X10_Y6_N6
-\myVirtualToplevel|UART0|Equal2~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal2~3_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) & ( (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) $ (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5)))) ) ) # (
--- !\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) & ( (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) $ (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000001010000010100000101000001001000001010000010100000101000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2),
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2),
- combout => \myVirtualToplevel|UART0|Equal2~3_combout\);
-
--- Location: LABCELL_X10_Y6_N3
-\myVirtualToplevel|UART0|Equal2~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal2~4_combout\ = (\myVirtualToplevel|UART0|Equal2~2_combout\ & (\myVirtualToplevel|UART0|Equal2~1_combout\ & (\myVirtualToplevel|UART0|Equal2~0_combout\ & \myVirtualToplevel|UART0|Equal2~3_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001000000000000000100000000000000010000000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Equal2~2_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal2~1_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Equal2~0_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Equal2~3_combout\,
- combout => \myVirtualToplevel|UART0|Equal2~4_combout\);
-
--- Location: MLABCELL_X13_Y9_N24
-\myVirtualToplevel|UART0|RX_DATA_READY~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA_READY~0_combout\ = ( \myVirtualToplevel|UART0_CS~combout\ & ( (\myVirtualToplevel|UART1|Equal7~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_READ_ENABLE~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000001100110000000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_READ_ENABLE~q\,
- dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA_READY~0_combout\);
-
--- Location: MLABCELL_X9_Y6_N27
-\myVirtualToplevel|UART0|RX_DATA_READY~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA_READY~1_combout\ = ( \myVirtualToplevel|UART0|RX_DATA_READY~0_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA_READY~q\ & ((!\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ &
--- (!\myVirtualToplevel|UART0|Equal2~4_combout\)) # (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & ((\myVirtualToplevel|UART0|RX_INTR~0_combout\))))) ) ) # ( !\myVirtualToplevel|UART0|RX_DATA_READY~0_combout\ & (
--- ((!\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|Equal2~4_combout\)) # (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & ((\myVirtualToplevel|UART0|RX_INTR~0_combout\)))) #
--- (\myVirtualToplevel|UART0|RX_DATA_READY~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000101111111111100010111111111110001011000000001000101100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Equal2~4_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~0_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA_READY~1_combout\);
-
--- Location: FF_X9_Y6_N28
-\myVirtualToplevel|UART0|RX_DATA_READY\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_DATA_READY~1_combout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_DATA_READY~q\);
-
--- Location: MLABCELL_X9_Y6_N57
-\myVirtualToplevel|UART0|process_3~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|process_3~0_combout\ = ( !\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|RX_DATA_READY~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART0|process_3~0_combout\);
-
--- Location: LABCELL_X10_Y6_N21
-\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\ = ( \myVirtualToplevel|UART0|Equal2~0_combout\ & ( \myVirtualToplevel|UART0|Equal2~1_combout\ & ( (\myVirtualToplevel|UART0|process_3~0_combout\ & (!\myVirtualToplevel|UART0|RX_ENABLE~q\ &
--- ((!\myVirtualToplevel|UART0|Equal2~2_combout\) # (!\myVirtualToplevel|UART0|Equal2~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|UART0|Equal2~0_combout\ & ( \myVirtualToplevel|UART0|Equal2~1_combout\ & ( (\myVirtualToplevel|UART0|process_3~0_combout\ &
--- !\myVirtualToplevel|UART0|RX_ENABLE~q\) ) ) ) # ( \myVirtualToplevel|UART0|Equal2~0_combout\ & ( !\myVirtualToplevel|UART0|Equal2~1_combout\ & ( (\myVirtualToplevel|UART0|process_3~0_combout\ & !\myVirtualToplevel|UART0|RX_ENABLE~q\) ) ) ) # (
--- !\myVirtualToplevel|UART0|Equal2~0_combout\ & ( !\myVirtualToplevel|UART0|Equal2~1_combout\ & ( (\myVirtualToplevel|UART0|process_3~0_combout\ & !\myVirtualToplevel|UART0|RX_ENABLE~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001100000011000000110000001100000011000000100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Equal2~2_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_process_3~0_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Equal2~3_combout\,
- datae => \myVirtualToplevel|UART0|ALT_INV_Equal2~0_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_Equal2~1_combout\,
- combout => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\);
-
--- Location: FF_X12_Y5_N59
-\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~5_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\);
-
--- Location: FF_X10_Y6_N28
-\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~9_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1));
-
--- Location: LABCELL_X12_Y6_N0
-\myVirtualToplevel|UART0|Add2~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add2~22\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0),
- cin => GND,
- cout => \myVirtualToplevel|UART0|Add2~22\);
-
--- Location: LABCELL_X12_Y6_N3
-\myVirtualToplevel|UART0|Add2~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add2~25_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~22\ ))
--- \myVirtualToplevel|UART0|Add2~26\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1),
- cin => \myVirtualToplevel|UART0|Add2~22\,
- sumout => \myVirtualToplevel|UART0|Add2~25_sumout\,
- cout => \myVirtualToplevel|UART0|Add2~26\);
-
--- Location: LABCELL_X12_Y6_N6
-\myVirtualToplevel|UART0|Add2~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add2~29_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~26\ ))
--- \myVirtualToplevel|UART0|Add2~30\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2),
- cin => \myVirtualToplevel|UART0|Add2~26\,
- sumout => \myVirtualToplevel|UART0|Add2~29_sumout\,
- cout => \myVirtualToplevel|UART0|Add2~30\);
-
--- Location: LABCELL_X12_Y6_N24
-\myVirtualToplevel|UART0|Equal3~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal3~1_combout\ = ( !\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|Add2~25_sumout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) &
--- (!\myVirtualToplevel|UART0|Add2~29_sumout\ $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2))))) # (\myVirtualToplevel|UART0|Add2~25_sumout\ & (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|Add2~29_sumout\ $
--- (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2))))) ) ) ) # ( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|Add2~25_sumout\ &
--- (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|Add2~29_sumout\ $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2))))) # (\myVirtualToplevel|UART0|Add2~25_sumout\ & (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) &
--- (!\myVirtualToplevel|UART0|Add2~29_sumout\ $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000100001000010000110000100001000010000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Add2~25_sumout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_Add2~29_sumout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2),
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART0|Equal3~1_combout\);
-
--- Location: LABCELL_X12_Y6_N9
-\myVirtualToplevel|UART0|Add2~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add2~9_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~30\ ))
--- \myVirtualToplevel|UART0|Add2~10\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3),
- cin => \myVirtualToplevel|UART0|Add2~30\,
- sumout => \myVirtualToplevel|UART0|Add2~9_sumout\,
- cout => \myVirtualToplevel|UART0|Add2~10\);
-
--- Location: LABCELL_X12_Y6_N12
-\myVirtualToplevel|UART0|Add2~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add2~13_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~10\ ))
--- \myVirtualToplevel|UART0|Add2~14\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4),
- cin => \myVirtualToplevel|UART0|Add2~10\,
- sumout => \myVirtualToplevel|UART0|Add2~13_sumout\,
- cout => \myVirtualToplevel|UART0|Add2~14\);
-
--- Location: LABCELL_X12_Y6_N15
-\myVirtualToplevel|UART0|Add2~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add2~17_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~14\ ))
--- \myVirtualToplevel|UART0|Add2~18\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5),
- cin => \myVirtualToplevel|UART0|Add2~14\,
- sumout => \myVirtualToplevel|UART0|Add2~17_sumout\,
- cout => \myVirtualToplevel|UART0|Add2~18\);
-
--- Location: LABCELL_X12_Y6_N18
-\myVirtualToplevel|UART0|Add2~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add2~1_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~18\ ))
--- \myVirtualToplevel|UART0|Add2~2\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6),
- cin => \myVirtualToplevel|UART0|Add2~18\,
- sumout => \myVirtualToplevel|UART0|Add2~1_sumout\,
- cout => \myVirtualToplevel|UART0|Add2~2\);
-
--- Location: LABCELL_X12_Y6_N21
-\myVirtualToplevel|UART0|Add2~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add2~5_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add2~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7),
- cin => \myVirtualToplevel|UART0|Add2~2\,
- sumout => \myVirtualToplevel|UART0|Add2~5_sumout\);
-
--- Location: LABCELL_X12_Y6_N39
-\myVirtualToplevel|UART0|Equal3~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal3~0_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & ( \myVirtualToplevel|UART0|Add2~13_sumout\ & ( (\myVirtualToplevel|UART0|Add2~17_sumout\ & (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) &
--- (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) $ (\myVirtualToplevel|UART0|Add2~9_sumout\)))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & ( \myVirtualToplevel|UART0|Add2~13_sumout\ & ( (!\myVirtualToplevel|UART0|Add2~17_sumout\ &
--- (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) $ (\myVirtualToplevel|UART0|Add2~9_sumout\)))) ) ) ) # ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & ( !\myVirtualToplevel|UART0|Add2~13_sumout\ & (
--- (\myVirtualToplevel|UART0|Add2~17_sumout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) $ (\myVirtualToplevel|UART0|Add2~9_sumout\)))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & (
--- !\myVirtualToplevel|UART0|Add2~13_sumout\ & ( (!\myVirtualToplevel|UART0|Add2~17_sumout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) $ (\myVirtualToplevel|UART0|Add2~9_sumout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1001000000000000000010010000000000000000100100000000000000001001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3),
- datab => \myVirtualToplevel|UART0|ALT_INV_Add2~9_sumout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Add2~17_sumout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4),
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5),
- dataf => \myVirtualToplevel|UART0|ALT_INV_Add2~13_sumout\,
- combout => \myVirtualToplevel|UART0|Equal3~0_combout\);
-
--- Location: LABCELL_X12_Y6_N54
-\myVirtualToplevel|UART0|Equal3~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal3~2_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & ( \myVirtualToplevel|UART0|Add2~1_sumout\ & ( (\myVirtualToplevel|UART0|Equal3~1_combout\ & (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) &
--- (\myVirtualToplevel|UART0|Add2~5_sumout\ & \myVirtualToplevel|UART0|Equal3~0_combout\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & ( \myVirtualToplevel|UART0|Add2~1_sumout\ & ( (\myVirtualToplevel|UART0|Equal3~1_combout\ &
--- (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART0|Add2~5_sumout\ & \myVirtualToplevel|UART0|Equal3~0_combout\))) ) ) ) # ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & ( !\myVirtualToplevel|UART0|Add2~1_sumout\ & (
--- (\myVirtualToplevel|UART0|Equal3~1_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & (\myVirtualToplevel|UART0|Add2~5_sumout\ & \myVirtualToplevel|UART0|Equal3~0_combout\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & (
--- !\myVirtualToplevel|UART0|Add2~1_sumout\ & ( (\myVirtualToplevel|UART0|Equal3~1_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART0|Add2~5_sumout\ & \myVirtualToplevel|UART0|Equal3~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000000000000000000010000000000000100000000000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Equal3~1_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6),
- datac => \myVirtualToplevel|UART0|ALT_INV_Add2~5_sumout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Equal3~0_combout\,
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7),
- dataf => \myVirtualToplevel|UART0|ALT_INV_Add2~1_sumout\,
- combout => \myVirtualToplevel|UART0|Equal3~2_combout\);
-
--- Location: LABCELL_X12_Y5_N27
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\ = ( !\myVirtualToplevel|UART0|Equal3~2_combout\ & ( (!\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & (\myVirtualToplevel|UART0|RX_INTR~0_combout\ & !\myVirtualToplevel|UART0|RX_ENABLE~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000000100000001000000010000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_Equal3~2_combout\,
- combout => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\);
-
--- Location: FF_X12_Y5_N26
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~1_combout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0));
-
--- Location: LABCELL_X10_Y6_N9
-\myVirtualToplevel|UART0|RX_FIFO~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO~33_combout\ = (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000100000000000000010000000000000001000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2),
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4),
- combout => \myVirtualToplevel|UART0|RX_FIFO~33_combout\);
-
--- Location: MLABCELL_X9_Y5_N24
-\myVirtualToplevel|UART0|RX_FIFO~31\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO~31_combout\ = ( \myVirtualToplevel|UART0|RX_RESET~q\ & ( !\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|RX_ENABLE~q\ & (\myVirtualToplevel|UART0|RX_CLOCK~q\ &
--- (\myVirtualToplevel|UART0|RX_STATE.stop~q\ & \myVirtualToplevel|UART0|RXD_SYNC~q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000001000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_CLOCK~q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_STATE.stop~q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RXD_SYNC~q\,
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_RESET~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART0|RX_FIFO~31_combout\);
-
--- Location: LABCELL_X12_Y6_N48
-\myVirtualToplevel|UART0|Equal3~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal3~3_combout\ = ( \myVirtualToplevel|UART0|Add2~1_sumout\ & ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) ) ) # ( !\myVirtualToplevel|UART0|Add2~1_sumout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001111001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6),
- dataf => \myVirtualToplevel|UART0|ALT_INV_Add2~1_sumout\,
- combout => \myVirtualToplevel|UART0|Equal3~3_combout\);
-
--- Location: LABCELL_X12_Y6_N30
-\myVirtualToplevel|UART0|RX_FIFO~32\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO~32_combout\ = ( \myVirtualToplevel|UART0|Add2~5_sumout\ & ( \myVirtualToplevel|UART0|Equal3~3_combout\ & ( \myVirtualToplevel|UART0|RX_FIFO~31_combout\ ) ) ) # ( !\myVirtualToplevel|UART0|Add2~5_sumout\ & (
--- \myVirtualToplevel|UART0|Equal3~3_combout\ & ( \myVirtualToplevel|UART0|RX_FIFO~31_combout\ ) ) ) # ( \myVirtualToplevel|UART0|Add2~5_sumout\ & ( !\myVirtualToplevel|UART0|Equal3~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO~31_combout\ &
--- ((!\myVirtualToplevel|UART0|Equal3~0_combout\) # ((!\myVirtualToplevel|UART0|Equal3~1_combout\) # (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7))))) ) ) ) # ( !\myVirtualToplevel|UART0|Add2~5_sumout\ & ( !\myVirtualToplevel|UART0|Equal3~3_combout\ & (
--- (\myVirtualToplevel|UART0|RX_FIFO~31_combout\ & ((!\myVirtualToplevel|UART0|Equal3~0_combout\) # ((!\myVirtualToplevel|UART0|Equal3~1_combout\) # (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010001010101010101010101010001010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~31_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_Equal3~0_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_Equal3~1_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7),
- datae => \myVirtualToplevel|UART0|ALT_INV_Add2~5_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_Equal3~3_combout\,
- combout => \myVirtualToplevel|UART0|RX_FIFO~32_combout\);
-
--- Location: LABCELL_X10_Y6_N24
-\myVirtualToplevel|UART0|RX_FIFO~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO~34_combout\ = ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & ( \myVirtualToplevel|UART0|RX_FIFO~32_combout\ & ( (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(0) & (\myVirtualToplevel|UART0|RX_FIFO~33_combout\ &
--- (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) & !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000100000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(0),
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~33_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1),
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~32_combout\,
- combout => \myVirtualToplevel|UART0|RX_FIFO~34_combout\);
-
--- Location: FF_X10_Y5_N25
-\myVirtualToplevel|UART0|RX_FIFO~24\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_BUFFER\(7),
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO~24_q\);
-
--- Location: LABCELL_X10_Y6_N0
-\myVirtualToplevel|UART0|RX_FIFO~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO~35_combout\ = (\myVirtualToplevel|UART0|RX_FIFO~17_q\) # (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111111111111000011111111111100001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~17_q\,
- combout => \myVirtualToplevel|UART0|RX_FIFO~35_combout\);
-
--- Location: FF_X10_Y6_N2
-\myVirtualToplevel|UART0|RX_FIFO~17\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_FIFO~35_combout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO~17_q\);
-
--- Location: FF_X10_Y6_N41
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(15));
-
--- Location: FF_X10_Y6_N38
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(13));
-
--- Location: FF_X9_Y6_N14
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(11));
-
--- Location: FF_X10_Y6_N35
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~17_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(14));
-
--- Location: FF_X12_Y5_N55
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~29_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(12));
-
--- Location: LABCELL_X10_Y6_N33
-\myVirtualToplevel|UART0|RX_FIFO~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO~26_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(12) & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(11) & (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(13) $
--- (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(14)))) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(12) & ( (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(11) & (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(13) $
--- (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(14)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000001010000101000000101000000001010000001010000101000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(13),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(11),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(14),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(12),
- combout => \myVirtualToplevel|UART0|RX_FIFO~26_combout\);
-
--- Location: FF_X10_Y6_N32
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~21_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(16));
-
--- Location: FF_X10_Y6_N50
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~9_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(4));
-
--- Location: FF_X10_Y6_N8
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~5_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(2));
-
--- Location: FF_X12_Y6_N34
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(1));
-
--- Location: FF_X10_Y6_N44
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(3));
-
--- Location: FF_X12_Y6_N28
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_FIFO~32_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(0));
-
--- Location: LABCELL_X10_Y6_N42
-\myVirtualToplevel|UART0|RX_FIFO~27\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO~27_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(0) & ( (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(4) & (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(3) &
--- (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(2) $ (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(1))))) # (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(4) & (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(3) &
--- (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(2) $ (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(1))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000010010000011000001001000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(4),
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(2),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(1),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(3),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(0),
- combout => \myVirtualToplevel|UART0|RX_FIFO~27_combout\);
-
--- Location: FF_X9_Y6_N58
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(9));
-
--- Location: FF_X10_Y6_N53
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~1_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(10));
-
--- Location: FF_X12_Y5_N14
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~13_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8));
-
--- Location: FF_X12_Y5_N5
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Add3~25_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6));
-
--- Location: FF_X9_Y6_N52
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5));
-
--- Location: FF_X9_Y6_N22
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7));
-
--- Location: LABCELL_X12_Y5_N54
-\myVirtualToplevel|UART0|RX_FIFO~28\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO~28_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5) & ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7) & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8) &
--- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5) & ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7) & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8) &
--- !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6)) ) ) ) # ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5) & ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7) & ( (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8) &
--- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(5) & ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(7) & ( (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(8) &
--- !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(6)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000011000000000011000000110000110000001100000000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(8),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(6),
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(5),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(7),
- combout => \myVirtualToplevel|UART0|RX_FIFO~28_combout\);
-
--- Location: LABCELL_X10_Y6_N51
-\myVirtualToplevel|UART0|RX_FIFO~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO~29_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(10) & ( \myVirtualToplevel|UART0|RX_FIFO~28_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO~27_combout\ & \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(9)) ) )
--- ) # ( !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(10) & ( \myVirtualToplevel|UART0|RX_FIFO~28_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO~27_combout\ & !\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(9)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000110000001100000000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~27_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(9),
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(10),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~28_combout\,
- combout => \myVirtualToplevel|UART0|RX_FIFO~29_combout\);
-
--- Location: LABCELL_X10_Y6_N30
-\myVirtualToplevel|UART0|RX_FIFO~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO~30_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO~29_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO~26_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(15) $ (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(16))))
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001100000000110000110000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(15),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~26_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(16),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~29_combout\,
- combout => \myVirtualToplevel|UART0|RX_FIFO~30_combout\);
-
--- Location: MLABCELL_X9_Y6_N42
-\myVirtualToplevel|UART0|RX_DATA[7]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO~30_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA_READY~q\ & (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_INTR~0_combout\)) ) ) # (
--- !\myVirtualToplevel|UART0|RX_FIFO~30_combout\ & ( (!\myVirtualToplevel|UART0|RX_FIFO~17_q\) # ((!\myVirtualToplevel|UART0|RX_DATA_READY~q\ & (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\ & \myVirtualToplevel|UART0|RX_INTR~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110010111100001111001000000000001000100000000000100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~17_q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~30_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA[7]~2_combout\);
-
--- Location: FF_X12_Y5_N37
-\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add4~9_sumout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[3]~DUPLICATE_q\);
-
--- Location: FF_X10_Y4_N14
-\myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector10~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER[2]~DUPLICATE_q\);
-
--- Location: FF_X10_Y4_N11
-\myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector9~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\);
-
--- Location: FF_X10_Y4_N7
-\myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector8~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER[4]~DUPLICATE_q\);
-
--- Location: FF_X10_Y4_N52
-\myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Selector6~0_combout\,
- ena => \myVirtualToplevel|UART0|RX_BUFFER[1]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_BUFFER[6]~DUPLICATE_q\);
-
--- Location: M10K_X11_Y5_N0
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- logical_ram_name => "zpu_soc:myVirtualToplevel|uart:UART0|altsyncram:RX_FIFO_rtl_0|altsyncram_1jo1:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 8,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 40,
- port_a_first_address => 0,
- port_a_first_bit_number => 0,
- port_a_last_address => 255,
- port_a_logical_ram_depth => 256,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 8,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 40,
- port_b_first_address => 0,
- port_b_first_bit_number => 0,
- port_b_last_address => 255,
- port_b_logical_ram_depth => 256,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|UART0|RX_FIFO~32_combout\,
- portbre => VCC,
- portbaddrstall => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR[0]~0_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);
-
--- Location: MLABCELL_X9_Y6_N45
-\myVirtualToplevel|UART0|RX_DATA[7]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ = ( !\myVirtualToplevel|UART0|RX_FIFO~30_combout\ & ( (!\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\) # ((!\myVirtualToplevel|UART0|RX_INTR~0_combout\) # (\myVirtualToplevel|UART0|RX_DATA_READY~q\)) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111001111111111111100111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~30_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\);
-
--- Location: LABCELL_X10_Y5_N24
-\myVirtualToplevel|UART0|RX_DATA~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA~8_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(7) & ( \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ &
--- ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a6\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO~24_q\)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(7) & (
--- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a6\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ &
--- (\myVirtualToplevel|UART0|RX_FIFO~24_q\)) ) ) ) # ( \myVirtualToplevel|UART0|RX_BUFFER\(7) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) # (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(23)) ) )
--- ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(7) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(23) & !\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010000010111110101111100000011111100110000001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(23),
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~24_q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\,
- datad => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(7),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA~8_combout\);
-
--- Location: MLABCELL_X9_Y5_N42
-\myVirtualToplevel|UART0|RX_DATA[6]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA[6]~9_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~8_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(6)) ) ) # (
--- !\myVirtualToplevel|UART0|RX_DATA~8_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(6) & ((!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111100000000001111110000000011111111110000001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(6),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~8_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA[6]~9_combout\);
-
--- Location: FF_X9_Y5_N43
-\myVirtualToplevel|UART0|RX_DATA[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_DATA[6]~9_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_DATA\(6));
-
--- Location: LABCELL_X12_Y9_N45
-\myVirtualToplevel|IO_DATA_READ~48\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~48_combout\ = ( \myVirtualToplevel|UART0|RX_DATA\(6) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|UART0|RX_ENABLE~q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) # (
--- !\myVirtualToplevel|UART0|RX_DATA\(6) & ( (!\myVirtualToplevel|UART0|RX_ENABLE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000000100000001000000010000011100000111000001110000011100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(6),
- combout => \myVirtualToplevel|IO_DATA_READ~48_combout\);
-
--- Location: LABCELL_X14_Y9_N21
-\myVirtualToplevel|IO_DATA_READ[0]~46\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[0]~46_combout\ = ( !\myVirtualToplevel|TIMER0_CS~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100001111111111110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\,
- combout => \myVirtualToplevel|IO_DATA_READ[0]~46_combout\);
-
--- Location: MLABCELL_X9_Y12_N9
-\myVirtualToplevel|IO_DATA_READ~50\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~50_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_COUNTER\(6) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|UART1|Equal7~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000100000001000000010000000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(6),
- combout => \myVirtualToplevel|IO_DATA_READ~50_combout\);
-
--- Location: LABCELL_X12_Y12_N0
-\myVirtualToplevel|Add19~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~41_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|Add19~42\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(0),
- cin => GND,
- sumout => \myVirtualToplevel|Add19~41_sumout\,
- cout => \myVirtualToplevel|Add19~42\);
-
--- Location: LABCELL_X12_Y12_N36
-\myVirtualToplevel|Equal36~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal36~1_combout\ = ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(2) & ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(4) & ( (!\myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ & !\myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000011000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[1]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(2),
- dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(4),
- combout => \myVirtualToplevel|Equal36~1_combout\);
-
--- Location: LABCELL_X12_Y12_N18
-\myVirtualToplevel|Add19~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~21_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add19~6\ ))
--- \myVirtualToplevel|Add19~22\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add19~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(6),
- cin => \myVirtualToplevel|Add19~6\,
- sumout => \myVirtualToplevel|Add19~21_sumout\,
- cout => \myVirtualToplevel|Add19~22\);
-
--- Location: LABCELL_X12_Y12_N21
-\myVirtualToplevel|Add19~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~25_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add19~22\ ))
--- \myVirtualToplevel|Add19~26\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add19~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(7),
- cin => \myVirtualToplevel|Add19~22\,
- sumout => \myVirtualToplevel|Add19~25_sumout\,
- cout => \myVirtualToplevel|Add19~26\);
-
--- Location: LABCELL_X16_Y13_N54
-\myVirtualToplevel|INTR0_CS~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|INTR0_CS~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- combout => \myVirtualToplevel|INTR0_CS~0_combout\);
-
--- Location: LABCELL_X12_Y12_N48
-\myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\ = ( \myVirtualToplevel|INTR0_CS~0_combout\ & ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (!\myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) ) # ( !\myVirtualToplevel|INTR0_CS~0_combout\ & ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( !\myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\ ) ) )
--- # ( \myVirtualToplevel|INTR0_CS~0_combout\ & ( !\myVirtualToplevel|TIMER0_CS~2_combout\ & ( !\myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\ ) ) ) # ( !\myVirtualToplevel|INTR0_CS~0_combout\ & ( !\myVirtualToplevel|TIMER0_CS~2_combout\ & (
--- !\myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011111111000000001111111100000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\,
- combout => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\);
-
--- Location: FF_X12_Y12_N22
-\myVirtualToplevel|SECOND_DOWN_COUNTER[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~25_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(7));
-
--- Location: LABCELL_X12_Y12_N24
-\myVirtualToplevel|Add19~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~29_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add19~26\ ))
--- \myVirtualToplevel|Add19~30\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add19~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(8),
- cin => \myVirtualToplevel|Add19~26\,
- sumout => \myVirtualToplevel|Add19~29_sumout\,
- cout => \myVirtualToplevel|Add19~30\);
-
--- Location: FF_X12_Y12_N26
-\myVirtualToplevel|SECOND_DOWN_COUNTER[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~29_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(8));
-
--- Location: LABCELL_X12_Y12_N27
-\myVirtualToplevel|Add19~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~9_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add19~30\ ))
--- \myVirtualToplevel|Add19~10\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add19~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(9),
- cin => \myVirtualToplevel|Add19~30\,
- sumout => \myVirtualToplevel|Add19~9_sumout\,
- cout => \myVirtualToplevel|Add19~10\);
-
--- Location: FF_X12_Y12_N29
-\myVirtualToplevel|SECOND_DOWN_COUNTER[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~9_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(9));
-
--- Location: LABCELL_X12_Y12_N30
-\myVirtualToplevel|Add19~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~13_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~10\ ))
--- \myVirtualToplevel|Add19~14\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[10]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add19~10\,
- sumout => \myVirtualToplevel|Add19~13_sumout\,
- cout => \myVirtualToplevel|Add19~14\);
-
--- Location: FF_X12_Y12_N32
-\myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~13_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y12_N33
-\myVirtualToplevel|Add19~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~17_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[11]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add19~14\,
- sumout => \myVirtualToplevel|Add19~17_sumout\);
-
--- Location: FF_X12_Y12_N35
-\myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~17_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y12_N54
-\myVirtualToplevel|Equal36~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal36~0_combout\ = ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(9) & ( !\myVirtualToplevel|SECOND_DOWN_COUNTER\(8) & ( (!\myVirtualToplevel|SECOND_DOWN_COUNTER[11]~DUPLICATE_q\ & (!\myVirtualToplevel|SECOND_DOWN_COUNTER\(7) &
--- (!\myVirtualToplevel|SECOND_DOWN_COUNTER\(0) & !\myVirtualToplevel|SECOND_DOWN_COUNTER[10]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[11]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(7),
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(0),
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[10]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(9),
- dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(8),
- combout => \myVirtualToplevel|Equal36~0_combout\);
-
--- Location: MLABCELL_X18_Y40_N0
-\myVirtualToplevel|Add18~93\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~93_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|Add18~94\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(0),
- cin => GND,
- sumout => \myVirtualToplevel|Add18~93_sumout\,
- cout => \myVirtualToplevel|Add18~94\);
-
--- Location: FF_X18_Y40_N2
-\myVirtualToplevel|SECOND_DOWN_TICK[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~93_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(0));
-
--- Location: MLABCELL_X18_Y40_N3
-\myVirtualToplevel|Add18~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~89_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add18~94\ ))
--- \myVirtualToplevel|Add18~90\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add18~94\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(1),
- cin => \myVirtualToplevel|Add18~94\,
- sumout => \myVirtualToplevel|Add18~89_sumout\,
- cout => \myVirtualToplevel|Add18~90\);
-
--- Location: FF_X18_Y40_N5
-\myVirtualToplevel|SECOND_DOWN_TICK[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~89_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(1));
-
--- Location: MLABCELL_X18_Y40_N6
-\myVirtualToplevel|Add18~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~85_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add18~90\ ))
--- \myVirtualToplevel|Add18~86\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add18~90\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(2),
- cin => \myVirtualToplevel|Add18~90\,
- sumout => \myVirtualToplevel|Add18~85_sumout\,
- cout => \myVirtualToplevel|Add18~86\);
-
--- Location: FF_X18_Y40_N8
-\myVirtualToplevel|SECOND_DOWN_TICK[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~85_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(2));
-
--- Location: MLABCELL_X18_Y40_N9
-\myVirtualToplevel|Add18~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~81_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add18~86\ ))
--- \myVirtualToplevel|Add18~82\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add18~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(3),
- cin => \myVirtualToplevel|Add18~86\,
- sumout => \myVirtualToplevel|Add18~81_sumout\,
- cout => \myVirtualToplevel|Add18~82\);
-
--- Location: FF_X18_Y40_N11
-\myVirtualToplevel|SECOND_DOWN_TICK[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~81_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(3));
-
--- Location: MLABCELL_X18_Y40_N12
-\myVirtualToplevel|Add18~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~77_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add18~82\ ))
--- \myVirtualToplevel|Add18~78\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add18~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(4),
- cin => \myVirtualToplevel|Add18~82\,
- sumout => \myVirtualToplevel|Add18~77_sumout\,
- cout => \myVirtualToplevel|Add18~78\);
-
--- Location: FF_X18_Y40_N14
-\myVirtualToplevel|SECOND_DOWN_TICK[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~77_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(4));
-
--- Location: MLABCELL_X18_Y40_N15
-\myVirtualToplevel|Add18~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~73_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add18~78\ ))
--- \myVirtualToplevel|Add18~74\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add18~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(5),
- cin => \myVirtualToplevel|Add18~78\,
- sumout => \myVirtualToplevel|Add18~73_sumout\,
- cout => \myVirtualToplevel|Add18~74\);
-
--- Location: FF_X18_Y40_N17
-\myVirtualToplevel|SECOND_DOWN_TICK[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~73_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(5));
-
--- Location: MLABCELL_X18_Y40_N18
-\myVirtualToplevel|Add18~109\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~109_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add18~74\ ))
--- \myVirtualToplevel|Add18~110\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add18~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(6),
- cin => \myVirtualToplevel|Add18~74\,
- sumout => \myVirtualToplevel|Add18~109_sumout\,
- cout => \myVirtualToplevel|Add18~110\);
-
--- Location: FF_X18_Y40_N20
-\myVirtualToplevel|SECOND_DOWN_TICK[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~109_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(6));
-
--- Location: MLABCELL_X18_Y40_N21
-\myVirtualToplevel|Add18~105\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~105_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add18~110\ ))
--- \myVirtualToplevel|Add18~106\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add18~110\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(7),
- cin => \myVirtualToplevel|Add18~110\,
- sumout => \myVirtualToplevel|Add18~105_sumout\,
- cout => \myVirtualToplevel|Add18~106\);
-
--- Location: FF_X18_Y40_N23
-\myVirtualToplevel|SECOND_DOWN_TICK[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~105_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(7));
-
--- Location: MLABCELL_X18_Y40_N24
-\myVirtualToplevel|Add18~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~69_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add18~106\ ))
--- \myVirtualToplevel|Add18~70\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add18~106\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(8),
- cin => \myVirtualToplevel|Add18~106\,
- sumout => \myVirtualToplevel|Add18~69_sumout\,
- cout => \myVirtualToplevel|Add18~70\);
-
--- Location: FF_X18_Y40_N26
-\myVirtualToplevel|SECOND_DOWN_TICK[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~69_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(8));
-
--- Location: MLABCELL_X18_Y40_N27
-\myVirtualToplevel|Add18~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~65_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add18~70\ ))
--- \myVirtualToplevel|Add18~66\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add18~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(9),
- cin => \myVirtualToplevel|Add18~70\,
- sumout => \myVirtualToplevel|Add18~65_sumout\,
- cout => \myVirtualToplevel|Add18~66\);
-
--- Location: FF_X18_Y40_N29
-\myVirtualToplevel|SECOND_DOWN_TICK[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~65_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(9));
-
--- Location: MLABCELL_X18_Y39_N0
-\myVirtualToplevel|Add18~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~13_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add18~66\ ))
--- \myVirtualToplevel|Add18~14\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add18~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(10),
- cin => \myVirtualToplevel|Add18~66\,
- sumout => \myVirtualToplevel|Add18~13_sumout\,
- cout => \myVirtualToplevel|Add18~14\);
-
--- Location: FF_X18_Y39_N1
-\myVirtualToplevel|SECOND_DOWN_TICK[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~13_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(10));
-
--- Location: MLABCELL_X18_Y39_N3
-\myVirtualToplevel|Add18~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~9_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add18~14\ ))
--- \myVirtualToplevel|Add18~10\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add18~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(11),
- cin => \myVirtualToplevel|Add18~14\,
- sumout => \myVirtualToplevel|Add18~9_sumout\,
- cout => \myVirtualToplevel|Add18~10\);
-
--- Location: FF_X18_Y39_N4
-\myVirtualToplevel|SECOND_DOWN_TICK[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~9_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(11));
-
--- Location: MLABCELL_X18_Y39_N6
-\myVirtualToplevel|Add18~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~45_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~10\ ))
--- \myVirtualToplevel|Add18~46\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add18~10\,
- sumout => \myVirtualToplevel|Add18~45_sumout\,
- cout => \myVirtualToplevel|Add18~46\);
-
--- Location: FF_X18_Y39_N8
-\myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~45_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK[12]~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y39_N9
-\myVirtualToplevel|Add18~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~41_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(13) ) + ( GND ) + ( \myVirtualToplevel|Add18~46\ ))
--- \myVirtualToplevel|Add18~42\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(13) ) + ( GND ) + ( \myVirtualToplevel|Add18~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(13),
- cin => \myVirtualToplevel|Add18~46\,
- sumout => \myVirtualToplevel|Add18~41_sumout\,
- cout => \myVirtualToplevel|Add18~42\);
-
--- Location: FF_X18_Y39_N11
-\myVirtualToplevel|SECOND_DOWN_TICK[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~41_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(13));
-
--- Location: MLABCELL_X18_Y39_N12
-\myVirtualToplevel|Add18~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~37_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(14) ) + ( GND ) + ( \myVirtualToplevel|Add18~42\ ))
--- \myVirtualToplevel|Add18~38\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(14) ) + ( GND ) + ( \myVirtualToplevel|Add18~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(14),
- cin => \myVirtualToplevel|Add18~42\,
- sumout => \myVirtualToplevel|Add18~37_sumout\,
- cout => \myVirtualToplevel|Add18~38\);
-
--- Location: FF_X18_Y39_N14
-\myVirtualToplevel|SECOND_DOWN_TICK[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~37_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(14));
-
--- Location: MLABCELL_X18_Y39_N15
-\myVirtualToplevel|Add18~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~33_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~38\ ))
--- \myVirtualToplevel|Add18~34\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[15]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add18~38\,
- sumout => \myVirtualToplevel|Add18~33_sumout\,
- cout => \myVirtualToplevel|Add18~34\);
-
--- Location: FF_X18_Y39_N17
-\myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~33_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK[15]~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y39_N18
-\myVirtualToplevel|Add18~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~29_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~34\ ))
--- \myVirtualToplevel|Add18~30\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add18~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[16]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add18~34\,
- sumout => \myVirtualToplevel|Add18~29_sumout\,
- cout => \myVirtualToplevel|Add18~30\);
-
--- Location: FF_X18_Y39_N20
-\myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~29_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK[16]~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y39_N21
-\myVirtualToplevel|Add18~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~5_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(17) ) + ( GND ) + ( \myVirtualToplevel|Add18~30\ ))
--- \myVirtualToplevel|Add18~6\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(17) ) + ( GND ) + ( \myVirtualToplevel|Add18~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(17),
- cin => \myVirtualToplevel|Add18~30\,
- sumout => \myVirtualToplevel|Add18~5_sumout\,
- cout => \myVirtualToplevel|Add18~6\);
-
--- Location: FF_X18_Y39_N22
-\myVirtualToplevel|SECOND_DOWN_TICK[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~5_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(17));
-
--- Location: MLABCELL_X18_Y39_N24
-\myVirtualToplevel|Add18~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~25_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(18) ) + ( GND ) + ( \myVirtualToplevel|Add18~6\ ))
--- \myVirtualToplevel|Add18~26\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(18) ) + ( GND ) + ( \myVirtualToplevel|Add18~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(18),
- cin => \myVirtualToplevel|Add18~6\,
- sumout => \myVirtualToplevel|Add18~25_sumout\,
- cout => \myVirtualToplevel|Add18~26\);
-
--- Location: FF_X18_Y39_N26
-\myVirtualToplevel|SECOND_DOWN_TICK[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~25_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(18));
-
--- Location: MLABCELL_X18_Y39_N27
-\myVirtualToplevel|Add18~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~1_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(19) ) + ( GND ) + ( \myVirtualToplevel|Add18~26\ ))
--- \myVirtualToplevel|Add18~2\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(19) ) + ( GND ) + ( \myVirtualToplevel|Add18~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(19),
- cin => \myVirtualToplevel|Add18~26\,
- sumout => \myVirtualToplevel|Add18~1_sumout\,
- cout => \myVirtualToplevel|Add18~2\);
-
--- Location: FF_X18_Y39_N28
-\myVirtualToplevel|SECOND_DOWN_TICK[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~1_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(19));
-
--- Location: MLABCELL_X18_Y39_N30
-\myVirtualToplevel|Add18~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~21_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(20) ) + ( GND ) + ( \myVirtualToplevel|Add18~2\ ))
--- \myVirtualToplevel|Add18~22\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(20) ) + ( GND ) + ( \myVirtualToplevel|Add18~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(20),
- cin => \myVirtualToplevel|Add18~2\,
- sumout => \myVirtualToplevel|Add18~21_sumout\,
- cout => \myVirtualToplevel|Add18~22\);
-
--- Location: FF_X18_Y39_N32
-\myVirtualToplevel|SECOND_DOWN_TICK[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~21_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(20));
-
--- Location: MLABCELL_X18_Y39_N33
-\myVirtualToplevel|Add18~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~17_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(21) ) + ( GND ) + ( \myVirtualToplevel|Add18~22\ ))
--- \myVirtualToplevel|Add18~18\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(21) ) + ( GND ) + ( \myVirtualToplevel|Add18~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(21),
- cin => \myVirtualToplevel|Add18~22\,
- sumout => \myVirtualToplevel|Add18~17_sumout\,
- cout => \myVirtualToplevel|Add18~18\);
-
--- Location: FF_X18_Y39_N35
-\myVirtualToplevel|SECOND_DOWN_TICK[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~17_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(21));
-
--- Location: MLABCELL_X18_Y39_N36
-\myVirtualToplevel|Add18~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~61_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(22) ) + ( GND ) + ( \myVirtualToplevel|Add18~18\ ))
--- \myVirtualToplevel|Add18~62\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(22) ) + ( GND ) + ( \myVirtualToplevel|Add18~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(22),
- cin => \myVirtualToplevel|Add18~18\,
- sumout => \myVirtualToplevel|Add18~61_sumout\,
- cout => \myVirtualToplevel|Add18~62\);
-
--- Location: FF_X18_Y39_N37
-\myVirtualToplevel|SECOND_DOWN_TICK[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~61_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(22));
-
--- Location: MLABCELL_X18_Y39_N39
-\myVirtualToplevel|Add18~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~57_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(23) ) + ( GND ) + ( \myVirtualToplevel|Add18~62\ ))
--- \myVirtualToplevel|Add18~58\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(23) ) + ( GND ) + ( \myVirtualToplevel|Add18~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(23),
- cin => \myVirtualToplevel|Add18~62\,
- sumout => \myVirtualToplevel|Add18~57_sumout\,
- cout => \myVirtualToplevel|Add18~58\);
-
--- Location: FF_X18_Y39_N41
-\myVirtualToplevel|SECOND_DOWN_TICK[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~57_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(23));
-
--- Location: MLABCELL_X18_Y39_N42
-\myVirtualToplevel|Add18~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~53_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(24) ) + ( GND ) + ( \myVirtualToplevel|Add18~58\ ))
--- \myVirtualToplevel|Add18~54\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(24) ) + ( GND ) + ( \myVirtualToplevel|Add18~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(24),
- cin => \myVirtualToplevel|Add18~58\,
- sumout => \myVirtualToplevel|Add18~53_sumout\,
- cout => \myVirtualToplevel|Add18~54\);
-
--- Location: FF_X18_Y39_N44
-\myVirtualToplevel|SECOND_DOWN_TICK[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~53_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(24));
-
--- Location: MLABCELL_X18_Y39_N45
-\myVirtualToplevel|Add18~101\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~101_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(25) ) + ( GND ) + ( \myVirtualToplevel|Add18~54\ ))
--- \myVirtualToplevel|Add18~102\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(25) ) + ( GND ) + ( \myVirtualToplevel|Add18~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(25),
- cin => \myVirtualToplevel|Add18~54\,
- sumout => \myVirtualToplevel|Add18~101_sumout\,
- cout => \myVirtualToplevel|Add18~102\);
-
--- Location: FF_X18_Y39_N46
-\myVirtualToplevel|SECOND_DOWN_TICK[25]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~101_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(25));
-
--- Location: MLABCELL_X18_Y39_N48
-\myVirtualToplevel|Add18~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~49_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(26) ) + ( GND ) + ( \myVirtualToplevel|Add18~102\ ))
--- \myVirtualToplevel|Add18~50\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_TICK\(26) ) + ( GND ) + ( \myVirtualToplevel|Add18~102\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(26),
- cin => \myVirtualToplevel|Add18~102\,
- sumout => \myVirtualToplevel|Add18~49_sumout\,
- cout => \myVirtualToplevel|Add18~50\);
-
--- Location: FF_X18_Y39_N49
-\myVirtualToplevel|SECOND_DOWN_TICK[26]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~49_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(26));
-
--- Location: MLABCELL_X18_Y39_N51
-\myVirtualToplevel|Add18~97\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add18~97_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_TICK\(27) ) + ( GND ) + ( \myVirtualToplevel|Add18~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(27),
- cin => \myVirtualToplevel|Add18~50\,
- sumout => \myVirtualToplevel|Add18~97_sumout\);
-
--- Location: FF_X18_Y39_N53
-\myVirtualToplevel|SECOND_DOWN_TICK[27]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~97_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(27));
-
--- Location: MLABCELL_X18_Y40_N30
-\myVirtualToplevel|Equal35~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal35~6_combout\ = ( !\myVirtualToplevel|SECOND_DOWN_TICK\(25) & ( (!\myVirtualToplevel|SECOND_DOWN_TICK\(27) & (\myVirtualToplevel|SECOND_DOWN_TICK\(6) & \myVirtualToplevel|SECOND_DOWN_TICK\(7))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001100000000000000110000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(27),
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(6),
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(7),
- dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(25),
- combout => \myVirtualToplevel|Equal35~6_combout\);
-
--- Location: FF_X18_Y39_N7
-\myVirtualToplevel|SECOND_DOWN_TICK[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~45_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(12));
-
--- Location: FF_X18_Y39_N16
-\myVirtualToplevel|SECOND_DOWN_TICK[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~33_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(15));
-
--- Location: MLABCELL_X18_Y39_N54
-\myVirtualToplevel|Equal35~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal35~1_combout\ = ( \myVirtualToplevel|SECOND_DOWN_TICK\(13) & ( (\myVirtualToplevel|SECOND_DOWN_TICK\(14) & (!\myVirtualToplevel|SECOND_DOWN_TICK\(12) & \myVirtualToplevel|SECOND_DOWN_TICK\(15))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000001100000000000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(14),
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(12),
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(15),
- dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(13),
- combout => \myVirtualToplevel|Equal35~1_combout\);
-
--- Location: FF_X18_Y39_N19
-\myVirtualToplevel|SECOND_DOWN_TICK[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~29_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK\(16));
-
--- Location: MLABCELL_X18_Y39_N57
-\myVirtualToplevel|Equal35~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal35~0_combout\ = ( \myVirtualToplevel|SECOND_DOWN_TICK\(21) & ( (\myVirtualToplevel|SECOND_DOWN_TICK\(18) & (\myVirtualToplevel|SECOND_DOWN_TICK\(20) & \myVirtualToplevel|SECOND_DOWN_TICK\(16))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(18),
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(20),
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(16),
- dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(21),
- combout => \myVirtualToplevel|Equal35~0_combout\);
-
--- Location: LABCELL_X17_Y39_N27
-\myVirtualToplevel|Equal35~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal35~2_combout\ = ( \myVirtualToplevel|Equal35~0_combout\ & ( !\myVirtualToplevel|SECOND_DOWN_TICK\(10) & ( (!\myVirtualToplevel|SECOND_DOWN_TICK\(19) & (\myVirtualToplevel|Equal35~1_combout\ &
--- (!\myVirtualToplevel|SECOND_DOWN_TICK\(17) & !\myVirtualToplevel|SECOND_DOWN_TICK\(11)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(19),
- datab => \myVirtualToplevel|ALT_INV_Equal35~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(17),
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(11),
- datae => \myVirtualToplevel|ALT_INV_Equal35~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(10),
- combout => \myVirtualToplevel|Equal35~2_combout\);
-
--- Location: MLABCELL_X18_Y40_N39
-\myVirtualToplevel|Equal35~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal35~4_combout\ = ( \myVirtualToplevel|SECOND_DOWN_TICK\(5) & ( (!\myVirtualToplevel|SECOND_DOWN_TICK\(8) & (\myVirtualToplevel|SECOND_DOWN_TICK\(4) & !\myVirtualToplevel|SECOND_DOWN_TICK\(9))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001010000000000000101000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(8),
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(4),
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(9),
- dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(5),
- combout => \myVirtualToplevel|Equal35~4_combout\);
-
--- Location: MLABCELL_X18_Y40_N36
-\myVirtualToplevel|Equal35~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal35~5_combout\ = ( \myVirtualToplevel|SECOND_DOWN_TICK\(2) & ( (\myVirtualToplevel|SECOND_DOWN_TICK\(3) & (\myVirtualToplevel|SECOND_DOWN_TICK\(0) & \myVirtualToplevel|SECOND_DOWN_TICK\(1))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(3),
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(0),
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(1),
- dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(2),
- combout => \myVirtualToplevel|Equal35~5_combout\);
-
--- Location: FF_X18_Y39_N40
-\myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add18~57_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal35~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y40_N33
-\myVirtualToplevel|Equal35~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal35~3_combout\ = ( \myVirtualToplevel|SECOND_DOWN_TICK\(24) & ( (\myVirtualToplevel|SECOND_DOWN_TICK\(22) & (\myVirtualToplevel|SECOND_DOWN_TICK[23]~DUPLICATE_q\ & \myVirtualToplevel|SECOND_DOWN_TICK\(26))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(22),
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK[23]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(26),
- dataf => \myVirtualToplevel|ALT_INV_SECOND_DOWN_TICK\(24),
- combout => \myVirtualToplevel|Equal35~3_combout\);
-
--- Location: MLABCELL_X18_Y40_N54
-\myVirtualToplevel|Equal35~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal35~7_combout\ = ( \myVirtualToplevel|Equal35~5_combout\ & ( \myVirtualToplevel|Equal35~3_combout\ & ( (\myVirtualToplevel|Equal35~6_combout\ & (\myVirtualToplevel|Equal35~2_combout\ & \myVirtualToplevel|Equal35~4_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_Equal35~6_combout\,
- datac => \myVirtualToplevel|ALT_INV_Equal35~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_Equal35~4_combout\,
- datae => \myVirtualToplevel|ALT_INV_Equal35~5_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal35~3_combout\,
- combout => \myVirtualToplevel|Equal35~7_combout\);
-
--- Location: LABCELL_X12_Y12_N42
-\myVirtualToplevel|SECOND_DOWN_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\ = ( \myVirtualToplevel|Equal36~0_combout\ & ( \myVirtualToplevel|Equal35~7_combout\ & ( (!\myVirtualToplevel|SECOND_DOWN_COUNTER\(6) & (!\myVirtualToplevel|SECOND_DOWN_COUNTER\(5) &
--- \myVirtualToplevel|Equal36~1_combout\)) ) ) ) # ( \myVirtualToplevel|Equal36~0_combout\ & ( !\myVirtualToplevel|Equal35~7_combout\ ) ) # ( !\myVirtualToplevel|Equal36~0_combout\ & ( !\myVirtualToplevel|Equal35~7_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000100000001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(6),
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(5),
- datac => \myVirtualToplevel|ALT_INV_Equal36~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_Equal36~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal35~7_combout\,
- combout => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\);
-
--- Location: FF_X12_Y12_N2
-\myVirtualToplevel|SECOND_DOWN_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~41_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(0));
-
--- Location: LABCELL_X12_Y12_N3
-\myVirtualToplevel|Add19~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~45_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~42\ ))
--- \myVirtualToplevel|Add19~46\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[1]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add19~42\,
- sumout => \myVirtualToplevel|Add19~45_sumout\,
- cout => \myVirtualToplevel|Add19~46\);
-
--- Location: FF_X12_Y12_N5
-\myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~45_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER[1]~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y12_N6
-\myVirtualToplevel|Add19~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~37_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add19~46\ ))
--- \myVirtualToplevel|Add19~38\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|Add19~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(2),
- cin => \myVirtualToplevel|Add19~46\,
- sumout => \myVirtualToplevel|Add19~37_sumout\,
- cout => \myVirtualToplevel|Add19~38\);
-
--- Location: FF_X12_Y12_N7
-\myVirtualToplevel|SECOND_DOWN_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~37_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(2));
-
--- Location: LABCELL_X12_Y12_N9
-\myVirtualToplevel|Add19~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~33_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~38\ ))
--- \myVirtualToplevel|Add19~34\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add19~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add19~38\,
- sumout => \myVirtualToplevel|Add19~33_sumout\,
- cout => \myVirtualToplevel|Add19~34\);
-
--- Location: FF_X12_Y12_N11
-\myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~33_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER[3]~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y12_N12
-\myVirtualToplevel|Add19~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~1_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add19~34\ ))
--- \myVirtualToplevel|Add19~2\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add19~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(4),
- cin => \myVirtualToplevel|Add19~34\,
- sumout => \myVirtualToplevel|Add19~1_sumout\,
- cout => \myVirtualToplevel|Add19~2\);
-
--- Location: FF_X12_Y12_N13
-\myVirtualToplevel|SECOND_DOWN_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~1_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(4));
-
--- Location: LABCELL_X12_Y12_N15
-\myVirtualToplevel|Add19~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add19~5_sumout\ = SUM(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add19~2\ ))
--- \myVirtualToplevel|Add19~6\ = CARRY(( \myVirtualToplevel|SECOND_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add19~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(5),
- cin => \myVirtualToplevel|Add19~2\,
- sumout => \myVirtualToplevel|Add19~5_sumout\,
- cout => \myVirtualToplevel|Add19~6\);
-
--- Location: FF_X12_Y12_N17
-\myVirtualToplevel|SECOND_DOWN_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~5_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(5));
-
--- Location: FF_X12_Y12_N20
-\myVirtualToplevel|SECOND_DOWN_COUNTER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~21_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER\(6));
-
--- Location: MLABCELL_X18_Y10_N0
-\myVirtualToplevel|Add16~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~69_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|Add16~70\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(0),
- cin => GND,
- sumout => \myVirtualToplevel|Add16~69_sumout\,
- cout => \myVirtualToplevel|Add16~70\);
-
--- Location: FF_X18_Y10_N1
-\myVirtualToplevel|MILLISEC_UP_TICK[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~69_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(0));
-
--- Location: FF_X18_Y10_N11
-\myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~57_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y10_N3
-\myVirtualToplevel|Add16~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~65_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~70\ ))
--- \myVirtualToplevel|Add16~66\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[1]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add16~70\,
- sumout => \myVirtualToplevel|Add16~65_sumout\,
- cout => \myVirtualToplevel|Add16~66\);
-
--- Location: FF_X18_Y10_N5
-\myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~65_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK[1]~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y10_N6
-\myVirtualToplevel|Add16~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~61_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add16~66\ ))
--- \myVirtualToplevel|Add16~62\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add16~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(2),
- cin => \myVirtualToplevel|Add16~66\,
- sumout => \myVirtualToplevel|Add16~61_sumout\,
- cout => \myVirtualToplevel|Add16~62\);
-
--- Location: FF_X18_Y10_N7
-\myVirtualToplevel|MILLISEC_UP_TICK[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~61_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(2));
-
--- Location: MLABCELL_X18_Y10_N9
-\myVirtualToplevel|Add16~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~57_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~62\ ))
--- \myVirtualToplevel|Add16~58\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add16~62\,
- sumout => \myVirtualToplevel|Add16~57_sumout\,
- cout => \myVirtualToplevel|Add16~58\);
-
--- Location: FF_X18_Y10_N10
-\myVirtualToplevel|MILLISEC_UP_TICK[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~57_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(3));
-
--- Location: FF_X18_Y10_N4
-\myVirtualToplevel|MILLISEC_UP_TICK[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~65_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(1));
-
--- Location: LABCELL_X19_Y10_N33
-\myVirtualToplevel|Equal34~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal34~3_combout\ = ( \myVirtualToplevel|MILLISEC_UP_TICK\(1) & ( (\myVirtualToplevel|MILLISEC_UP_TICK\(0) & (\myVirtualToplevel|MILLISEC_UP_TICK\(3) & \myVirtualToplevel|MILLISEC_UP_TICK\(2))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(0),
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(3),
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(2),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(1),
- combout => \myVirtualToplevel|Equal34~3_combout\);
-
--- Location: MLABCELL_X18_Y10_N12
-\myVirtualToplevel|Add16~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~5_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add16~58\ ))
--- \myVirtualToplevel|Add16~6\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add16~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(4),
- cin => \myVirtualToplevel|Add16~58\,
- sumout => \myVirtualToplevel|Add16~5_sumout\,
- cout => \myVirtualToplevel|Add16~6\);
-
--- Location: FF_X18_Y10_N13
-\myVirtualToplevel|MILLISEC_UP_TICK[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~5_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(4));
-
--- Location: MLABCELL_X18_Y10_N15
-\myVirtualToplevel|Add16~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~1_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~6\ ))
--- \myVirtualToplevel|Add16~2\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add16~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK[5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add16~6\,
- sumout => \myVirtualToplevel|Add16~1_sumout\,
- cout => \myVirtualToplevel|Add16~2\);
-
--- Location: FF_X18_Y10_N17
-\myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~1_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK[5]~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y10_N18
-\myVirtualToplevel|Add16~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~21_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add16~2\ ))
--- \myVirtualToplevel|Add16~22\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add16~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(6),
- cin => \myVirtualToplevel|Add16~2\,
- sumout => \myVirtualToplevel|Add16~21_sumout\,
- cout => \myVirtualToplevel|Add16~22\);
-
--- Location: FF_X18_Y10_N19
-\myVirtualToplevel|MILLISEC_UP_TICK[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~21_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(6));
-
--- Location: MLABCELL_X18_Y10_N21
-\myVirtualToplevel|Add16~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~53_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add16~22\ ))
--- \myVirtualToplevel|Add16~54\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add16~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(7),
- cin => \myVirtualToplevel|Add16~22\,
- sumout => \myVirtualToplevel|Add16~53_sumout\,
- cout => \myVirtualToplevel|Add16~54\);
-
--- Location: FF_X18_Y10_N23
-\myVirtualToplevel|MILLISEC_UP_TICK[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~53_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(7));
-
--- Location: MLABCELL_X18_Y10_N24
-\myVirtualToplevel|Add16~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~17_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add16~54\ ))
--- \myVirtualToplevel|Add16~18\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add16~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(8),
- cin => \myVirtualToplevel|Add16~54\,
- sumout => \myVirtualToplevel|Add16~17_sumout\,
- cout => \myVirtualToplevel|Add16~18\);
-
--- Location: FF_X18_Y10_N25
-\myVirtualToplevel|MILLISEC_UP_TICK[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~17_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(8));
-
--- Location: MLABCELL_X18_Y10_N27
-\myVirtualToplevel|Add16~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~49_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add16~18\ ))
--- \myVirtualToplevel|Add16~50\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add16~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(9),
- cin => \myVirtualToplevel|Add16~18\,
- sumout => \myVirtualToplevel|Add16~49_sumout\,
- cout => \myVirtualToplevel|Add16~50\);
-
--- Location: FF_X18_Y10_N29
-\myVirtualToplevel|MILLISEC_UP_TICK[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~49_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(9));
-
--- Location: MLABCELL_X18_Y10_N30
-\myVirtualToplevel|Add16~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~45_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add16~50\ ))
--- \myVirtualToplevel|Add16~46\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add16~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(10),
- cin => \myVirtualToplevel|Add16~50\,
- sumout => \myVirtualToplevel|Add16~45_sumout\,
- cout => \myVirtualToplevel|Add16~46\);
-
--- Location: FF_X18_Y10_N32
-\myVirtualToplevel|MILLISEC_UP_TICK[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~45_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(10));
-
--- Location: MLABCELL_X18_Y10_N33
-\myVirtualToplevel|Add16~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~41_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add16~46\ ))
--- \myVirtualToplevel|Add16~42\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add16~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(11),
- cin => \myVirtualToplevel|Add16~46\,
- sumout => \myVirtualToplevel|Add16~41_sumout\,
- cout => \myVirtualToplevel|Add16~42\);
-
--- Location: FF_X18_Y10_N35
-\myVirtualToplevel|MILLISEC_UP_TICK[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~41_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(11));
-
--- Location: MLABCELL_X18_Y10_N36
-\myVirtualToplevel|Add16~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~37_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(12) ) + ( GND ) + ( \myVirtualToplevel|Add16~42\ ))
--- \myVirtualToplevel|Add16~38\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(12) ) + ( GND ) + ( \myVirtualToplevel|Add16~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(12),
- cin => \myVirtualToplevel|Add16~42\,
- sumout => \myVirtualToplevel|Add16~37_sumout\,
- cout => \myVirtualToplevel|Add16~38\);
-
--- Location: FF_X18_Y10_N38
-\myVirtualToplevel|MILLISEC_UP_TICK[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~37_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(12));
-
--- Location: MLABCELL_X18_Y10_N39
-\myVirtualToplevel|Add16~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~33_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(13) ) + ( GND ) + ( \myVirtualToplevel|Add16~38\ ))
--- \myVirtualToplevel|Add16~34\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(13) ) + ( GND ) + ( \myVirtualToplevel|Add16~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(13),
- cin => \myVirtualToplevel|Add16~38\,
- sumout => \myVirtualToplevel|Add16~33_sumout\,
- cout => \myVirtualToplevel|Add16~34\);
-
--- Location: FF_X18_Y10_N41
-\myVirtualToplevel|MILLISEC_UP_TICK[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~33_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(13));
-
--- Location: MLABCELL_X18_Y10_N42
-\myVirtualToplevel|Add16~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~29_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(14) ) + ( GND ) + ( \myVirtualToplevel|Add16~34\ ))
--- \myVirtualToplevel|Add16~30\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(14) ) + ( GND ) + ( \myVirtualToplevel|Add16~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(14),
- cin => \myVirtualToplevel|Add16~34\,
- sumout => \myVirtualToplevel|Add16~29_sumout\,
- cout => \myVirtualToplevel|Add16~30\);
-
--- Location: FF_X18_Y10_N44
-\myVirtualToplevel|MILLISEC_UP_TICK[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~29_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(14));
-
--- Location: MLABCELL_X18_Y10_N45
-\myVirtualToplevel|Add16~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~13_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(15) ) + ( GND ) + ( \myVirtualToplevel|Add16~30\ ))
--- \myVirtualToplevel|Add16~14\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(15) ) + ( GND ) + ( \myVirtualToplevel|Add16~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(15),
- cin => \myVirtualToplevel|Add16~30\,
- sumout => \myVirtualToplevel|Add16~13_sumout\,
- cout => \myVirtualToplevel|Add16~14\);
-
--- Location: FF_X18_Y10_N46
-\myVirtualToplevel|MILLISEC_UP_TICK[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~13_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(15));
-
--- Location: MLABCELL_X18_Y10_N48
-\myVirtualToplevel|Add16~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~9_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(16) ) + ( GND ) + ( \myVirtualToplevel|Add16~14\ ))
--- \myVirtualToplevel|Add16~10\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_TICK\(16) ) + ( GND ) + ( \myVirtualToplevel|Add16~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(16),
- cin => \myVirtualToplevel|Add16~14\,
- sumout => \myVirtualToplevel|Add16~9_sumout\,
- cout => \myVirtualToplevel|Add16~10\);
-
--- Location: FF_X18_Y10_N49
-\myVirtualToplevel|MILLISEC_UP_TICK[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~9_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(16));
-
--- Location: MLABCELL_X18_Y10_N51
-\myVirtualToplevel|Add16~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add16~25_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_TICK\(17) ) + ( GND ) + ( \myVirtualToplevel|Add16~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(17),
- cin => \myVirtualToplevel|Add16~10\,
- sumout => \myVirtualToplevel|Add16~25_sumout\);
-
--- Location: FF_X18_Y10_N53
-\myVirtualToplevel|MILLISEC_UP_TICK[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~25_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(17));
-
--- Location: MLABCELL_X18_Y10_N54
-\myVirtualToplevel|Equal34~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal34~0_combout\ = ( !\myVirtualToplevel|MILLISEC_UP_TICK\(13) & ( (!\myVirtualToplevel|MILLISEC_UP_TICK\(14) & (!\myVirtualToplevel|MILLISEC_UP_TICK\(17) & !\myVirtualToplevel|MILLISEC_UP_TICK\(12))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(14),
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(17),
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(12),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(13),
- combout => \myVirtualToplevel|Equal34~0_combout\);
-
--- Location: MLABCELL_X18_Y10_N57
-\myVirtualToplevel|Equal34~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal34~1_combout\ = ( !\myVirtualToplevel|MILLISEC_UP_TICK\(11) & ( (\myVirtualToplevel|MILLISEC_UP_TICK\(9) & (\myVirtualToplevel|MILLISEC_UP_TICK\(10) & \myVirtualToplevel|MILLISEC_UP_TICK\(7))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000101000000000000010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(9),
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(10),
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(7),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(11),
- combout => \myVirtualToplevel|Equal34~1_combout\);
-
--- Location: LABCELL_X19_Y10_N24
-\myVirtualToplevel|Equal34~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal34~2_combout\ = ( !\myVirtualToplevel|MILLISEC_UP_TICK\(8) & ( \myVirtualToplevel|MILLISEC_UP_TICK\(15) & ( (\myVirtualToplevel|Equal34~0_combout\ & (!\myVirtualToplevel|MILLISEC_UP_TICK\(6) &
--- (\myVirtualToplevel|MILLISEC_UP_TICK\(16) & \myVirtualToplevel|Equal34~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal34~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(6),
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(16),
- datad => \myVirtualToplevel|ALT_INV_Equal34~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(8),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(15),
- combout => \myVirtualToplevel|Equal34~2_combout\);
-
--- Location: FF_X18_Y10_N16
-\myVirtualToplevel|MILLISEC_UP_TICK[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add16~1_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal34~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_TICK\(5));
-
--- Location: LABCELL_X19_Y10_N30
-\myVirtualToplevel|Equal34~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal34~4_combout\ = ( !\myVirtualToplevel|MILLISEC_UP_TICK\(5) & ( (\myVirtualToplevel|Equal34~3_combout\ & (\myVirtualToplevel|Equal34~2_combout\ & \myVirtualToplevel|MILLISEC_UP_TICK\(4))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000101000000000000010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal34~3_combout\,
- datac => \myVirtualToplevel|ALT_INV_Equal34~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(4),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_TICK\(5),
- combout => \myVirtualToplevel|Equal34~4_combout\);
-
--- Location: LABCELL_X16_Y13_N27
-\myVirtualToplevel|Equal3~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal3~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- combout => \myVirtualToplevel|Equal3~0_combout\);
-
--- Location: LABCELL_X12_Y11_N0
-\myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\ = ( \myVirtualToplevel|Equal34~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) ) # ( \myVirtualToplevel|Equal34~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) ) # (
--- !\myVirtualToplevel|Equal34~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|Equal3~0_combout\ & (\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000011111111111111111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_Equal3~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datae => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- combout => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\);
-
--- Location: FF_X17_Y11_N20
-\myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~69_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y11_N0
-\myVirtualToplevel|Add17~125\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~125_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|Add17~126\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(0),
- cin => GND,
- sumout => \myVirtualToplevel|Add17~125_sumout\,
- cout => \myVirtualToplevel|Add17~126\);
-
--- Location: FF_X17_Y11_N2
-\myVirtualToplevel|MILLISEC_UP_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~125_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(0));
-
--- Location: LABCELL_X17_Y11_N3
-\myVirtualToplevel|Add17~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~89_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add17~126\ ))
--- \myVirtualToplevel|Add17~90\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add17~126\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(1),
- cin => \myVirtualToplevel|Add17~126\,
- sumout => \myVirtualToplevel|Add17~89_sumout\,
- cout => \myVirtualToplevel|Add17~90\);
-
--- Location: FF_X17_Y11_N5
-\myVirtualToplevel|MILLISEC_UP_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~89_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(1));
-
--- Location: LABCELL_X17_Y11_N6
-\myVirtualToplevel|Add17~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~85_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add17~90\ ))
--- \myVirtualToplevel|Add17~86\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add17~90\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(2),
- cin => \myVirtualToplevel|Add17~90\,
- sumout => \myVirtualToplevel|Add17~85_sumout\,
- cout => \myVirtualToplevel|Add17~86\);
-
--- Location: FF_X17_Y11_N8
-\myVirtualToplevel|MILLISEC_UP_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~85_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(2));
-
--- Location: LABCELL_X17_Y11_N9
-\myVirtualToplevel|Add17~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~81_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(3) ) + ( GND ) + ( \myVirtualToplevel|Add17~86\ ))
--- \myVirtualToplevel|Add17~82\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(3) ) + ( GND ) + ( \myVirtualToplevel|Add17~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(3),
- cin => \myVirtualToplevel|Add17~86\,
- sumout => \myVirtualToplevel|Add17~81_sumout\,
- cout => \myVirtualToplevel|Add17~82\);
-
--- Location: FF_X17_Y11_N11
-\myVirtualToplevel|MILLISEC_UP_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~81_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(3));
-
--- Location: LABCELL_X17_Y11_N12
-\myVirtualToplevel|Add17~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~49_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~82\ ))
--- \myVirtualToplevel|Add17~50\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[4]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add17~82\,
- sumout => \myVirtualToplevel|Add17~49_sumout\,
- cout => \myVirtualToplevel|Add17~50\);
-
--- Location: FF_X17_Y11_N14
-\myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~49_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER[4]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y11_N15
-\myVirtualToplevel|Add17~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~53_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add17~50\ ))
--- \myVirtualToplevel|Add17~54\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add17~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(5),
- cin => \myVirtualToplevel|Add17~50\,
- sumout => \myVirtualToplevel|Add17~53_sumout\,
- cout => \myVirtualToplevel|Add17~54\);
-
--- Location: FF_X17_Y11_N17
-\myVirtualToplevel|MILLISEC_UP_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~53_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(5));
-
--- Location: LABCELL_X17_Y11_N18
-\myVirtualToplevel|Add17~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~69_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~54\ ))
--- \myVirtualToplevel|Add17~70\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[6]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add17~54\,
- sumout => \myVirtualToplevel|Add17~69_sumout\,
- cout => \myVirtualToplevel|Add17~70\);
-
--- Location: FF_X17_Y11_N19
-\myVirtualToplevel|MILLISEC_UP_COUNTER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~69_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(6));
-
--- Location: MLABCELL_X13_Y12_N0
-\myVirtualToplevel|Add13~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~89_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|Add13~90\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(0),
- cin => GND,
- sumout => \myVirtualToplevel|Add13~89_sumout\,
- cout => \myVirtualToplevel|Add13~90\);
-
--- Location: LABCELL_X12_Y11_N27
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\ = ( \myVirtualToplevel|Equal3~0_combout\ & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ & ( (!\myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\) #
--- (\myVirtualToplevel|UART1|Equal7~0_combout\) ) ) ) # ( !\myVirtualToplevel|Equal3~0_combout\ & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ & ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\ ) ) ) # ( \myVirtualToplevel|Equal3~0_combout\ &
--- ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ & ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\ ) ) ) # ( !\myVirtualToplevel|Equal3~0_combout\ & ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\ & (
--- !\myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010101010101010111110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~0_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_Equal3~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\,
- combout => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\);
-
--- Location: FF_X13_Y12_N2
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~89_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(0));
-
--- Location: MLABCELL_X13_Y12_N3
-\myVirtualToplevel|Add13~93\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~93_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add13~90\ ))
--- \myVirtualToplevel|Add13~94\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add13~90\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(1),
- cin => \myVirtualToplevel|Add13~90\,
- sumout => \myVirtualToplevel|Add13~93_sumout\,
- cout => \myVirtualToplevel|Add13~94\);
-
--- Location: FF_X13_Y12_N5
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~93_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(1));
-
--- Location: MLABCELL_X13_Y12_N6
-\myVirtualToplevel|Add13~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~85_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~94\ ))
--- \myVirtualToplevel|Add13~86\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~94\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add13~94\,
- sumout => \myVirtualToplevel|Add13~85_sumout\,
- cout => \myVirtualToplevel|Add13~86\);
-
--- Location: FF_X13_Y12_N8
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~85_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y12_N9
-\myVirtualToplevel|Add13~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~81_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add13~86\ ))
--- \myVirtualToplevel|Add13~82\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add13~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(3),
- cin => \myVirtualToplevel|Add13~86\,
- sumout => \myVirtualToplevel|Add13~81_sumout\,
- cout => \myVirtualToplevel|Add13~82\);
-
--- Location: FF_X13_Y12_N11
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~81_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(3));
-
--- Location: MLABCELL_X13_Y12_N12
-\myVirtualToplevel|Add13~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~49_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add13~82\ ))
--- \myVirtualToplevel|Add13~50\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add13~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(4),
- cin => \myVirtualToplevel|Add13~82\,
- sumout => \myVirtualToplevel|Add13~49_sumout\,
- cout => \myVirtualToplevel|Add13~50\);
-
--- Location: FF_X13_Y12_N14
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~49_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4));
-
--- Location: MLABCELL_X13_Y12_N15
-\myVirtualToplevel|Add13~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~53_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add13~50\ ))
--- \myVirtualToplevel|Add13~54\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add13~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(5),
- cin => \myVirtualToplevel|Add13~50\,
- sumout => \myVirtualToplevel|Add13~53_sumout\,
- cout => \myVirtualToplevel|Add13~54\);
-
--- Location: FF_X13_Y12_N17
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~53_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(5));
-
--- Location: MLABCELL_X13_Y12_N18
-\myVirtualToplevel|Add13~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~69_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add13~54\ ))
--- \myVirtualToplevel|Add13~70\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add13~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(6),
- cin => \myVirtualToplevel|Add13~54\,
- sumout => \myVirtualToplevel|Add13~69_sumout\,
- cout => \myVirtualToplevel|Add13~70\);
-
--- Location: MLABCELL_X13_Y12_N21
-\myVirtualToplevel|Add13~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~73_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add13~70\ ))
--- \myVirtualToplevel|Add13~74\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|Add13~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(7),
- cin => \myVirtualToplevel|Add13~70\,
- sumout => \myVirtualToplevel|Add13~73_sumout\,
- cout => \myVirtualToplevel|Add13~74\);
-
--- Location: FF_X13_Y12_N22
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~73_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(7));
-
--- Location: MLABCELL_X13_Y12_N24
-\myVirtualToplevel|Add13~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~77_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add13~74\ ))
--- \myVirtualToplevel|Add13~78\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8) ) + ( VCC ) + ( \myVirtualToplevel|Add13~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(8),
- cin => \myVirtualToplevel|Add13~74\,
- sumout => \myVirtualToplevel|Add13~77_sumout\,
- cout => \myVirtualToplevel|Add13~78\);
-
--- Location: FF_X13_Y12_N26
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~77_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(8));
-
--- Location: MLABCELL_X13_Y12_N27
-\myVirtualToplevel|Add13~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~57_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add13~78\ ))
--- \myVirtualToplevel|Add13~58\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(9) ) + ( VCC ) + ( \myVirtualToplevel|Add13~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(9),
- cin => \myVirtualToplevel|Add13~78\,
- sumout => \myVirtualToplevel|Add13~57_sumout\,
- cout => \myVirtualToplevel|Add13~58\);
-
--- Location: FF_X13_Y12_N28
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~57_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(9));
-
--- Location: MLABCELL_X13_Y11_N0
-\myVirtualToplevel|Add13~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~61_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~58\ ))
--- \myVirtualToplevel|Add13~62\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add13~58\,
- sumout => \myVirtualToplevel|Add13~61_sumout\,
- cout => \myVirtualToplevel|Add13~62\);
-
--- Location: FF_X13_Y11_N2
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~61_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[10]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y11_N3
-\myVirtualToplevel|Add13~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~65_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add13~62\ ))
--- \myVirtualToplevel|Add13~66\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add13~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(11),
- cin => \myVirtualToplevel|Add13~62\,
- sumout => \myVirtualToplevel|Add13~65_sumout\,
- cout => \myVirtualToplevel|Add13~66\);
-
--- Location: FF_X13_Y11_N5
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~65_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(11));
-
--- Location: MLABCELL_X13_Y11_N6
-\myVirtualToplevel|Add13~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~33_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~66\ ))
--- \myVirtualToplevel|Add13~34\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add13~66\,
- sumout => \myVirtualToplevel|Add13~33_sumout\,
- cout => \myVirtualToplevel|Add13~34\);
-
--- Location: FF_X13_Y11_N8
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~33_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[12]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y11_N9
-\myVirtualToplevel|Add13~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~37_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~34\ ))
--- \myVirtualToplevel|Add13~38\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add13~34\,
- sumout => \myVirtualToplevel|Add13~37_sumout\,
- cout => \myVirtualToplevel|Add13~38\);
-
--- Location: FF_X13_Y11_N11
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~37_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[13]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y11_N12
-\myVirtualToplevel|Add13~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~41_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~38\ ))
--- \myVirtualToplevel|Add13~42\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add13~38\,
- sumout => \myVirtualToplevel|Add13~41_sumout\,
- cout => \myVirtualToplevel|Add13~42\);
-
--- Location: FF_X13_Y11_N14
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~41_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[14]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y11_N15
-\myVirtualToplevel|Add13~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~45_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|Add13~42\ ))
--- \myVirtualToplevel|Add13~46\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(15) ) + ( VCC ) + ( \myVirtualToplevel|Add13~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(15),
- cin => \myVirtualToplevel|Add13~42\,
- sumout => \myVirtualToplevel|Add13~45_sumout\,
- cout => \myVirtualToplevel|Add13~46\);
-
--- Location: FF_X13_Y11_N17
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~45_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(15));
-
--- Location: MLABCELL_X13_Y11_N18
-\myVirtualToplevel|Add13~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~1_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16) ) + ( VCC ) + ( \myVirtualToplevel|Add13~46\ ))
--- \myVirtualToplevel|Add13~2\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16) ) + ( VCC ) + ( \myVirtualToplevel|Add13~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(16),
- cin => \myVirtualToplevel|Add13~46\,
- sumout => \myVirtualToplevel|Add13~1_sumout\,
- cout => \myVirtualToplevel|Add13~2\);
-
--- Location: FF_X13_Y11_N20
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~1_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(16));
-
--- Location: MLABCELL_X13_Y11_N21
-\myVirtualToplevel|Add13~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~21_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~2\ ))
--- \myVirtualToplevel|Add13~22\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[17]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add13~2\,
- sumout => \myVirtualToplevel|Add13~21_sumout\,
- cout => \myVirtualToplevel|Add13~22\);
-
--- Location: FF_X9_Y18_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_NEW_REG1614\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]_OTERM1615\);
-
--- Location: LABCELL_X24_Y24_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[2]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[2]~0_combout\);
-
--- Location: LABCELL_X29_Y25_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[3]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[3]~1_combout\);
-
--- Location: FF_X35_Y21_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1694~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[12]~0_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\);
-
--- Location: LABCELL_X31_Y28_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010000010100000101000001011111010111110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[4]~2_combout\);
-
--- Location: LABCELL_X29_Y24_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(5) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[5]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[5]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(5),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[5]~3_combout\);
-
--- Location: MLABCELL_X28_Y24_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\) ) ) #
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[6]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[6]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[6]~4_combout\);
-
--- Location: LABCELL_X32_Y24_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(7) & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001100000011000000111111001111110011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(7),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(7),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[7]~5_combout\);
-
--- Location: MLABCELL_X23_Y23_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[8]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(8) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100110011001111001100110011001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[8]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(8),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[8]~6_combout\);
-
--- Location: LABCELL_X32_Y24_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(9) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[9]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000000000000000000110011001100111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[9]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(9),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[9]~7_combout\);
-
--- Location: LABCELL_X21_Y27_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC\(10) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[10]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC\(10),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[10]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[10]~8_combout\);
-
--- Location: MLABCELL_X23_Y23_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|debugPC[11]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[11]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010000010100000101000001011111010111110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[11]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugPC[11]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Mux2Addr[11]~9_combout\);
-
--- Location: FF_X18_Y14_N8
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0));
-
--- Location: LABCELL_X17_Y14_N18
-\myVirtualToplevel|LessThan0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|LessThan0~1_combout\ = ( \myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23),
- dataf => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\,
- combout => \myVirtualToplevel|LessThan0~1_combout\);
-
--- Location: FF_X13_Y14_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0));
-
--- Location: MLABCELL_X13_Y14_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux89~2_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux7~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|Equal4~0_combout\)
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000000000011001100001111001100110000111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux89~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal4~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux7~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0_combout\);
-
--- Location: MLABCELL_X13_Y14_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEMXACT~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState~36_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|WideOr116~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector216~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100110111000001010011011100000000001100110000000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState~36_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(0),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector216~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr116~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEMXACT~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1_combout\);
-
--- Location: FF_X13_Y14_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector216~1_combout\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y14_N39
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010000010100000101011111010101010101111101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\);
-
--- Location: MLABCELL_X23_Y14_N21
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node[0]\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0) = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~0_combout\ & ( (\myVirtualToplevel|BRAM_WREN~1_combout\
--- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & \myVirtualToplevel|LessThan3~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000001000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM0_WREN~0_combout\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0));
-
--- Location: FF_X16_Y14_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector208~0_combout\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[8]~103_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(8));
-
--- Location: M10K_X22_Y14_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011513680414814204E7226F0380A08C0442000835B00000020039320000000301590824C1042810A509248008A96310001001040FFFFFFDB0056A404000E00000C4014494C540A40207840488102440900770955330A72AB2A610F3A2CE60602924497424964143AE0AA43138BAA",
- mem_init2 => "067C11C0022E13C9C7909383CDA54530B03ECE3C90CE0EB89C200CF84E380400A4B550F11813B42D093DA85123AB907D5B24182C819D05BE046103E40504821FDA8A304554AA8304AA554182D0147066090D2C05618A1380C81C0BD4AE9277CD5835D5C924840801817518498DE378790655D46E856FFD63E92E767F7A7599C6D9F28E65410BC01DEE8090C31CB7481CB71421E1D686425928A2001A700088A41A309B44CB16A902A3146042B4CF32D54A462254C80D2A4A38A9034C1480CFE470C17ECA249404F0830033F4804CE050001CAC810D9749009393EDA8A4800008C22513011809A56345234F48440AF1A8809E408882195C2CF03A36960110670A",
- mem_init1 => "42298895DB70147596E26AEC0C8CC2001FE0707AC90A74BAE41C84A383532880785073896BE24E8408566692213641D9D449A6A419ACB025A348D23A1ACD45D504E040461B5B49E2D7198A874B968C53BD558BF0500381141C293FD176985E14854B0A420DEBC5F282EC8CDDD484B7175ABB4C926A388293C0130841D50181419F9F91E3BAC1238144D8A04D8F06F2138F49427F6194C128C2C9434C341EA6E883565D1C36AD2353BF43D091BA443C9E13C604900D000190136B184CA9AA98151F941F1511200012328D84C369B857FC1B00517C52A001533E0CB39ADD3650ACB118329E73D5C32A8423566E050D3C1C427252E307F6125DE404504020EF8905",
- mem_init0 => "9044D120477E118C6003627BBF12C62904064C842110961A819E29470AF0D8590054080050881A4EEF2AE8EB180808DDBCB089B525BA0B607BA66A4F48EED4043CE058A26A5C12102C041B302417440118C8E49257039BAEF5C3870E1C30E1F8433080CB98C219730843AE64C6130984CA0C81E8060BCCC810D1760341408377BA1795567610A41095553F6DB71B68D4A081F0EC01C1E66F7A285C0A1002D110A09809610BA0000040880055448008881100A420468CB2802B00340000000000000000000000000002C005000B003600FFFFFFFFFFFA4924936DB6DA492492FEFD000300010000162A000414180300000C0C1A0707010100032E031E7A180001",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 1,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 1,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\);
-
--- Location: M10K_X11_Y14_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 1,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 1,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\);
-
--- Location: MLABCELL_X18_Y14_N51
-\myVirtualToplevel|MEM_DATA_READ[1]~64\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[1]~64_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ &
--- ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0)))) ) ) # (
--- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a9~portbdataout\ & ( (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0) & (\myVirtualToplevel|LessThan0~1_combout\ &
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a1~portbdataout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001100000000000000110000000011000011110000001100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b\(0),
- datac => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\,
- datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[1]~64_combout\);
-
--- Location: MLABCELL_X18_Y14_N30
-\myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\ = ( \myVirtualToplevel|MEM_DATA_READ[1]~63_combout\ & ( (((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) #
--- (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[1]~64_combout\) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[1]~63_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]~35_combout\ &
--- \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[1]~64_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101110111010101010111011101011111011111110101111101111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~64_combout\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]~35_combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~63_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\);
-
--- Location: LABCELL_X10_Y16_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( \myVirtualToplevel|MEM_BUSY~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ &
--- ( \myVirtualToplevel|MEM_BUSY~1_combout\ ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( !\myVirtualToplevel|MEM_BUSY~1_combout\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & (
--- !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( (!\myVirtualToplevel|RESET_n~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111001111111111111111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\);
-
--- Location: MLABCELL_X9_Y18_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_OTERM3217\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux86~2_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101000111000000000100011111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux86~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~65_Duplicate_152\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[1]_NEW3216_RESYN13452_BDD13453\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_OTERM3217\);
-
--- Location: FF_X9_Y18_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[1]_OTERM3217\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1));
-
--- Location: LABCELL_X21_Y15_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\ = ( \myVirtualToplevel|MEM_BUSY~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ & ( ((!\myVirtualToplevel|RESET_n~q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\) ) ) ) # (
--- \myVirtualToplevel|MEM_BUSY~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) ) # ( !\myVirtualToplevel|MEM_BUSY~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111011111110111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datab => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- datae => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\);
-
--- Location: FF_X16_Y14_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector210~0_combout\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[16]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6));
-
--- Location: M10K_X11_Y16_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 2,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 2,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10_PORTBDATAOUT_bus\);
-
--- Location: MLABCELL_X23_Y9_N12
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(1) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(1),
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder_combout\);
-
--- Location: LABCELL_X26_Y7_N42
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0) &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\ & (((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0))))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal6~1_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0)) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(0))))) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v\(1) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[9]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010111001011111010100000000000000001100010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[9]~DUPLICATE_q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal6~1_combout\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0),
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v\(1),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\);
-
--- Location: LABCELL_X25_Y7_N54
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & (
--- (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & (((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\)))) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ &
--- ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\) # ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ & (
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ & ((!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~0_combout\) #
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|byteCnt_v[2]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Equal3~0_combout\ & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RD_BLK~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100111111111100100011001000110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector63~0_combout\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RD_BLK~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_byteCnt_v[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnData_v~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Equal3~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1_combout\);
-
--- Location: FF_X25_Y7_N55
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector63~1_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[13]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\);
-
--- Location: LABCELL_X24_Y7_N3
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~0_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rtnData_v~q\ &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.RX_BITS~q\ & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~45_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rtnData_v~q\,
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.RX_BITS~q\,
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~45_combout\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o[3]~0_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\);
-
--- Location: FF_X23_Y9_N13
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[2]~feeder_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(2));
-
--- Location: FF_X18_Y9_N44
-\myVirtualToplevel|SD_ADDR[0][2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2),
- sload => VCC,
- ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_ADDR[0][2]~q\);
-
--- Location: MLABCELL_X18_Y9_N57
-\myVirtualToplevel|Mux81~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux81~0_combout\ = ( \myVirtualToplevel|SD_ADDR[0][2]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\)))) ) ) # (
--- !\myVirtualToplevel|SD_ADDR[0][2]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|hndShk_r~DUPLICATE_q\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000101000000110000010111110011000001011111001100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_hndShk_r~DUPLICATE_q\,
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_SD_ADDR[0][2]~q\,
- combout => \myVirtualToplevel|Mux81~0_combout\);
-
--- Location: FF_X18_Y9_N58
-\myVirtualToplevel|IO_DATA_READ_SD[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Mux81~0_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SD\(2));
-
--- Location: LABCELL_X16_Y14_N0
-\myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(11),
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\);
-
--- Location: LABCELL_X16_Y14_N18
-\myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125_BDD9126\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9)) # (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1011111111111111111111111111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125_BDD9126\);
-
--- Location: LABCELL_X17_Y14_N30
-\myVirtualToplevel|MEM_DATA_READ[2]~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ = ( \myVirtualToplevel|IO_SELECT~2_combout\ & ( \myVirtualToplevel|SD_CS~0_combout\ & ( ((!\myVirtualToplevel|IO_SELECT~0_combout\) # (!\myVirtualToplevel|IO_SELECT~1_combout\)) #
--- (\myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\) ) ) ) # ( !\myVirtualToplevel|IO_SELECT~2_combout\ & ( \myVirtualToplevel|SD_CS~0_combout\ ) ) # ( \myVirtualToplevel|IO_SELECT~2_combout\ & ( !\myVirtualToplevel|SD_CS~0_combout\ & (
--- ((!\myVirtualToplevel|IO_SELECT~0_combout\) # ((!\myVirtualToplevel|IO_SELECT~1_combout\) # (\myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9125_BDD9126\))) # (\myVirtualToplevel|MEM_DATA_READ[2]~34_RESYN9127_BDD9128\) ) ) ) # (
--- !\myVirtualToplevel|IO_SELECT~2_combout\ & ( !\myVirtualToplevel|SD_CS~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111011111111111111111111111111111110111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9127_BDD9128\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_RESYN9125_BDD9126\,
- datae => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\,
- dataf => \myVirtualToplevel|ALT_INV_SD_CS~0_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~34_combout\);
-
--- Location: LABCELL_X14_Y9_N18
-\myVirtualToplevel|IO_DATA_READ[0]~70\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[0]~70_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) # (
--- !\myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|TIMER0_CS~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000100010001000100010001000100000001000000010000000100000001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datab => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|IO_DATA_READ[0]~70_combout\);
-
--- Location: FF_X10_Y5_N52
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(19));
-
--- Location: FF_X10_Y5_N19
-\myVirtualToplevel|UART0|RX_FIFO~20\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO~20_q\);
-
--- Location: LABCELL_X10_Y5_N18
-\myVirtualToplevel|UART0|RX_DATA~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA~14_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ & ( \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ &
--- (\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ((\myVirtualToplevel|UART0|RX_FIFO~20_q\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ & (
--- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a2\)) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ &
--- ((\myVirtualToplevel|UART0|RX_FIFO~20_q\))) ) ) ) # ( \myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(19)) #
--- (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER[3]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ &
--- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(19)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000100010011101110111011100001010010111110000101001011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(19),
- datac => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~20_q\,
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER[3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA~14_combout\);
-
--- Location: MLABCELL_X9_Y5_N0
-\myVirtualToplevel|UART0|RX_DATA[2]~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA[2]~15_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~14_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ & \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(2)) ) ) # (
--- !\myVirtualToplevel|UART0|RX_DATA~14_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(2) & ((!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(2),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~14_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA[2]~15_combout\);
-
--- Location: FF_X9_Y5_N1
-\myVirtualToplevel|UART0|RX_DATA[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_DATA[2]~15_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_DATA\(2));
-
--- Location: LABCELL_X10_Y12_N0
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\ = ( \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ ) # ( !\myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ & \myVirtualToplevel|TIMER0_CS~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000100000000000000010011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- combout => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\);
-
--- Location: FF_X10_Y12_N59
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~9_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(9));
-
--- Location: LABCELL_X10_Y12_N30
-\myVirtualToplevel|Add5~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add5~33_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|Add5~34\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(0),
- cin => GND,
- sumout => \myVirtualToplevel|Add5~33_sumout\,
- cout => \myVirtualToplevel|Add5~34\);
-
--- Location: FF_X10_Y12_N32
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~33_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0));
-
--- Location: LABCELL_X10_Y12_N33
-\myVirtualToplevel|Add5~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add5~37_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add5~34\ ))
--- \myVirtualToplevel|Add5~38\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add5~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(1),
- cin => \myVirtualToplevel|Add5~34\,
- sumout => \myVirtualToplevel|Add5~37_sumout\,
- cout => \myVirtualToplevel|Add5~38\);
-
--- Location: FF_X10_Y12_N34
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~37_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(1));
-
--- Location: LABCELL_X10_Y12_N36
-\myVirtualToplevel|Add5~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add5~29_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add5~38\ ))
--- \myVirtualToplevel|Add5~30\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add5~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(2),
- cin => \myVirtualToplevel|Add5~38\,
- sumout => \myVirtualToplevel|Add5~29_sumout\,
- cout => \myVirtualToplevel|Add5~30\);
-
--- Location: FF_X10_Y12_N38
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~29_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2));
-
--- Location: LABCELL_X10_Y12_N39
-\myVirtualToplevel|Add5~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add5~25_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(3) ) + ( GND ) + ( \myVirtualToplevel|Add5~30\ ))
--- \myVirtualToplevel|Add5~26\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(3) ) + ( GND ) + ( \myVirtualToplevel|Add5~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(3),
- cin => \myVirtualToplevel|Add5~30\,
- sumout => \myVirtualToplevel|Add5~25_sumout\,
- cout => \myVirtualToplevel|Add5~26\);
-
--- Location: FF_X10_Y12_N41
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~25_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(3));
-
--- Location: LABCELL_X10_Y12_N42
-\myVirtualToplevel|Add5~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add5~1_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) ) + ( GND ) + ( \myVirtualToplevel|Add5~26\ ))
--- \myVirtualToplevel|Add5~2\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) ) + ( GND ) + ( \myVirtualToplevel|Add5~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(4),
- cin => \myVirtualToplevel|Add5~26\,
- sumout => \myVirtualToplevel|Add5~1_sumout\,
- cout => \myVirtualToplevel|Add5~2\);
-
--- Location: FF_X10_Y12_N44
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~1_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4));
-
--- Location: LABCELL_X10_Y12_N45
-\myVirtualToplevel|Add5~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add5~5_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add5~2\ ))
--- \myVirtualToplevel|Add5~6\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(5) ) + ( GND ) + ( \myVirtualToplevel|Add5~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(5),
- cin => \myVirtualToplevel|Add5~2\,
- sumout => \myVirtualToplevel|Add5~5_sumout\,
- cout => \myVirtualToplevel|Add5~6\);
-
--- Location: LABCELL_X10_Y12_N48
-\myVirtualToplevel|Add5~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add5~13_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(6) ) + ( GND ) + ( \myVirtualToplevel|Add5~6\ ))
--- \myVirtualToplevel|Add5~14\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(6) ) + ( GND ) + ( \myVirtualToplevel|Add5~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(6),
- cin => \myVirtualToplevel|Add5~6\,
- sumout => \myVirtualToplevel|Add5~13_sumout\,
- cout => \myVirtualToplevel|Add5~14\);
-
--- Location: FF_X10_Y12_N49
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~13_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(6));
-
--- Location: LABCELL_X10_Y12_N51
-\myVirtualToplevel|Add5~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add5~17_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add5~14\ ))
--- \myVirtualToplevel|Add5~18\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add5~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(7),
- cin => \myVirtualToplevel|Add5~14\,
- sumout => \myVirtualToplevel|Add5~17_sumout\,
- cout => \myVirtualToplevel|Add5~18\);
-
--- Location: FF_X10_Y12_N52
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~17_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(7));
-
--- Location: LABCELL_X10_Y12_N54
-\myVirtualToplevel|Add5~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add5~21_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(8) ) + ( GND ) + ( \myVirtualToplevel|Add5~18\ ))
--- \myVirtualToplevel|Add5~22\ = CARRY(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(8) ) + ( GND ) + ( \myVirtualToplevel|Add5~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(8),
- cin => \myVirtualToplevel|Add5~18\,
- sumout => \myVirtualToplevel|Add5~21_sumout\,
- cout => \myVirtualToplevel|Add5~22\);
-
--- Location: FF_X10_Y12_N56
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~21_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(8));
-
--- Location: LABCELL_X10_Y12_N57
-\myVirtualToplevel|Add5~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add5~9_sumout\ = SUM(( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(9) ) + ( GND ) + ( \myVirtualToplevel|Add5~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(9),
- cin => \myVirtualToplevel|Add5~22\,
- sumout => \myVirtualToplevel|Add5~9_sumout\);
-
--- Location: FF_X10_Y12_N58
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~9_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\);
-
--- Location: FF_X10_Y12_N35
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~37_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\);
-
--- Location: LABCELL_X10_Y12_N21
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\ = ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) & ( (\myVirtualToplevel|RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\ & (!\myVirtualToplevel|RTC_MILLISEC_COUNTER\(3) &
--- \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010000000000000101000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[1]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(3),
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(2),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(4),
- combout => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\);
-
--- Location: LABCELL_X10_Y12_N12
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ = ( \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\ & ( \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ & ( (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\ &
--- (\myVirtualToplevel|RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\ & \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[9]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(0),
- datae => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~2_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- combout => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\);
-
--- Location: FF_X10_Y12_N46
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~5_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER\(5));
-
--- Location: FF_X10_Y12_N47
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~5_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\);
-
--- Location: FF_X10_Y12_N50
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add5~13_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\,
- sload => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- ena => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\);
-
--- Location: LABCELL_X10_Y12_N18
-\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\ = ( \myVirtualToplevel|RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\ & ( (\myVirtualToplevel|RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\ & (\myVirtualToplevel|RTC_MILLISEC_COUNTER\(8) &
--- \myVirtualToplevel|RTC_MILLISEC_COUNTER\(7))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[5]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(8),
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(7),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\);
-
--- Location: LABCELL_X10_Y10_N57
-\myVirtualToplevel|RTC_SECOND_COUNTER~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_SECOND_COUNTER~5_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & !\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\) ) ) # (
--- !\myVirtualToplevel|RTC_SECOND_COUNTER\(0) & ( (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010111111111010101010000000001010101111111110101010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\,
- datae => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(0),
- combout => \myVirtualToplevel|RTC_SECOND_COUNTER~5_combout\);
-
--- Location: MLABCELL_X13_Y10_N15
-\myVirtualToplevel|RTC_SECOND_COUNTER[3]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\ = ( \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ ) ) # ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ & (
--- \myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ ) ) # ( \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\ & ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|TIMER0_CS~2_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000101011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\,
- datae => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\,
- combout => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\);
-
--- Location: FF_X10_Y10_N59
-\myVirtualToplevel|RTC_SECOND_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_SECOND_COUNTER~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_SECOND_COUNTER\(0));
-
--- Location: FF_X10_Y10_N58
-\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_SECOND_COUNTER~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\);
-
--- Location: LABCELL_X10_Y10_N0
-\myVirtualToplevel|RTC_SECOND_COUNTER~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_SECOND_COUNTER~6_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) #
--- (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & ((!\myVirtualToplevel|RTC_SECOND_COUNTER\(1)))) ) ) # ( !\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & ((\myVirtualToplevel|RTC_SECOND_COUNTER\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000111111001100000011111100111111001100000011111100110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1),
- datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(1),
- dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|RTC_SECOND_COUNTER~6_combout\);
-
--- Location: FF_X10_Y10_N1
-\myVirtualToplevel|RTC_SECOND_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_SECOND_COUNTER~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_SECOND_COUNTER\(1));
-
--- Location: LABCELL_X10_Y10_N3
-\myVirtualToplevel|Add6~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add6~0_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(1) & ( \myVirtualToplevel|RTC_SECOND_COUNTER\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(0),
- dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(1),
- combout => \myVirtualToplevel|Add6~0_combout\);
-
--- Location: LABCELL_X10_Y10_N15
-\myVirtualToplevel|RTC_SECOND_COUNTER~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_SECOND_COUNTER~4_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & !\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\) ) ) # (
--- !\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ &
--- (!\myVirtualToplevel|Add6~0_combout\ $ ((!\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111101100110000011110110011000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Add6~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\,
- combout => \myVirtualToplevel|RTC_SECOND_COUNTER~4_combout\);
-
--- Location: FF_X10_Y10_N17
-\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_SECOND_COUNTER~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\);
-
--- Location: FF_X10_Y10_N16
-\myVirtualToplevel|RTC_SECOND_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_SECOND_COUNTER~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_SECOND_COUNTER\(2));
-
--- Location: LABCELL_X10_Y10_N30
-\myVirtualToplevel|RTC_SECOND_COUNTER~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_SECOND_COUNTER~3_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( \myVirtualToplevel|RTC_SECOND_COUNTER\(2) & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) #
--- (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (((!\myVirtualToplevel|Add6~0_combout\ & !\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( \myVirtualToplevel|RTC_SECOND_COUNTER\(2) & (
--- (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (((\myVirtualToplevel|Add6~0_combout\ &
--- !\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\)))) ) ) ) # ( \myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( !\myVirtualToplevel|RTC_SECOND_COUNTER\(2) & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\))) ) ) ) # ( !\myVirtualToplevel|RTC_SECOND_COUNTER\(3) & (
--- !\myVirtualToplevel|RTC_SECOND_COUNTER\(2) & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000100010011101110010001000100111001000100111001000100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3),
- datac => \myVirtualToplevel|ALT_INV_Add6~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(3),
- dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(2),
- combout => \myVirtualToplevel|RTC_SECOND_COUNTER~3_combout\);
-
--- Location: FF_X10_Y10_N31
-\myVirtualToplevel|RTC_SECOND_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_SECOND_COUNTER~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_SECOND_COUNTER\(3));
-
--- Location: LABCELL_X10_Y10_N27
-\myVirtualToplevel|Add6~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add6~1_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(3) & ( (\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & \myVirtualToplevel|Add6~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_Add6~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(3),
- combout => \myVirtualToplevel|Add6~1_combout\);
-
--- Location: FF_X10_Y10_N26
-\myVirtualToplevel|RTC_SECOND_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_SECOND_COUNTER~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_SECOND_COUNTER\(4));
-
--- Location: LABCELL_X10_Y10_N24
-\myVirtualToplevel|RTC_SECOND_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_SECOND_COUNTER~0_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4)) ) ) # (
--- !\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ &
--- ((!\myVirtualToplevel|Add6~1_combout\ $ (!\myVirtualToplevel|RTC_SECOND_COUNTER\(4))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010011101110010001001110111001000100010001000100010001000100010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4),
- datac => \myVirtualToplevel|ALT_INV_Add6~1_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(4),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\,
- combout => \myVirtualToplevel|RTC_SECOND_COUNTER~0_combout\);
-
--- Location: FF_X10_Y10_N25
-\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_SECOND_COUNTER~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\);
-
--- Location: LABCELL_X10_Y10_N18
-\myVirtualToplevel|RTC_SECOND_COUNTER~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_SECOND_COUNTER~2_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(5) & ( \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5))))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (!\myVirtualToplevel|Add6~1_combout\ & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|RTC_SECOND_COUNTER\(5) & ( \myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5))))) #
--- (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|Add6~1_combout\ & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\)))) ) ) ) # ( \myVirtualToplevel|RTC_SECOND_COUNTER\(5) & (
--- !\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5))) # (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\ &
--- ((!\myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\))) ) ) ) # ( !\myVirtualToplevel|RTC_SECOND_COUNTER\(5) & ( !\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5) &
--- !\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~3_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001111110011000000110101001100000011101000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Add6~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5),
- datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~3_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(5),
- dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|RTC_SECOND_COUNTER~2_combout\);
-
--- Location: FF_X10_Y10_N19
-\myVirtualToplevel|RTC_SECOND_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_SECOND_COUNTER~2_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_SECOND_COUNTER[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_SECOND_COUNTER\(5));
-
--- Location: LABCELL_X10_Y10_N12
-\myVirtualToplevel|RTC_MINUTE_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ = ( \myVirtualToplevel|RTC_SECOND_COUNTER\(4) & ( (\myVirtualToplevel|Add6~0_combout\ & (!\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & (\myVirtualToplevel|RTC_SECOND_COUNTER\(3) &
--- \myVirtualToplevel|RTC_SECOND_COUNTER\(5)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001000000000000000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Add6~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(3),
- datad => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(5),
- dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER\(4),
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\);
-
--- Location: LABCELL_X10_Y12_N6
-\myVirtualToplevel|RTC_MINUTE_COUNTER~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER~0_combout\ & ( \myVirtualToplevel|RTC_MICROSEC_COUNTER[6]~2_combout\ & ( (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~1_combout\ &
--- (\myVirtualToplevel|RTC_MILLISEC_COUNTER\(9) & (\myVirtualToplevel|RTC_MILLISEC_COUNTER[3]~2_combout\ & \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~1_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(9),
- datac => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER[3]~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(0),
- datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER[6]~2_combout\,
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\);
-
--- Location: MLABCELL_X9_Y11_N45
-\myVirtualToplevel|RTC_MINUTE_COUNTER~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER~8_combout\ = (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ &
--- ((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(0))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011111100001100001111110000110000111111000011000011111100001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(0),
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~8_combout\);
-
--- Location: LABCELL_X10_Y11_N39
-\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\ = ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( ((\myVirtualToplevel|UART1|Mux0~0_combout\ & \myVirtualToplevel|RTC_MILLISEC_COUNTER~0_combout\)) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\) ) )
--- # ( !\myVirtualToplevel|TIMER0_CS~2_combout\ & ( \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111010111110000111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\,
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\);
-
--- Location: FF_X9_Y11_N46
-\myVirtualToplevel|RTC_MINUTE_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MINUTE_COUNTER~8_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(0));
-
--- Location: FF_X9_Y11_N47
-\myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MINUTE_COUNTER~8_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE_q\);
-
--- Location: MLABCELL_X9_Y11_N24
-\myVirtualToplevel|RTC_MINUTE_COUNTER~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER~9_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) #
--- (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(1)))) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ((\myVirtualToplevel|RTC_MINUTE_COUNTER\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000111111000011000011111100111111000011000011111100001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1),
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(1),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~9_combout\);
-
--- Location: FF_X9_Y11_N26
-\myVirtualToplevel|RTC_MINUTE_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MINUTE_COUNTER~9_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(1));
-
--- Location: MLABCELL_X9_Y11_N21
-\myVirtualToplevel|Add7~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add7~0_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(1) & ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(0),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(1),
- combout => \myVirtualToplevel|Add7~0_combout\);
-
--- Location: FF_X9_Y11_N4
-\myVirtualToplevel|RTC_MINUTE_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MINUTE_COUNTER~7_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(2));
-
--- Location: MLABCELL_X9_Y11_N48
-\myVirtualToplevel|RTC_MINUTE_COUNTER~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER~6_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(2) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))))) #
--- (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & ((!\myVirtualToplevel|Add7~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(2) & (
--- (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ &
--- ((\myVirtualToplevel|Add7~0_combout\)))) ) ) ) # ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(2) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)))) #
--- (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\)) ) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(2) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & !\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100000000001100111010101000110011000010100011001110100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3),
- datac => \myVirtualToplevel|ALT_INV_Add7~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(2),
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~6_combout\);
-
--- Location: FF_X9_Y11_N50
-\myVirtualToplevel|RTC_MINUTE_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MINUTE_COUNTER~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(3));
-
--- Location: MLABCELL_X9_Y11_N39
-\myVirtualToplevel|Add7~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add7~1_combout\ = !\myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ $ (((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(3)) # ((!\myVirtualToplevel|Add7~0_combout\) # (!\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100011110000011110001111000001111000111100000111100011110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3),
- datab => \myVirtualToplevel|ALT_INV_Add7~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|Add7~1_combout\);
-
--- Location: MLABCELL_X9_Y11_N0
-\myVirtualToplevel|RTC_MINUTE_COUNTER~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER~3_combout\ = ( \myVirtualToplevel|Add7~1_combout\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4)))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ &
--- (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\)) ) ) # ( !\myVirtualToplevel|Add7~1_combout\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100000011000000110000101110001011100010111000101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4),
- dataf => \myVirtualToplevel|ALT_INV_Add7~1_combout\,
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~3_combout\);
-
--- Location: FF_X9_Y11_N1
-\myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MINUTE_COUNTER~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\);
-
--- Location: FF_X9_Y11_N2
-\myVirtualToplevel|RTC_MINUTE_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MINUTE_COUNTER~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(4));
-
--- Location: FF_X9_Y11_N32
-\myVirtualToplevel|RTC_MINUTE_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MINUTE_COUNTER~10_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MINUTE_COUNTER\(5));
-
--- Location: MLABCELL_X9_Y11_N30
-\myVirtualToplevel|RTC_MINUTE_COUNTER~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER~10_combout\ = ( !\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ( (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5)))) ) ) # ( \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (
--- (!\myVirtualToplevel|RTC_MINUTE_COUNTER\(4) & (\myVirtualToplevel|RTC_MINUTE_COUNTER\(5))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER\(4) & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(5) & (\myVirtualToplevel|Add7~0_combout\ &
--- (\myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & \myVirtualToplevel|RTC_MINUTE_COUNTER\(2)))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER\(5) & ((!\myVirtualToplevel|Add7~0_combout\) # ((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(3))))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "on",
- lut_mask => "0000111100001111001100110011001000001111000011110011001100110110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(4),
- datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(5),
- datac => \myVirtualToplevel|ALT_INV_Add7~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3),
- datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(2),
- datag => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5),
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~10_combout\);
-
--- Location: FF_X9_Y11_N31
-\myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MINUTE_COUNTER~10_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\);
-
--- Location: MLABCELL_X9_Y11_N36
-\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|RTC_MINUTE_COUNTER\(3) & (\myVirtualToplevel|Add7~0_combout\ & (!\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ &
--- \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000100000000000000010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(3),
- datab => \myVirtualToplevel|ALT_INV_Add7~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[4]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[5]~DUPLICATE_q\,
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\);
-
--- Location: MLABCELL_X9_Y11_N3
-\myVirtualToplevel|RTC_MINUTE_COUNTER~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER~7_combout\ = ( \myVirtualToplevel|Add7~0_combout\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ &
--- (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & ((!\myVirtualToplevel|RTC_MINUTE_COUNTER\(2))))) ) ) # ( !\myVirtualToplevel|Add7~0_combout\ & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & ((\myVirtualToplevel|RTC_MINUTE_COUNTER\(2))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000101110000011000010111000101110000011000010111000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(2),
- dataf => \myVirtualToplevel|ALT_INV_Add7~0_combout\,
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER~7_combout\);
-
--- Location: FF_X9_Y11_N5
-\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MINUTE_COUNTER~7_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\);
-
--- Location: LABCELL_X10_Y10_N6
-\myVirtualToplevel|IO_DATA_READ~74\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~74_combout\ = ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) & ( \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) #
--- (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(2))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\))) ) ) ) # (
--- !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) & ( \myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(2))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) ) # ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) & (
--- !\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(2) & ( !\myVirtualToplevel|RTC_SECOND_COUNTER[2]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|RTC_MINUTE_COUNTER[2]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000010001001111110001000100001100110111010011111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[2]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datae => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(2),
- dataf => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|IO_DATA_READ~74_combout\);
-
--- Location: LABCELL_X14_Y12_N0
-\myVirtualToplevel|Add15~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~65_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|Add15~66\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(0),
- cin => GND,
- sumout => \myVirtualToplevel|Add15~65_sumout\,
- cout => \myVirtualToplevel|Add15~66\);
-
--- Location: LABCELL_X16_Y12_N54
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ &
--- (\myVirtualToplevel|TIMER0_CS~2_combout\ & (\myVirtualToplevel|INTR0_CS~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datab => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER~0_combout\,
- combout => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\);
-
--- Location: FF_X14_Y12_N1
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~65_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0));
-
--- Location: LABCELL_X14_Y12_N3
-\myVirtualToplevel|Add15~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~69_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add15~66\ ))
--- \myVirtualToplevel|Add15~70\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|Add15~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(1),
- cin => \myVirtualToplevel|Add15~66\,
- sumout => \myVirtualToplevel|Add15~69_sumout\,
- cout => \myVirtualToplevel|Add15~70\);
-
--- Location: FF_X14_Y12_N5
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~69_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1));
-
--- Location: LABCELL_X14_Y12_N6
-\myVirtualToplevel|Add15~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~61_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~70\ ))
--- \myVirtualToplevel|Add15~62\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add15~70\,
- sumout => \myVirtualToplevel|Add15~61_sumout\,
- cout => \myVirtualToplevel|Add15~62\);
-
--- Location: LABCELL_X14_Y12_N9
-\myVirtualToplevel|Add15~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~57_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add15~62\ ))
--- \myVirtualToplevel|Add15~58\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|Add15~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(3),
- cin => \myVirtualToplevel|Add15~62\,
- sumout => \myVirtualToplevel|Add15~57_sumout\,
- cout => \myVirtualToplevel|Add15~58\);
-
--- Location: FF_X14_Y12_N11
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~57_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3));
-
--- Location: LABCELL_X14_Y12_N12
-\myVirtualToplevel|Add15~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~25_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add15~58\ ))
--- \myVirtualToplevel|Add15~26\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|Add15~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(4),
- cin => \myVirtualToplevel|Add15~58\,
- sumout => \myVirtualToplevel|Add15~25_sumout\,
- cout => \myVirtualToplevel|Add15~26\);
-
--- Location: FF_X14_Y12_N14
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~25_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4));
-
--- Location: MLABCELL_X13_Y12_N39
-\myVirtualToplevel|Equal33~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal33~3_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) & ( (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(3) & (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(2) & !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(1))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(3),
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(2),
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(1),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(4),
- combout => \myVirtualToplevel|Equal33~3_combout\);
-
--- Location: LABCELL_X14_Y12_N15
-\myVirtualToplevel|Add15~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~29_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add15~26\ ))
--- \myVirtualToplevel|Add15~30\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|Add15~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(5),
- cin => \myVirtualToplevel|Add15~26\,
- sumout => \myVirtualToplevel|Add15~29_sumout\,
- cout => \myVirtualToplevel|Add15~30\);
-
--- Location: FF_X14_Y12_N16
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~29_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5));
-
--- Location: LABCELL_X14_Y12_N18
-\myVirtualToplevel|Add15~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~45_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add15~30\ ))
--- \myVirtualToplevel|Add15~46\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|Add15~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(6),
- cin => \myVirtualToplevel|Add15~30\,
- sumout => \myVirtualToplevel|Add15~45_sumout\,
- cout => \myVirtualToplevel|Add15~46\);
-
--- Location: FF_X14_Y12_N20
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~45_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6));
-
--- Location: LABCELL_X14_Y12_N21
-\myVirtualToplevel|Add15~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~49_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~46\ ))
--- \myVirtualToplevel|Add15~50\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add15~46\,
- sumout => \myVirtualToplevel|Add15~49_sumout\,
- cout => \myVirtualToplevel|Add15~50\);
-
--- Location: FF_X14_Y12_N23
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~49_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y12_N24
-\myVirtualToplevel|Add15~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~53_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~50\ ))
--- \myVirtualToplevel|Add15~54\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add15~50\,
- sumout => \myVirtualToplevel|Add15~53_sumout\,
- cout => \myVirtualToplevel|Add15~54\);
-
--- Location: FF_X14_Y12_N26
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~53_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y12_N27
-\myVirtualToplevel|Add15~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~33_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~54\ ))
--- \myVirtualToplevel|Add15~34\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add15~54\,
- sumout => \myVirtualToplevel|Add15~33_sumout\,
- cout => \myVirtualToplevel|Add15~34\);
-
--- Location: FF_X14_Y12_N29
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~33_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y12_N30
-\myVirtualToplevel|Add15~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~37_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add15~34\ ))
--- \myVirtualToplevel|Add15~38\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10) ) + ( VCC ) + ( \myVirtualToplevel|Add15~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(10),
- cin => \myVirtualToplevel|Add15~34\,
- sumout => \myVirtualToplevel|Add15~37_sumout\,
- cout => \myVirtualToplevel|Add15~38\);
-
--- Location: FF_X14_Y12_N32
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~37_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10));
-
--- Location: LABCELL_X14_Y12_N33
-\myVirtualToplevel|Add15~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~41_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add15~38\ ))
--- \myVirtualToplevel|Add15~42\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(11) ) + ( VCC ) + ( \myVirtualToplevel|Add15~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(11),
- cin => \myVirtualToplevel|Add15~38\,
- sumout => \myVirtualToplevel|Add15~41_sumout\,
- cout => \myVirtualToplevel|Add15~42\);
-
--- Location: FF_X14_Y12_N35
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~41_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(11));
-
--- Location: LABCELL_X14_Y12_N36
-\myVirtualToplevel|Add15~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~9_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add15~42\ ))
--- \myVirtualToplevel|Add15~10\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12) ) + ( VCC ) + ( \myVirtualToplevel|Add15~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(12),
- cin => \myVirtualToplevel|Add15~42\,
- sumout => \myVirtualToplevel|Add15~9_sumout\,
- cout => \myVirtualToplevel|Add15~10\);
-
--- Location: FF_X14_Y12_N37
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~9_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12));
-
--- Location: LABCELL_X14_Y12_N39
-\myVirtualToplevel|Add15~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~13_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~10\ ))
--- \myVirtualToplevel|Add15~14\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add15~10\,
- sumout => \myVirtualToplevel|Add15~13_sumout\,
- cout => \myVirtualToplevel|Add15~14\);
-
--- Location: FF_X14_Y12_N41
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~13_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y12_N42
-\myVirtualToplevel|Add15~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~17_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~14\ ))
--- \myVirtualToplevel|Add15~18\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add15~14\,
- sumout => \myVirtualToplevel|Add15~17_sumout\,
- cout => \myVirtualToplevel|Add15~18\);
-
--- Location: FF_X14_Y12_N44
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~17_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y12_N45
-\myVirtualToplevel|Add15~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~21_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~18\ ))
--- \myVirtualToplevel|Add15~22\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add15~18\,
- sumout => \myVirtualToplevel|Add15~21_sumout\,
- cout => \myVirtualToplevel|Add15~22\);
-
--- Location: FF_X14_Y12_N47
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~21_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y12_N48
-\myVirtualToplevel|Add15~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~1_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~22\ ))
--- \myVirtualToplevel|Add15~2\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add15~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add15~22\,
- sumout => \myVirtualToplevel|Add15~1_sumout\,
- cout => \myVirtualToplevel|Add15~2\);
-
--- Location: FF_X14_Y12_N50
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~1_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y12_N57
-\myVirtualToplevel|Equal33~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal33~0_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\ & ( (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\ & (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\ &
--- !\myVirtualToplevel|MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[16]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[15]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[13]~DUPLICATE_q\,
- combout => \myVirtualToplevel|Equal33~0_combout\);
-
--- Location: LABCELL_X14_Y12_N51
-\myVirtualToplevel|Add15~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add15~5_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(17) ) + ( VCC ) + ( \myVirtualToplevel|Add15~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(17),
- cin => \myVirtualToplevel|Add15~2\,
- sumout => \myVirtualToplevel|Add15~5_sumout\);
-
--- Location: FF_X14_Y12_N52
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~5_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(17));
-
--- Location: LABCELL_X14_Y12_N54
-\myVirtualToplevel|Equal33~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal33~1_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\ & ( (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(10) & (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\ &
--- !\myVirtualToplevel|MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(10),
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[9]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[8]~DUPLICATE_q\,
- combout => \myVirtualToplevel|Equal33~1_combout\);
-
--- Location: FF_X14_Y12_N34
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~41_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y12_N15
-\myVirtualToplevel|Equal33~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal33~2_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\ & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(12) & ( (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0) & (\myVirtualToplevel|Equal33~0_combout\ &
--- (!\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(17) & \myVirtualToplevel|Equal33~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000100000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(0),
- datab => \myVirtualToplevel|ALT_INV_Equal33~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(17),
- datad => \myVirtualToplevel|ALT_INV_Equal33~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER[11]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(12),
- combout => \myVirtualToplevel|Equal33~2_combout\);
-
--- Location: LABCELL_X19_Y40_N0
-\myVirtualToplevel|Add14~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~69_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|Add14~70\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(0),
- cin => GND,
- sumout => \myVirtualToplevel|Add14~69_sumout\,
- cout => \myVirtualToplevel|Add14~70\);
-
--- Location: FF_X19_Y40_N2
-\myVirtualToplevel|MILLISEC_DOWN_TICK[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~69_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(0));
-
--- Location: LABCELL_X19_Y40_N3
-\myVirtualToplevel|Add14~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~65_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add14~70\ ))
--- \myVirtualToplevel|Add14~66\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(1) ) + ( GND ) + ( \myVirtualToplevel|Add14~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(1),
- cin => \myVirtualToplevel|Add14~70\,
- sumout => \myVirtualToplevel|Add14~65_sumout\,
- cout => \myVirtualToplevel|Add14~66\);
-
--- Location: FF_X19_Y40_N5
-\myVirtualToplevel|MILLISEC_DOWN_TICK[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~65_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(1));
-
--- Location: LABCELL_X19_Y40_N6
-\myVirtualToplevel|Add14~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~61_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add14~66\ ))
--- \myVirtualToplevel|Add14~62\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(2) ) + ( GND ) + ( \myVirtualToplevel|Add14~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(2),
- cin => \myVirtualToplevel|Add14~66\,
- sumout => \myVirtualToplevel|Add14~61_sumout\,
- cout => \myVirtualToplevel|Add14~62\);
-
--- Location: FF_X19_Y40_N8
-\myVirtualToplevel|MILLISEC_DOWN_TICK[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~61_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(2));
-
--- Location: LABCELL_X19_Y40_N9
-\myVirtualToplevel|Add14~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~5_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add14~62\ ))
--- \myVirtualToplevel|Add14~6\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(3) ) + ( GND ) + ( \myVirtualToplevel|Add14~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(3),
- cin => \myVirtualToplevel|Add14~62\,
- sumout => \myVirtualToplevel|Add14~5_sumout\,
- cout => \myVirtualToplevel|Add14~6\);
-
--- Location: FF_X19_Y40_N11
-\myVirtualToplevel|MILLISEC_DOWN_TICK[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~5_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(3));
-
--- Location: LABCELL_X19_Y40_N12
-\myVirtualToplevel|Add14~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~57_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add14~6\ ))
--- \myVirtualToplevel|Add14~58\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(4) ) + ( GND ) + ( \myVirtualToplevel|Add14~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(4),
- cin => \myVirtualToplevel|Add14~6\,
- sumout => \myVirtualToplevel|Add14~57_sumout\,
- cout => \myVirtualToplevel|Add14~58\);
-
--- Location: FF_X19_Y40_N14
-\myVirtualToplevel|MILLISEC_DOWN_TICK[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~57_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(4));
-
--- Location: LABCELL_X19_Y40_N54
-\myVirtualToplevel|Equal32~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal32~3_combout\ = ( \myVirtualToplevel|MILLISEC_DOWN_TICK\(4) & ( (\myVirtualToplevel|MILLISEC_DOWN_TICK\(2) & (\myVirtualToplevel|MILLISEC_DOWN_TICK\(0) & \myVirtualToplevel|MILLISEC_DOWN_TICK\(1))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(2),
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(0),
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(1),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(4),
- combout => \myVirtualToplevel|Equal32~3_combout\);
-
--- Location: FF_X19_Y40_N50
-\myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~9_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y40_N15
-\myVirtualToplevel|Add14~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~1_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add14~58\ ))
--- \myVirtualToplevel|Add14~2\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(5) ) + ( GND ) + ( \myVirtualToplevel|Add14~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(5),
- cin => \myVirtualToplevel|Add14~58\,
- sumout => \myVirtualToplevel|Add14~1_sumout\,
- cout => \myVirtualToplevel|Add14~2\);
-
--- Location: FF_X19_Y40_N17
-\myVirtualToplevel|MILLISEC_DOWN_TICK[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~1_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(5));
-
--- Location: LABCELL_X19_Y40_N18
-\myVirtualToplevel|Add14~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~21_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add14~2\ ))
--- \myVirtualToplevel|Add14~22\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(6) ) + ( GND ) + ( \myVirtualToplevel|Add14~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(6),
- cin => \myVirtualToplevel|Add14~2\,
- sumout => \myVirtualToplevel|Add14~21_sumout\,
- cout => \myVirtualToplevel|Add14~22\);
-
--- Location: FF_X19_Y40_N20
-\myVirtualToplevel|MILLISEC_DOWN_TICK[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~21_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(6));
-
--- Location: LABCELL_X19_Y40_N21
-\myVirtualToplevel|Add14~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~53_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add14~22\ ))
--- \myVirtualToplevel|Add14~54\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(7) ) + ( GND ) + ( \myVirtualToplevel|Add14~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(7),
- cin => \myVirtualToplevel|Add14~22\,
- sumout => \myVirtualToplevel|Add14~53_sumout\,
- cout => \myVirtualToplevel|Add14~54\);
-
--- Location: FF_X19_Y40_N22
-\myVirtualToplevel|MILLISEC_DOWN_TICK[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~53_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(7));
-
--- Location: LABCELL_X19_Y40_N24
-\myVirtualToplevel|Add14~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~17_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add14~54\ ))
--- \myVirtualToplevel|Add14~18\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(8) ) + ( GND ) + ( \myVirtualToplevel|Add14~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(8),
- cin => \myVirtualToplevel|Add14~54\,
- sumout => \myVirtualToplevel|Add14~17_sumout\,
- cout => \myVirtualToplevel|Add14~18\);
-
--- Location: FF_X19_Y40_N26
-\myVirtualToplevel|MILLISEC_DOWN_TICK[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~17_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(8));
-
--- Location: LABCELL_X19_Y40_N27
-\myVirtualToplevel|Add14~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~49_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add14~18\ ))
--- \myVirtualToplevel|Add14~50\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(9) ) + ( GND ) + ( \myVirtualToplevel|Add14~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(9),
- cin => \myVirtualToplevel|Add14~18\,
- sumout => \myVirtualToplevel|Add14~49_sumout\,
- cout => \myVirtualToplevel|Add14~50\);
-
--- Location: FF_X19_Y40_N28
-\myVirtualToplevel|MILLISEC_DOWN_TICK[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~49_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(9));
-
--- Location: LABCELL_X19_Y40_N30
-\myVirtualToplevel|Add14~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~45_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add14~50\ ))
--- \myVirtualToplevel|Add14~46\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(10) ) + ( GND ) + ( \myVirtualToplevel|Add14~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(10),
- cin => \myVirtualToplevel|Add14~50\,
- sumout => \myVirtualToplevel|Add14~45_sumout\,
- cout => \myVirtualToplevel|Add14~46\);
-
--- Location: FF_X19_Y40_N32
-\myVirtualToplevel|MILLISEC_DOWN_TICK[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~45_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(10));
-
--- Location: LABCELL_X19_Y40_N33
-\myVirtualToplevel|Add14~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~41_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add14~46\ ))
--- \myVirtualToplevel|Add14~42\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(11) ) + ( GND ) + ( \myVirtualToplevel|Add14~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(11),
- cin => \myVirtualToplevel|Add14~46\,
- sumout => \myVirtualToplevel|Add14~41_sumout\,
- cout => \myVirtualToplevel|Add14~42\);
-
--- Location: FF_X19_Y40_N35
-\myVirtualToplevel|MILLISEC_DOWN_TICK[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~41_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(11));
-
--- Location: LABCELL_X19_Y40_N36
-\myVirtualToplevel|Add14~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~37_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~42\ ))
--- \myVirtualToplevel|Add14~38\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add14~42\,
- sumout => \myVirtualToplevel|Add14~37_sumout\,
- cout => \myVirtualToplevel|Add14~38\);
-
--- Location: FF_X19_Y40_N37
-\myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~37_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK[12]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y40_N39
-\myVirtualToplevel|Add14~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~33_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~38\ ))
--- \myVirtualToplevel|Add14~34\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[13]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add14~38\,
- sumout => \myVirtualToplevel|Add14~33_sumout\,
- cout => \myVirtualToplevel|Add14~34\);
-
--- Location: FF_X19_Y40_N41
-\myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~33_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK[13]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y40_N42
-\myVirtualToplevel|Add14~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~29_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~34\ ))
--- \myVirtualToplevel|Add14~30\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[14]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add14~34\,
- sumout => \myVirtualToplevel|Add14~29_sumout\,
- cout => \myVirtualToplevel|Add14~30\);
-
--- Location: FF_X19_Y40_N43
-\myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~29_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK[14]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y40_N45
-\myVirtualToplevel|Add14~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~13_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(15) ) + ( GND ) + ( \myVirtualToplevel|Add14~30\ ))
--- \myVirtualToplevel|Add14~14\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK\(15) ) + ( GND ) + ( \myVirtualToplevel|Add14~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(15),
- cin => \myVirtualToplevel|Add14~30\,
- sumout => \myVirtualToplevel|Add14~13_sumout\,
- cout => \myVirtualToplevel|Add14~14\);
-
--- Location: FF_X19_Y40_N47
-\myVirtualToplevel|MILLISEC_DOWN_TICK[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~13_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(15));
-
--- Location: LABCELL_X19_Y40_N48
-\myVirtualToplevel|Add14~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~9_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~14\ ))
--- \myVirtualToplevel|Add14~10\ = CARRY(( \myVirtualToplevel|MILLISEC_DOWN_TICK[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[16]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add14~14\,
- sumout => \myVirtualToplevel|Add14~9_sumout\,
- cout => \myVirtualToplevel|Add14~10\);
-
--- Location: FF_X19_Y40_N49
-\myVirtualToplevel|MILLISEC_DOWN_TICK[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~9_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(16));
-
--- Location: FF_X19_Y40_N40
-\myVirtualToplevel|MILLISEC_DOWN_TICK[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~33_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(13));
-
--- Location: FF_X19_Y40_N38
-\myVirtualToplevel|MILLISEC_DOWN_TICK[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~37_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(12));
-
--- Location: FF_X19_Y40_N44
-\myVirtualToplevel|MILLISEC_DOWN_TICK[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~29_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(14));
-
--- Location: FF_X19_Y40_N53
-\myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~25_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y40_N51
-\myVirtualToplevel|Add14~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add14~25_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_DOWN_TICK[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add14~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK[17]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add14~10\,
- sumout => \myVirtualToplevel|Add14~25_sumout\);
-
--- Location: FF_X19_Y40_N52
-\myVirtualToplevel|MILLISEC_DOWN_TICK[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add14~25_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|Equal32~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_TICK\(17));
-
--- Location: MLABCELL_X18_Y40_N45
-\myVirtualToplevel|Equal32~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal32~0_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_TICK\(17) & ( (!\myVirtualToplevel|MILLISEC_DOWN_TICK\(13) & (!\myVirtualToplevel|MILLISEC_DOWN_TICK\(12) & !\myVirtualToplevel|MILLISEC_DOWN_TICK\(14))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(13),
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(12),
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(14),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(17),
- combout => \myVirtualToplevel|Equal32~0_combout\);
-
--- Location: MLABCELL_X18_Y40_N42
-\myVirtualToplevel|Equal32~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal32~1_combout\ = ( \myVirtualToplevel|MILLISEC_DOWN_TICK\(7) & ( (!\myVirtualToplevel|MILLISEC_DOWN_TICK\(11) & (\myVirtualToplevel|MILLISEC_DOWN_TICK\(10) & \myVirtualToplevel|MILLISEC_DOWN_TICK\(9))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000010100000000000001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(11),
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(10),
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(9),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(7),
- combout => \myVirtualToplevel|Equal32~1_combout\);
-
--- Location: MLABCELL_X18_Y40_N48
-\myVirtualToplevel|Equal32~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal32~2_combout\ = ( \myVirtualToplevel|Equal32~0_combout\ & ( \myVirtualToplevel|Equal32~1_combout\ & ( (\myVirtualToplevel|MILLISEC_DOWN_TICK\(16) & (!\myVirtualToplevel|MILLISEC_DOWN_TICK\(6) &
--- (\myVirtualToplevel|MILLISEC_DOWN_TICK\(15) & !\myVirtualToplevel|MILLISEC_DOWN_TICK\(8)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000010000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(16),
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(6),
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(15),
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(8),
- datae => \myVirtualToplevel|ALT_INV_Equal32~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal32~1_combout\,
- combout => \myVirtualToplevel|Equal32~2_combout\);
-
--- Location: LABCELL_X19_Y40_N57
-\myVirtualToplevel|Equal32~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal32~4_combout\ = ( !\myVirtualToplevel|MILLISEC_DOWN_TICK\(5) & ( (\myVirtualToplevel|Equal32~3_combout\ & (\myVirtualToplevel|MILLISEC_DOWN_TICK\(3) & \myVirtualToplevel|Equal32~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000101000000000000010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal32~3_combout\,
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(3),
- datad => \myVirtualToplevel|ALT_INV_Equal32~2_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_TICK\(5),
- combout => \myVirtualToplevel|Equal32~4_combout\);
-
--- Location: LABCELL_X16_Y12_N48
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\ = ( !\myVirtualToplevel|Equal32~4_combout\ & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5) ) ) # ( \myVirtualToplevel|Equal32~4_combout\ & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5) & (
--- (\myVirtualToplevel|Equal33~3_combout\ & (\myVirtualToplevel|Equal33~2_combout\ & !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(6))) ) ) ) # ( !\myVirtualToplevel|Equal32~4_combout\ & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(5) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111000000110000000011111111111111110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_Equal33~3_combout\,
- datac => \myVirtualToplevel|ALT_INV_Equal33~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(6),
- datae => \myVirtualToplevel|ALT_INV_Equal32~4_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(5),
- combout => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\);
-
--- Location: FF_X14_Y12_N7
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~61_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]~DUPLICATE_q\);
-
--- Location: FF_X14_Y12_N8
-\myVirtualToplevel|MILLISEC_DOWN_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add15~61_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MILLISEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MILLISEC_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(2));
-
--- Location: MLABCELL_X13_Y12_N54
-\myVirtualToplevel|IO_DATA_READ~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~73_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(2))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(2)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(2))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(2)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (
--- !\myVirtualToplevel|MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(2)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011010001110100011111001100111111110100011101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(2),
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(2),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|IO_DATA_READ~73_combout\);
-
--- Location: LABCELL_X14_Y11_N51
-\myVirtualToplevel|RTC_HOUR_COUNTER~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ = ( \myVirtualToplevel|TIMER0_CS~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001000000000000000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\,
- combout => \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\);
-
--- Location: LABCELL_X12_Y11_N15
-\myVirtualToplevel|RTC_MONTH_COUNTER~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER~1_combout\,
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\);
-
--- Location: LABCELL_X12_Y11_N45
-\myVirtualToplevel|RTC_MONTH_COUNTER[3]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\ ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\ & ( \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~5_combout\,
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\);
-
--- Location: FF_X9_Y11_N19
-\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MONTH_COUNTER~10_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\);
-
--- Location: LABCELL_X7_Y11_N54
-\myVirtualToplevel|RTC_MONTH_COUNTER~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER~7_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER\(2) & ( \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( ((!\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & !\myVirtualToplevel|RTC_MONTH_COUNTER\(3))) #
--- (\myVirtualToplevel|RTC_MONTH_COUNTER\(0)) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(2) & ( \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( (\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & !\myVirtualToplevel|RTC_MONTH_COUNTER\(0)) ) ) )
--- # ( \myVirtualToplevel|RTC_MONTH_COUNTER\(2) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(2) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\
--- & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010000010100001000111110001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3),
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- datae => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(2),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\,
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER~7_combout\);
-
--- Location: FF_X7_Y11_N56
-\myVirtualToplevel|RTC_MONTH_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MONTH_COUNTER~7_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MONTH_COUNTER\(2));
-
--- Location: MLABCELL_X9_Y11_N57
-\myVirtualToplevel|RTC_MONTH_COUNTER~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER~4_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ( \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER\(2)) # (\myVirtualToplevel|RTC_MONTH_COUNTER\(0)) ) ) ) # (
--- !\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ( \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & (\myVirtualToplevel|RTC_MONTH_COUNTER\(2) & \myVirtualToplevel|RTC_MONTH_COUNTER\(1))) ) ) ) # (
--- \myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000001000101101110111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0),
- datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3),
- datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(1),
- datae => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\,
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER~4_combout\);
-
--- Location: FF_X9_Y11_N58
-\myVirtualToplevel|RTC_MONTH_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MONTH_COUNTER~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MONTH_COUNTER\(3));
-
--- Location: MLABCELL_X9_Y11_N27
-\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ( \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\,
- combout => \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\);
-
--- Location: LABCELL_X7_Y11_N18
-\myVirtualToplevel|RTC_HOUR_COUNTER~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_HOUR_COUNTER~5_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(0) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111111111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- datad => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\,
- combout => \myVirtualToplevel|RTC_HOUR_COUNTER~5_combout\);
-
--- Location: LABCELL_X12_Y11_N30
-\myVirtualToplevel|RTC_HOUR_COUNTER[2]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ( \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (
--- \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ & ( \myVirtualToplevel|UART1|Equal7~0_combout\ ) ) ) # ( \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ( !\myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100110011001100111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER~1_combout\,
- combout => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\);
-
--- Location: FF_X7_Y11_N20
-\myVirtualToplevel|RTC_HOUR_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_HOUR_COUNTER~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_HOUR_COUNTER\(0));
-
--- Location: LABCELL_X7_Y11_N12
-\myVirtualToplevel|RTC_HOUR_COUNTER~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_HOUR_COUNTER~6_combout\ = ( \myVirtualToplevel|RTC_HOUR_COUNTER\(0) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) #
--- (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ((!\myVirtualToplevel|RTC_HOUR_COUNTER\(1)))) ) ) # ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(0) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ((\myVirtualToplevel|RTC_HOUR_COUNTER\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000111111000011000011111100111111000011000011111100001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1),
- datad => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(1),
- dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0),
- combout => \myVirtualToplevel|RTC_HOUR_COUNTER~6_combout\);
-
--- Location: FF_X7_Y11_N14
-\myVirtualToplevel|RTC_HOUR_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_HOUR_COUNTER~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_HOUR_COUNTER\(1));
-
--- Location: LABCELL_X7_Y11_N15
-\myVirtualToplevel|RTC_HOUR_COUNTER~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_HOUR_COUNTER~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\) # (!\myVirtualToplevel|RTC_HOUR_COUNTER\(2) $ (((!\myVirtualToplevel|RTC_HOUR_COUNTER\(0)) #
--- (!\myVirtualToplevel|RTC_HOUR_COUNTER\(1))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2) & ( (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (!\myVirtualToplevel|RTC_HOUR_COUNTER\(2) $ (((!\myVirtualToplevel|RTC_HOUR_COUNTER\(0)) #
--- (!\myVirtualToplevel|RTC_HOUR_COUNTER\(1)))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100110010000000010011001011001101111111101100110111111110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0),
- datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(1),
- datad => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- combout => \myVirtualToplevel|RTC_HOUR_COUNTER~4_combout\);
-
--- Location: FF_X7_Y11_N17
-\myVirtualToplevel|RTC_HOUR_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_HOUR_COUNTER~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_HOUR_COUNTER\(2));
-
--- Location: LABCELL_X7_Y11_N9
-\myVirtualToplevel|RTC_MONTH_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\ = ( \myVirtualToplevel|RTC_HOUR_COUNTER\(0) & ( (\myVirtualToplevel|RTC_HOUR_COUNTER\(2) & \myVirtualToplevel|RTC_HOUR_COUNTER\(1)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000011000000110000001100000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(2),
- datac => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(1),
- dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0),
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\);
-
--- Location: LABCELL_X7_Y11_N30
-\myVirtualToplevel|RTC_HOUR_COUNTER~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_HOUR_COUNTER~3_combout\ = ( \myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( \myVirtualToplevel|RTC_HOUR_COUNTER\(4) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) #
--- (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ((!\myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\))) ) ) ) # ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( \myVirtualToplevel|RTC_HOUR_COUNTER\(4) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & !\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\) ) ) ) # ( \myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(4) & (
--- (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ((!\myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\))) ) ) ) # (
--- !\myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(4) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ &
--- ((\myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001011111010111110101000001010000010100000101111101010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3),
- datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(3),
- dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(4),
- combout => \myVirtualToplevel|RTC_HOUR_COUNTER~3_combout\);
-
--- Location: FF_X7_Y11_N31
-\myVirtualToplevel|RTC_HOUR_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_HOUR_COUNTER~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_HOUR_COUNTER\(3));
-
--- Location: LABCELL_X7_Y11_N21
-\myVirtualToplevel|RTC_HOUR_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_HOUR_COUNTER~0_combout\ = ( \myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4))) #
--- (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & ((!\myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\ $ (!\myVirtualToplevel|RTC_HOUR_COUNTER\(4))))) ) ) # ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(3) & (
--- (!\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4))) # (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~5_combout\ & (((!\myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\ &
--- \myVirtualToplevel|RTC_HOUR_COUNTER\(4))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010001110100010001000111010001000111011101000100011101110100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4),
- datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~5_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(4),
- dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(3),
- combout => \myVirtualToplevel|RTC_HOUR_COUNTER~0_combout\);
-
--- Location: FF_X7_Y11_N22
-\myVirtualToplevel|RTC_HOUR_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_HOUR_COUNTER~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_HOUR_COUNTER[2]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_HOUR_COUNTER\(4));
-
--- Location: LABCELL_X7_Y11_N39
-\myVirtualToplevel|RTC_MONTH_COUNTER~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\ = ( !\myVirtualToplevel|RTC_HOUR_COUNTER\(3) & ( (\myVirtualToplevel|RTC_HOUR_COUNTER\(4) & \myVirtualToplevel|RTC_MONTH_COUNTER~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011000000110000001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(4),
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(3),
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\);
-
--- Location: MLABCELL_X9_Y11_N9
-\myVirtualToplevel|RTC_MONTH_COUNTER~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & ( (\myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\ & \myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~1_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\,
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\);
-
--- Location: FF_X5_Y11_N40
-\myVirtualToplevel|RTC_DAY_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_DAY_COUNTER~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_DAY_COUNTER\(0));
-
--- Location: LABCELL_X12_Y11_N39
-\myVirtualToplevel|RTC_DAY_COUNTER~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ = ( \myVirtualToplevel|RTC_HOUR_COUNTER~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER~1_combout\,
- combout => \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\);
-
--- Location: LABCELL_X5_Y11_N39
-\myVirtualToplevel|RTC_DAY_COUNTER~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_DAY_COUNTER~6_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER\(0) & ( \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)) ) ) ) # (
--- !\myVirtualToplevel|RTC_DAY_COUNTER\(0) & ( \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ &
--- (!\myVirtualToplevel|process_1~4_combout\)) ) ) ) # ( \myVirtualToplevel|RTC_DAY_COUNTER\(0) & ( !\myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ & ( !\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ ) ) ) # ( !\myVirtualToplevel|RTC_DAY_COUNTER\(0) & (
--- !\myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ & ( (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & !\myVirtualToplevel|process_1~4_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010001000100101010101010101011100100111001001010000010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\,
- datab => \myVirtualToplevel|ALT_INV_process_1~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- datae => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(0),
- dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~2_combout\,
- combout => \myVirtualToplevel|RTC_DAY_COUNTER~6_combout\);
-
--- Location: FF_X5_Y11_N41
-\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_DAY_COUNTER~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\);
-
--- Location: LABCELL_X10_Y11_N36
-\myVirtualToplevel|IO_DATA_READ[5]~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[5]~49_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|UART1|Mux0~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000010001000100010001000100010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[5]~DUPLICATE_q\,
- combout => \myVirtualToplevel|IO_DATA_READ[5]~49_combout\);
-
--- Location: LABCELL_X10_Y11_N42
-\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ = (!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|IO_DATA_READ[5]~49_combout\ & \myVirtualToplevel|MICROSEC_DOWN_COUNTER~1_combout\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110011111100001111001111110000111100111111000011110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[5]~49_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER~1_combout\,
- combout => \myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\);
-
--- Location: MLABCELL_X9_Y11_N12
-\myVirtualToplevel|RTC_YEAR_COUNTER[0]_NEW1628\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_YEAR_COUNTER[0]_OTERM1629\ = ( \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & ((\myVirtualToplevel|RTC_YEAR_COUNTER\(0)))) #
--- (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0))) ) ) # ( !\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & ( !\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ $
--- (!\myVirtualToplevel|RTC_YEAR_COUNTER\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010110101010010101011010101000000101101011110000010110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(0),
- dataf => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\,
- combout => \myVirtualToplevel|RTC_YEAR_COUNTER[0]_OTERM1629\);
-
--- Location: FF_X9_Y11_N13
-\myVirtualToplevel|RTC_YEAR_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_YEAR_COUNTER[0]_OTERM1629\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_YEAR_COUNTER\(0));
-
--- Location: LABCELL_X6_Y11_N0
-\myVirtualToplevel|Add11~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add11~42\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(0),
- cin => GND,
- cout => \myVirtualToplevel|Add11~42\);
-
--- Location: LABCELL_X6_Y11_N3
-\myVirtualToplevel|Add11~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add11~45_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add11~42\ ))
--- \myVirtualToplevel|Add11~46\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(1) ) + ( GND ) + ( \myVirtualToplevel|Add11~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(1),
- cin => \myVirtualToplevel|Add11~42\,
- sumout => \myVirtualToplevel|Add11~45_sumout\,
- cout => \myVirtualToplevel|Add11~46\);
-
--- Location: LABCELL_X6_Y11_N51
-\myVirtualToplevel|RTC_YEAR_COUNTER[1]_NEW1626\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_YEAR_COUNTER[1]_OTERM1627\ = ( \myVirtualToplevel|Add11~45_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(1))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ &
--- ((!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) ) ) # ( !\myVirtualToplevel|Add11~45_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ &
--- (((\myVirtualToplevel|RTC_YEAR_COUNTER\(1))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1),
- datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(1),
- dataf => \myVirtualToplevel|ALT_INV_Add11~45_sumout\,
- combout => \myVirtualToplevel|RTC_YEAR_COUNTER[1]_OTERM1627\);
-
--- Location: FF_X6_Y11_N52
-\myVirtualToplevel|RTC_YEAR_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_YEAR_COUNTER[1]_OTERM1627\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_YEAR_COUNTER\(1));
-
--- Location: LABCELL_X5_Y11_N48
-\myVirtualToplevel|RTC_DAY_COUNTER~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_DAY_COUNTER~8_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) #
--- (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (\myVirtualToplevel|process_1~5_combout\ & ((\myVirtualToplevel|RTC_DAY_COUNTER\(1))))) ) ) # ( !\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (\myVirtualToplevel|process_1~5_combout\ & ((!\myVirtualToplevel|RTC_DAY_COUNTER\(1))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001101100001010000110110000101000001010000110110000101000011011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\,
- datab => \myVirtualToplevel|ALT_INV_process_1~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1),
- datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1),
- dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|RTC_DAY_COUNTER~8_combout\);
-
--- Location: LABCELL_X5_Y11_N51
-\myVirtualToplevel|RTC_DAY_COUNTER[4]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ ) # ( !\myVirtualToplevel|RTC_DAY_COUNTER~2_combout\ & ( \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~2_combout\,
- combout => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\);
-
--- Location: FF_X5_Y11_N49
-\myVirtualToplevel|RTC_DAY_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_DAY_COUNTER~8_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_DAY_COUNTER\(1));
-
--- Location: LABCELL_X7_Y11_N6
-\myVirtualToplevel|process_1~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|process_1~2_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER\(1) & ( (\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & (!\myVirtualToplevel|RTC_YEAR_COUNTER\(1) & !\myVirtualToplevel|RTC_YEAR_COUNTER\(0))) ) ) # (
--- !\myVirtualToplevel|RTC_DAY_COUNTER\(1) & ( (!\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & ((\myVirtualToplevel|RTC_YEAR_COUNTER\(0)) # (\myVirtualToplevel|RTC_YEAR_COUNTER\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101010101010000010101010101001010000000000000101000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(1),
- datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(0),
- dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1),
- combout => \myVirtualToplevel|process_1~2_combout\);
-
--- Location: LABCELL_X5_Y11_N57
-\myVirtualToplevel|Add9~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add9~0_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER\(1) & ( !\myVirtualToplevel|RTC_DAY_COUNTER\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1),
- dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(0),
- combout => \myVirtualToplevel|Add9~0_combout\);
-
--- Location: FF_X7_Y11_N55
-\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MONTH_COUNTER~7_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\);
-
--- Location: LABCELL_X5_Y11_N0
-\myVirtualToplevel|process_1~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|process_1~3_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ((!\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ &
--- (\myVirtualToplevel|process_1~2_combout\)) # (\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ((\myVirtualToplevel|Add9~0_combout\))))) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( \myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|Add9~0_combout\ & (\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|Add9~0_combout\ & (!\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|Add9~0_combout\ & (\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000000000000000011000000000011000000000101000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_process_1~2_combout\,
- datab => \myVirtualToplevel|ALT_INV_Add9~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3),
- datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|process_1~3_combout\);
-
--- Location: FF_X5_Y11_N25
-\myVirtualToplevel|RTC_DAY_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_DAY_COUNTER~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_DAY_COUNTER\(4));
-
--- Location: FF_X5_Y11_N29
-\myVirtualToplevel|RTC_DAY_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_DAY_COUNTER~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_DAY_COUNTER\(2));
-
--- Location: LABCELL_X5_Y11_N27
-\myVirtualToplevel|RTC_DAY_COUNTER~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_DAY_COUNTER~5_combout\ = ( \myVirtualToplevel|process_1~5_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ &
--- (!\myVirtualToplevel|Add9~0_combout\ $ (((!\myVirtualToplevel|RTC_DAY_COUNTER\(2)))))) ) ) # ( !\myVirtualToplevel|process_1~5_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010000010100000101000011011010011100001101101001110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\,
- datab => \myVirtualToplevel|ALT_INV_Add9~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(2),
- dataf => \myVirtualToplevel|ALT_INV_process_1~5_combout\,
- combout => \myVirtualToplevel|RTC_DAY_COUNTER~5_combout\);
-
--- Location: FF_X5_Y11_N28
-\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_DAY_COUNTER~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\);
-
--- Location: LABCELL_X5_Y11_N30
-\myVirtualToplevel|RTC_DAY_COUNTER~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_DAY_COUNTER~4_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER\(3) & ( \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) #
--- (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (((\myVirtualToplevel|process_1~5_combout\ & !\myVirtualToplevel|Add9~0_combout\)))) ) ) ) # ( !\myVirtualToplevel|RTC_DAY_COUNTER\(3) & ( \myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (((\myVirtualToplevel|process_1~5_combout\ & \myVirtualToplevel|Add9~0_combout\)))) ) ) ) # (
--- \myVirtualToplevel|RTC_DAY_COUNTER\(3) & ( !\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ &
--- ((\myVirtualToplevel|process_1~5_combout\))) ) ) ) # ( !\myVirtualToplevel|RTC_DAY_COUNTER\(3) & ( !\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & !\myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\)
--- ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010000010100110101001101010000010100110101001101010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3),
- datab => \myVirtualToplevel|ALT_INV_process_1~5_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\,
- datad => \myVirtualToplevel|ALT_INV_Add9~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(3),
- dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|RTC_DAY_COUNTER~4_combout\);
-
--- Location: FF_X5_Y11_N32
-\myVirtualToplevel|RTC_DAY_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_DAY_COUNTER~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_DAY_COUNTER\(3));
-
--- Location: LABCELL_X5_Y11_N21
-\myVirtualToplevel|Add9~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add9~1_combout\ = ( \myVirtualToplevel|RTC_DAY_COUNTER\(3) & ( (\myVirtualToplevel|Add9~0_combout\ & \myVirtualToplevel|RTC_DAY_COUNTER\(2)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_Add9~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(2),
- dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(3),
- combout => \myVirtualToplevel|Add9~1_combout\);
-
--- Location: LABCELL_X5_Y11_N6
-\myVirtualToplevel|RTC_DAY_COUNTER~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_DAY_COUNTER~7_combout\ = ( \myVirtualToplevel|Add9~1_combout\ & ( (\myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ & (!\myVirtualToplevel|RTC_DAY_COUNTER\(4) $ (!\myVirtualToplevel|RTC_DAY_COUNTER\(5)))) ) ) # (
--- !\myVirtualToplevel|Add9~1_combout\ & ( (\myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ & \myVirtualToplevel|RTC_DAY_COUNTER\(5)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100000011000011000000001100001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(4),
- datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(5),
- dataf => \myVirtualToplevel|ALT_INV_Add9~1_combout\,
- combout => \myVirtualToplevel|RTC_DAY_COUNTER~7_combout\);
-
--- Location: FF_X5_Y11_N8
-\myVirtualToplevel|RTC_DAY_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_DAY_COUNTER~7_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_DAY_COUNTER\(5));
-
--- Location: LABCELL_X5_Y11_N9
-\myVirtualToplevel|process_1~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|process_1~4_combout\ = ( !\myVirtualToplevel|RTC_DAY_COUNTER\(5) & ( (\myVirtualToplevel|process_1~3_combout\ & (\myVirtualToplevel|RTC_DAY_COUNTER\(4) & (\myVirtualToplevel|RTC_DAY_COUNTER\(3) &
--- \myVirtualToplevel|RTC_DAY_COUNTER\(2)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001000000000000000100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_process_1~3_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(4),
- datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(3),
- datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(2),
- dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(5),
- combout => \myVirtualToplevel|process_1~4_combout\);
-
--- Location: LABCELL_X5_Y11_N42
-\myVirtualToplevel|process_1~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|process_1~5_combout\ = ( !\myVirtualToplevel|process_1~1_combout\ & ( !\myVirtualToplevel|process_1~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_process_1~4_combout\,
- dataf => \myVirtualToplevel|ALT_INV_process_1~1_combout\,
- combout => \myVirtualToplevel|process_1~5_combout\);
-
--- Location: LABCELL_X5_Y11_N18
-\myVirtualToplevel|RTC_DAY_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ = ( \myVirtualToplevel|process_1~5_combout\ & ( \myVirtualToplevel|RTC_MONTH_COUNTER~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~3_combout\,
- dataf => \myVirtualToplevel|ALT_INV_process_1~5_combout\,
- combout => \myVirtualToplevel|RTC_DAY_COUNTER~0_combout\);
-
--- Location: LABCELL_X5_Y11_N24
-\myVirtualToplevel|RTC_DAY_COUNTER~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_DAY_COUNTER~1_combout\ = ( \myVirtualToplevel|Add9~1_combout\ & ( (\myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ & !\myVirtualToplevel|RTC_DAY_COUNTER\(4)) ) ) # ( !\myVirtualToplevel|Add9~1_combout\ & (
--- (\myVirtualToplevel|RTC_DAY_COUNTER~0_combout\ & \myVirtualToplevel|RTC_DAY_COUNTER\(4)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100001111000000000000111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(4),
- dataf => \myVirtualToplevel|ALT_INV_Add9~1_combout\,
- combout => \myVirtualToplevel|RTC_DAY_COUNTER~1_combout\);
-
--- Location: FF_X5_Y11_N26
-\myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_DAY_COUNTER~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE_q\);
-
--- Location: FF_X5_Y11_N31
-\myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_DAY_COUNTER~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_DAY_COUNTER[4]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE_q\);
-
--- Location: LABCELL_X5_Y11_N45
-\myVirtualToplevel|process_1~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|process_1~0_combout\ = ( !\myVirtualToplevel|RTC_DAY_COUNTER[3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_DAY_COUNTER[4]~DUPLICATE_q\ & (!\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\ & !\myVirtualToplevel|RTC_DAY_COUNTER\(1))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(1),
- dataf => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[3]~DUPLICATE_q\,
- combout => \myVirtualToplevel|process_1~0_combout\);
-
--- Location: LABCELL_X5_Y11_N12
-\myVirtualToplevel|process_1~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|process_1~1_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|RTC_MONTH_COUNTER\(3) & (\myVirtualToplevel|process_1~0_combout\ &
--- (\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & \myVirtualToplevel|RTC_DAY_COUNTER\(5)))) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|process_1~0_combout\ &
--- (\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & \myVirtualToplevel|RTC_DAY_COUNTER\(5))) ) ) ) # ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( (\myVirtualToplevel|process_1~0_combout\ &
--- (\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & \myVirtualToplevel|RTC_DAY_COUNTER\(5))) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER\(3) &
--- (\myVirtualToplevel|process_1~0_combout\ & (\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\ & \myVirtualToplevel|RTC_DAY_COUNTER\(5)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000010000000000000001100000000000000110000000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3),
- datab => \myVirtualToplevel|ALT_INV_process_1~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(5),
- datae => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|process_1~1_combout\);
-
--- Location: MLABCELL_X9_Y11_N42
-\myVirtualToplevel|RTC_MONTH_COUNTER~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ = ( \myVirtualToplevel|process_1~4_combout\ & ( (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\)) )
--- ) # ( !\myVirtualToplevel|process_1~4_combout\ & ( (\myVirtualToplevel|process_1~1_combout\ & (\myVirtualToplevel|RTC_MINUTE_COUNTER~1_combout\ & (\myVirtualToplevel|RTC_MINUTE_COUNTER[3]~2_combout\ & \myVirtualToplevel|RTC_MONTH_COUNTER~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001000000000000000100000000000000110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_process_1~1_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[3]~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_process_1~4_combout\,
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\);
-
--- Location: LABCELL_X10_Y11_N57
-\myVirtualToplevel|RTC_MONTH_COUNTER~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER[1]~DUPLICATE_q\ & \myVirtualToplevel|RTC_MONTH_COUNTER\(3)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111100000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[1]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\);
-
--- Location: LABCELL_X12_Y11_N42
-\myVirtualToplevel|RTC_MONTH_COUNTER~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (!\myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\ & ((\myVirtualToplevel|RTC_MONTH_COUNTER\(0)))))
--- # (\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (((!\myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\ & !\myVirtualToplevel|RTC_MONTH_COUNTER\(0))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & (
--- (!\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (((\myVirtualToplevel|RTC_MONTH_COUNTER\(0))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~5_combout\))) # (\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ &
--- (((!\myVirtualToplevel|RTC_MONTH_COUNTER~8_combout\ & !\myVirtualToplevel|RTC_MONTH_COUNTER\(0))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0111001010101010011100101010101001010000100010000101000010001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~5_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~8_combout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER~9_combout\);
-
--- Location: FF_X12_Y11_N43
-\myVirtualToplevel|RTC_MONTH_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MONTH_COUNTER~9_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MONTH_COUNTER\(0));
-
--- Location: MLABCELL_X9_Y11_N18
-\myVirtualToplevel|RTC_MONTH_COUNTER~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_MONTH_COUNTER~10_combout\ = ( \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & ( (!\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1))))) #
--- (\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\ & (!\myVirtualToplevel|RTC_MONTH_COUNTER\(0) $ (((\myVirtualToplevel|RTC_MONTH_COUNTER\(1)))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000101110000111010010111000011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0),
- datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1),
- datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(1),
- dataf => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\,
- combout => \myVirtualToplevel|RTC_MONTH_COUNTER~10_combout\);
-
--- Location: FF_X9_Y11_N20
-\myVirtualToplevel|RTC_MONTH_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_MONTH_COUNTER~10_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|RTC_MONTH_COUNTER[3]~6_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_MONTH_COUNTER\(1));
-
--- Location: MLABCELL_X9_Y11_N6
-\myVirtualToplevel|RTC_YEAR_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER\(3) & ( ((!\myVirtualToplevel|RTC_MONTH_COUNTER~2_combout\) # ((!\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\) # (\myVirtualToplevel|RTC_MONTH_COUNTER\(0)))) #
--- (\myVirtualToplevel|RTC_MONTH_COUNTER\(1)) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(3) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111110111111111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(1),
- datab => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0),
- datad => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(3),
- combout => \myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\);
-
--- Location: LABCELL_X6_Y11_N6
-\myVirtualToplevel|Add11~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add11~37_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add11~46\ ))
--- \myVirtualToplevel|Add11~38\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(2) ) + ( GND ) + ( \myVirtualToplevel|Add11~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(2),
- cin => \myVirtualToplevel|Add11~46\,
- sumout => \myVirtualToplevel|Add11~37_sumout\,
- cout => \myVirtualToplevel|Add11~38\);
-
--- Location: LABCELL_X7_Y11_N0
-\myVirtualToplevel|RTC_YEAR_COUNTER[2]_NEW1754\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_YEAR_COUNTER[2]_OTERM1755\ = ( \myVirtualToplevel|Add11~37_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(2))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ &
--- ((!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2))))) ) ) # ( !\myVirtualToplevel|Add11~37_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ &
--- (((\myVirtualToplevel|RTC_YEAR_COUNTER\(2))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(2),
- dataf => \myVirtualToplevel|ALT_INV_Add11~37_sumout\,
- combout => \myVirtualToplevel|RTC_YEAR_COUNTER[2]_OTERM1755\);
-
--- Location: FF_X7_Y11_N2
-\myVirtualToplevel|RTC_YEAR_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_YEAR_COUNTER[2]_OTERM1755\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_YEAR_COUNTER\(2));
-
--- Location: LABCELL_X7_Y11_N48
-\myVirtualToplevel|IO_DATA_READ~72\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~72_combout\ = ( \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- ((\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_YEAR_COUNTER\(2))) ) ) ) # ( !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_DAY_COUNTER[2]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_YEAR_COUNTER\(2))) ) ) ) # (
--- \myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) # (\myVirtualToplevel|RTC_HOUR_COUNTER\(2)) ) ) ) # (
--- !\myVirtualToplevel|RTC_MONTH_COUNTER[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (\myVirtualToplevel|RTC_HOUR_COUNTER\(2) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001111110011111100000101111101010000010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(2),
- datab => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[2]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- combout => \myVirtualToplevel|IO_DATA_READ~72_combout\);
-
--- Location: LABCELL_X10_Y10_N51
-\myVirtualToplevel|IO_DATA_READ~75\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~75_combout\ = ( \myVirtualToplevel|IO_DATA_READ~72_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((\myVirtualToplevel|IO_DATA_READ~73_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (\myVirtualToplevel|IO_DATA_READ~74_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))) ) ) # (
--- !\myVirtualToplevel|IO_DATA_READ~72_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((\myVirtualToplevel|IO_DATA_READ~73_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) &
--- (\myVirtualToplevel|IO_DATA_READ~74_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001010001010000000101000101000010011100110110001001110011011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~74_combout\,
- datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~73_combout\,
- dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~72_combout\,
- combout => \myVirtualToplevel|IO_DATA_READ~75_combout\);
-
--- Location: LABCELL_X12_Y7_N33
-\myVirtualToplevel|UART1|Add9~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~29_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( \myVirtualToplevel|UART1_CS~combout\ ) ) # ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( !\myVirtualToplevel|UART1_CS~combout\ & (
--- \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) ) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2),
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add9~29_combout\);
-
--- Location: LABCELL_X14_Y7_N0
-\myVirtualToplevel|UART1|Add9~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~34_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add9~34_combout\);
-
--- Location: LABCELL_X12_Y7_N3
-\myVirtualToplevel|UART1|Add9~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~39_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( \myVirtualToplevel|UART1_CS~combout\ ) ) # ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( !\myVirtualToplevel|UART1_CS~combout\ & (
--- \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\,
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add9~39_combout\);
-
--- Location: MLABCELL_X13_Y7_N0
-\myVirtualToplevel|UART1|Add9~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~42_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- cin => GND,
- cout => \myVirtualToplevel|UART1|Add9~42_cout\);
-
--- Location: MLABCELL_X13_Y7_N3
-\myVirtualToplevel|UART1|Add9~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~36_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~39_combout\ ) + ( (!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|IO_SELECT~combout\ &
--- ((!\myVirtualToplevel|Equal4~0_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|Equal4~0_combout\ & ((!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\))))) ) + ( \myVirtualToplevel|UART1|Add9~42_cout\ ))
--- \myVirtualToplevel|UART1|Add9~37\ = CARRY(( \myVirtualToplevel|UART1|Add9~39_combout\ ) + ( (!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|IO_SELECT~combout\ &
--- ((!\myVirtualToplevel|Equal4~0_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0))) # (\myVirtualToplevel|Equal4~0_combout\ & ((!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\))))) ) + ( \myVirtualToplevel|UART1|Add9~42_cout\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101001100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0),
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Add9~39_combout\,
- dataf => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- cin => \myVirtualToplevel|UART1|Add9~42_cout\,
- sumout => \myVirtualToplevel|UART1|Add9~36_sumout\,
- cout => \myVirtualToplevel|UART1|Add9~37\);
-
--- Location: MLABCELL_X13_Y7_N6
-\myVirtualToplevel|UART1|Add9~31\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~31_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~34_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1))))) ) + ( \myVirtualToplevel|UART1|Add9~37\ ))
--- \myVirtualToplevel|UART1|Add9~32\ = CARRY(( \myVirtualToplevel|UART1|Add9~34_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1))))) ) + ( \myVirtualToplevel|UART1|Add9~37\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000011110111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add9~34_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1),
- cin => \myVirtualToplevel|UART1|Add9~37\,
- sumout => \myVirtualToplevel|UART1|Add9~31_sumout\,
- cout => \myVirtualToplevel|UART1|Add9~32\);
-
--- Location: MLABCELL_X13_Y7_N9
-\myVirtualToplevel|UART1|Add9~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~21_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~29_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2))))) ) + ( \myVirtualToplevel|UART1|Add9~32\ ))
--- \myVirtualToplevel|UART1|Add9~22\ = CARRY(( \myVirtualToplevel|UART1|Add9~29_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2))))) ) + ( \myVirtualToplevel|UART1|Add9~32\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000011110111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add9~29_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2),
- cin => \myVirtualToplevel|UART1|Add9~32\,
- sumout => \myVirtualToplevel|UART1|Add9~21_sumout\,
- cout => \myVirtualToplevel|UART1|Add9~22\);
-
--- Location: FF_X14_Y6_N55
-\myVirtualToplevel|UART1|RX_FIFO~20\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_BUFFER\(3),
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO~20_q\);
-
--- Location: LABCELL_X14_Y6_N24
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder_combout\ = \myVirtualToplevel|UART1|RX_BUFFER\(3)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(3),
- combout => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder_combout\);
-
--- Location: FF_X14_Y6_N25
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[19]~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(19));
-
--- Location: LABCELL_X14_Y6_N54
-\myVirtualToplevel|UART1|RX_DATA~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA~14_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(3) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) # (\myVirtualToplevel|UART1|RX_FIFO~20_q\) ) ) ) # (
--- !\myVirtualToplevel|UART1|RX_BUFFER\(3) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & \myVirtualToplevel|UART1|RX_FIFO~20_q\) ) ) ) # ( \myVirtualToplevel|UART1|RX_BUFFER\(3) & (
--- !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(19)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ &
--- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a2\)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_BUFFER\(3) & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ &
--- ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(19)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a2\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010110101111000001011010111100010001000100011011101110111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~20_q\,
- datac => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a2\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(19),
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(3),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\,
- combout => \myVirtualToplevel|UART1|RX_DATA~14_combout\);
-
--- Location: LABCELL_X16_Y6_N0
-\myVirtualToplevel|UART1|RX_DATA[2]~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA[2]~15_combout\ = ( \myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & ((\myVirtualToplevel|UART1|RX_DATA\(2)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ &
--- (\myVirtualToplevel|UART1|RX_DATA~14_combout\)) ) ) # ( !\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ & ( \myVirtualToplevel|UART1|RX_DATA\(2) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000011111100110000001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~14_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(2),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\,
- combout => \myVirtualToplevel|UART1|RX_DATA[2]~15_combout\);
-
--- Location: FF_X16_Y6_N1
-\myVirtualToplevel|UART1|RX_DATA[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_DATA[2]~15_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_DATA\(2));
-
--- Location: LABCELL_X14_Y9_N48
-\myVirtualToplevel|IO_DATA_READ~76\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~76_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|RX_DATA\(2)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_DATA_READY~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000000000000000110101001101010000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|IO_DATA_READ~76_combout\);
-
--- Location: LABCELL_X14_Y9_N54
-\myVirtualToplevel|IO_DATA_READ~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~77_combout\ = ( \myVirtualToplevel|UART1|Add9~21_sumout\ & ( \myVirtualToplevel|IO_DATA_READ~76_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (((\myVirtualToplevel|IO_DATA_READ~75_combout\) #
--- (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\)))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (((!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(2)))) ) ) ) # ( !\myVirtualToplevel|UART1|Add9~21_sumout\ & (
--- \myVirtualToplevel|IO_DATA_READ~76_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (((\myVirtualToplevel|IO_DATA_READ~75_combout\) # (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\)))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ &
--- (\myVirtualToplevel|UART0|RX_DATA\(2) & (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\))) ) ) ) # ( \myVirtualToplevel|UART1|Add9~21_sumout\ & ( !\myVirtualToplevel|IO_DATA_READ~76_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ &
--- (((!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & \myVirtualToplevel|IO_DATA_READ~75_combout\)))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (((!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(2)))) ) ) )
--- # ( !\myVirtualToplevel|UART1|Add9~21_sumout\ & ( !\myVirtualToplevel|IO_DATA_READ~76_combout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (((!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & \myVirtualToplevel|IO_DATA_READ~75_combout\)))) #
--- (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(2) & (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000110100001010100011111000100001011101010110101101111111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~70_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(2),
- datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\,
- datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~75_combout\,
- datae => \myVirtualToplevel|UART1|ALT_INV_Add9~21_sumout\,
- dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~76_combout\,
- combout => \myVirtualToplevel|IO_DATA_READ~77_combout\);
-
--- Location: LABCELL_X16_Y10_N57
-\myVirtualToplevel|IO_DATA_READ[0]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[0]~5_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|RESET_n~q\ ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|RESET_n~q\ & ((\myVirtualToplevel|UART0_CS~combout\) #
--- (\myVirtualToplevel|TIMER0_CS~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001011111000000001111111100000000010111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_UART0_CS~combout\,
- datad => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- datae => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\);
-
--- Location: FF_X14_Y9_N55
-\myVirtualToplevel|IO_DATA_READ[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ~77_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ\(2));
-
--- Location: FF_X17_Y14_N25
-\myVirtualToplevel|INT_ENABLE[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|INT_ENABLE\(2));
-
--- Location: FF_X17_Y14_N44
-\myVirtualToplevel|IO_DATA_READ_INTRCTL[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|INT_ENABLE\(2),
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- sload => VCC,
- ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(2));
-
--- Location: LABCELL_X16_Y14_N33
-\myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ = ( \myVirtualToplevel|IO_SELECT~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(11)) # (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|IO_SELECT~2_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111111100001111111111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(11),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\);
-
--- Location: LABCELL_X17_Y14_N0
-\myVirtualToplevel|MEM_DATA_READ[2]~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~22_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ & ( \myVirtualToplevel|IO_SELECT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) $ (!\myVirtualToplevel|LessThan0~0_combout\) ) )
--- ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ & ( \myVirtualToplevel|IO_SELECT~1_combout\ & ( (!\myVirtualToplevel|IO_SELECT~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) $ ((!\myVirtualToplevel|LessThan0~0_combout\))))
--- # (\myVirtualToplevel|IO_SELECT~0_combout\ & (!\myVirtualToplevel|SD_CS~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) $ (!\myVirtualToplevel|LessThan0~0_combout\)))) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ & (
--- !\myVirtualToplevel|IO_SELECT~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) $ (!\myVirtualToplevel|LessThan0~0_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~22_RESYN12616_BDD12617\ & ( !\myVirtualToplevel|IO_SELECT~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(23) $ (!\myVirtualToplevel|LessThan0~0_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101101001011010010110100101101001011010010010000101101001011010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(23),
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_SD_CS~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_RESYN12616_BDD12617\,
- dataf => \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~22_combout\);
-
--- Location: LABCELL_X17_Y14_N21
-\myVirtualToplevel|MEM_DATA_READ[2]~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ = ( \myVirtualToplevel|INTR0_CS~combout\ & ( (\myVirtualToplevel|SD_CS~combout\ & ((!\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\) # ((\myVirtualToplevel|IO_SELECT~combout\ &
--- !\myVirtualToplevel|SOCCFG_CS~combout\)))) ) ) # ( !\myVirtualToplevel|INTR0_CS~combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~22_combout\) # ((\myVirtualToplevel|IO_SELECT~combout\ & !\myVirtualToplevel|SOCCFG_CS~combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100110000111111110011000001010101000100000101010100010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_SD_CS~combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~22_combout\,
- dataf => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\);
-
--- Location: LABCELL_X17_Y14_N42
-\myVirtualToplevel|MEM_DATA_READ[2]~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(2) & ( \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(2))) #
--- (\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & ((\myVirtualToplevel|IO_DATA_READ\(2)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(2) & ( \myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ &
--- (\myVirtualToplevel|IO_DATA_READ_SD\(2))) # (\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\ & ((\myVirtualToplevel|IO_DATA_READ\(2)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(2) & ( !\myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & (
--- (!\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\) # (!\myVirtualToplevel|SOCCFG_CS~combout\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(2) & ( !\myVirtualToplevel|MEM_DATA_READ[2]~35_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[2]~34_combout\
--- & !\myVirtualToplevel|SOCCFG_CS~combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100000000111111111100110001000111010001110100011101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(2),
- datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~34_combout\,
- datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(2),
- datad => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\,
- datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(2),
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~35_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\);
-
--- Location: FF_X14_Y15_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]_OTERM3338\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[13]~DUPLICATE_q\);
-
--- Location: M10K_X22_Y15_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110101010000000000001151E6CB3128578D4C211C31904064C575010AE570AD6B5AD790C9934050000FD524A3A16728E452361345D88A2185520054000555555577005290E50231042092200210B42B100811C1A9A040A142063E0536CCF0C672AB572979AAECA4117675DD01C259661039757AE2F25AA9",
- mem_init2 => "004803C9013403C996925323881744253A38AC3496AC0ECCD1A000900F920270929526F450128E438904A64D43BBE07D39A4994C4938D0F6A0016C58AB74CA7F92C06A5D50B24146A95920D251F053EB49E92E27E1B29D06092D88D49790D2CD31C314530D04100CC16E3B4889462F2E0894CD665ECAB4C94F67C689E20A930C5099292CEA8BC193C8CCAA214D3B0C4D3B0615C10E242A58A2021025B944788758B1B361E94362BA2C19694B32FE22D93E5723DC08F9844878C6424294C7A6B497E0F50C337480709614B12C85692D1024FC85C81430E1818231AF23ADB0150AC32DA84B57730CE36469481C65CAF1EC208F4AA156E19DCC802B35F5D3AC710E",
- mem_init1 => "5AE806C59E38593E160277C0A20FC416B9D05378E1427083C411C63DC1AC30CC2EC37E813D42623D1ADAF2A276365919F6419729808683BBEBA49AB2D8E344F315D45193065F0824AA8168B4298AE7A929F14E516482048F89F419573EFD6A37856E73A00DD36BE23BC90C9C12778C17577F848459F0018BC8E348CAE20B61A3989A95C11F33E038A6A8C3E40863765BDF8D345DA816D284E8810005010304A5E9F342C3C9A94F559F5580978BB029E493D20499BDC015315A27D343B10D0903062ED00D91A74CBB3B8880C26978D7980B1067655E2011DFFA3CFE154A2B55AC861C14EEBC81F13A1A2FBBCD25C29034765A7E4517709C1DA6D343909812C61E",
- mem_init0 => "D1E401225B361008058DAB4C9B14040047AAE9600136A3F075582A2150E43E076B3E8841304C0832E94380CBD0C067C8A8F0E0BA3393D15791961C41084F3B43B040283C4BF9D1A02BAD96330D3B4E683808A09265A00A805000000000082DD108000209004241A0084824144251289463A583640422485800D734C3208A9ED69B3660F9F067195D3000340010C2DB5C1018F34C2D934D02958DDC16FA35C893E3B8D5E7D3E04281F5DF9AF7FC303C3EBBF0172A98A36A00BB5B76B77777777777777777777777776E96DDADAB5B76B6FFFFFFFFFFFC924925B6DB6DB6DB6DFEFD000000000001243C060206040700010D050409050200000022001D30040C00",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 2,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 2,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2_PORTBDATAOUT_bus\);
-
--- Location: FF_X18_Y14_N23
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_NEW_REG30\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM31\);
-
--- Location: MLABCELL_X18_Y14_N24
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM31\) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM33\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]_OTERM31\ & ((!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM3~DUPLICATE_q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111010000000001111101000000101111111110000010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM3~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM31\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]_OTERM33\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\);
-
--- Location: MLABCELL_X18_Y14_N57
-\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ & ( ((\myVirtualToplevel|LessThan0~1_combout\ &
--- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\))) # (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0) &
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110000000000000011000001010101011101010101010101110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\,
- datab => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\,
- datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b\(0),
- datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]~25_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\);
-
--- Location: MLABCELL_X18_Y14_N18
-\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ & (
--- \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ ) ) # ( \myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ & (
--- ((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\))) #
--- (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~36_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\ & (
--- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000010001000011110001111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\,
- datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b\(0),
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\,
- datad => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~36_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_RESYN12806_BDD12807\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\);
-
--- Location: LABCELL_X10_Y15_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_OTERM3214\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux85~2_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[2]~38_Duplicate_155\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101000000011100000100111101111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux85~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[2]_NEW3213_RESYN13450_BDD13451\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~38_Duplicate_155\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_OTERM3214\);
-
--- Location: FF_X10_Y15_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[2]_OTERM3214\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2));
-
--- Location: LABCELL_X10_Y17_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ = ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|cpuBusy~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|MEM_BUSY~1_combout\ &
--- (\myVirtualToplevel|RESET_n~q\ & (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|process_1~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan4~2_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000001000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_BUSY~1_combout\,
- datab => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_process_1~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan4~2_combout\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_cpuBusy~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\);
-
--- Location: LABCELL_X10_Y17_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_NEW3210\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_OTERM3211\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[3]~99_Duplicate_158\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101000111010001110100011101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[3]~99_Duplicate_158\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_OTERM3211\);
-
--- Location: FF_X10_Y17_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[3]_OTERM3211\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3));
-
--- Location: MLABCELL_X9_Y16_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_NEW3222\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_OTERM3223\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ &
--- ((\myVirtualToplevel|MEM_DATA_READ[4]~131_Duplicate_173\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001010010111110000101001011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[4]~131_Duplicate_173\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_OTERM3223\);
-
--- Location: FF_X9_Y16_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]_OTERM3223\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4));
-
--- Location: MLABCELL_X9_Y18_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_NEW3207\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_OTERM3208\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux82~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ &
--- ((\myVirtualToplevel|MEM_DATA_READ[5]~127_Duplicate_167\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001100001111110000110000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux82~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[5]~127_Duplicate_167\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_OTERM3208\);
-
--- Location: FF_X9_Y18_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[5]_OTERM3208\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5));
-
--- Location: LABCELL_X7_Y17_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_NEW3204\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_OTERM3205\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux81~2_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[6]~111_Duplicate_170\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101000111010001110100011101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux81~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[6]~111_Duplicate_170\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(6),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_OTERM3205\);
-
--- Location: FF_X7_Y17_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[6]_OTERM3205\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6));
-
--- Location: MLABCELL_X9_Y16_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_NEW3201\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_OTERM3202\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux80~2_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\ & ((\myVirtualToplevel|MEM_DATA_READ[7]~107_Duplicate_164\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[4]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux80~2_combout\,
- datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[7]~107_Duplicate_164\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_OpcodeFetch~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[4]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_OTERM3202\);
-
--- Location: FF_X9_Y16_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[7]_OTERM3202\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7));
-
--- Location: M10K_X3_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init4 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- clk0_core_clock_enable => "ena0",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram0_evo_L2cache_a612c956.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|evo_L2cache:CACHEL2|altsyncram:RAM0_rtl_0|altsyncram_bnn1:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "dont_care",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 10,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 10,
- port_a_first_address => 0,
- port_a_first_bit_number => 0,
- port_a_last_address => 1023,
- port_a_logical_ram_depth => 1024,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock1",
- port_b_address_width => 10,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 10,
- port_b_first_address => 0,
- port_b_first_bit_number => 0,
- port_b_last_address => 1023,
- port_b_logical_ram_depth => 1024,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock1",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0_combout\,
- portbre => VCC,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- clk1 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- ena0 => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_WREN~0_combout\,
- portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);
-
--- Location: MLABCELL_X28_Y35_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001110111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374_combout\);
-
--- Location: FF_X28_Y35_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~374_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\);
-
--- Location: LABCELL_X12_Y16_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[9]~123_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[9]~123_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder_combout\);
-
--- Location: FF_X12_Y16_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1308\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309\);
-
--- Location: FF_X7_Y16_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1312\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux96~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1313\);
-
--- Location: FF_X7_Y16_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1314\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\);
-
--- Location: FF_X7_Y16_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_NEW_REG1310\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_OpcodeFetch~q\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\);
-
--- Location: LABCELL_X7_Y16_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1309\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1313\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1315\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1313\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000011111111111100111100000000000100011111111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1309\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1313\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1315\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\);
-
--- Location: MLABCELL_X9_Y18_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000000000000000011111111001100111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]~19_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[1]~5_combout\);
-
--- Location: LABCELL_X14_Y14_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[10]~119_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~119_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder_combout\);
-
--- Location: FF_X14_Y14_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1316\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317\);
-
--- Location: FF_X9_Y16_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1318\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux95~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1319\);
-
--- Location: FF_X7_Y16_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_NEW_REG1320\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\);
-
--- Location: LABCELL_X7_Y16_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1317\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1319\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1321\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]_OTERM1319\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000011111111111111001100000000000001011111111111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1317\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1319\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]_OTERM1321\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\);
-
--- Location: LABCELL_X7_Y16_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[10]~17_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000000000000000011110101111101011111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(2),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[10]~17_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[2]~4_combout\);
-
--- Location: FF_X14_Y14_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1322\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[11]~115_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1323\);
-
--- Location: FF_X6_Y18_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1324\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux94~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1325\);
-
--- Location: FF_X6_Y18_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_NEW_REG1326\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\);
-
--- Location: LABCELL_X6_Y18_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1325\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1323\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1325\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1323\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]_OTERM1327\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001010001011010101111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1323\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1325\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]_OTERM1327\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\);
-
--- Location: LABCELL_X7_Y18_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[11]~15_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000000100000001000000010011110111111101111111011111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(3),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[11]~15_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[3]~3_combout\);
-
--- Location: LABCELL_X10_Y16_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[12]~147_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[12]~147_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder_combout\);
-
--- Location: FF_X10_Y16_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1352\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353\);
-
--- Location: FF_X9_Y20_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1354\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux93~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1355\);
-
--- Location: FF_X6_Y18_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_NEW_REG1356\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\);
-
--- Location: LABCELL_X6_Y18_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1355\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1355\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1353\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]_OTERM1357\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000011000001011111001111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1353\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1355\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]_OTERM1357\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\);
-
--- Location: LABCELL_X7_Y18_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7_combout\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[12]~5_combout\)))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010010111111000001001011111100000100101111110000010010111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[12]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[4]~7_combout\);
-
--- Location: FF_X9_Y20_N22
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1342\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux92~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1343\);
-
--- Location: FF_X7_Y18_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1340\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[13]~143_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1341\);
-
--- Location: FF_X6_Y18_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_NEW_REG1344\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\);
-
--- Location: LABCELL_X6_Y18_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1343\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1341\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1343\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1341\))))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]_OTERM1345\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000101000000111111010111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1343\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1341\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]_OTERM1345\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\);
-
--- Location: LABCELL_X6_Y18_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[13]~9_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001100000000000000110011110011111111111111001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(5),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[13]~9_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[5]~1_combout\);
-
--- Location: FF_X18_Y16_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1346\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[14]~139_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1347\);
-
--- Location: FF_X6_Y18_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1348\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux91~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1349\);
-
--- Location: FF_X6_Y18_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_NEW_REG1350\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\);
-
--- Location: LABCELL_X6_Y18_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1349\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1347\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1349\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1347\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]_OTERM1351\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000101000100011010111110111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1347\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1349\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]_OTERM1351\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\);
-
--- Location: LABCELL_X7_Y18_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[14]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000100000000000100010010111011111111111011101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(6),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[14]~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[6]~0_combout\);
-
--- Location: FF_X17_Y16_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1334\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[15]~135_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1335\);
-
--- Location: FF_X7_Y16_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1336\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Mux90~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1337\);
-
--- Location: FF_X7_Y16_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_NEW_REG1338\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\);
-
--- Location: LABCELL_X7_Y16_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1335\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1335\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1337\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1339\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]_OTERM1311\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[24]_OTERM752\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]_OTERM1337\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000011111111111100111100000000000100011111111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1335\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[24]_OTERM752\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1337\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]_OTERM1339\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]_OTERM1311\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\);
-
--- Location: LABCELL_X7_Y18_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[15]~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000100000000000100010010111011111111111011101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[15]~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_DATA[7]~6_combout\);
-
--- Location: M10K_X22_Y38_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init4 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- clk0_core_clock_enable => "ena0",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram1_evo_L2cache_a612c956.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|evo_L2cache:CACHEL2|altsyncram:RAM1_rtl_0|altsyncram_cnn1:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "dont_care",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 10,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 10,
- port_a_first_address => 0,
- port_a_first_bit_number => 0,
- port_a_last_address => 1023,
- port_a_logical_ram_depth => 1024,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock1",
- port_b_address_width => 10,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 10,
- port_b_first_address => 0,
- port_b_first_bit_number => 0,
- port_b_last_address => 1023,
- port_b_logical_ram_depth => 1024,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock1",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0_combout\,
- portbre => VCC,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- clk1 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- ena0 => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_WREN~0_combout\,
- portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);
-
--- Location: LABCELL_X26_Y35_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375_combout\);
-
--- Location: FF_X26_Y35_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~375_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\);
-
--- Location: LABCELL_X26_Y35_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][6]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][6]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][6]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\);
-
--- Location: LABCELL_X29_Y25_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\);
-
--- Location: LABCELL_X26_Y35_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373_combout\);
-
--- Location: FF_X26_Y35_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~373_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\);
-
--- Location: FF_X26_Y35_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\);
-
--- Location: LABCELL_X26_Y35_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111101111111100000001000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372_combout\);
-
--- Location: FF_X26_Y35_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~372_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y36_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][6]~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\);
-
--- Location: LABCELL_X29_Y25_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010100000101000001010000010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\);
-
--- Location: FF_X29_Y35_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\);
-
--- Location: LABCELL_X29_Y35_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111101111111100000001000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377_combout\);
-
--- Location: FF_X29_Y35_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~377_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\);
-
--- Location: FF_X26_Y35_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\);
-
--- Location: LABCELL_X26_Y35_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001111111111111110100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376_combout\);
-
--- Location: FF_X26_Y35_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~376_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\);
-
--- Location: LABCELL_X29_Y35_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][6]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011001100000000001100110000110011111111110011001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][6]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\);
-
--- Location: LABCELL_X32_Y28_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[3]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111100000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\);
-
--- Location: LABCELL_X32_Y29_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379_combout\);
-
--- Location: FF_X32_Y29_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~379_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\);
-
--- Location: LABCELL_X25_Y34_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001111111111111101100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378_combout\);
-
--- Location: FF_X25_Y34_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~378_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\);
-
--- Location: LABCELL_X32_Y36_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][6]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][6]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][6]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\);
-
--- Location: LABCELL_X26_Y36_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~5_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~6_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001010001010010001101100111000010011100110110101011111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~5_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~9_combout\);
-
--- Location: LABCELL_X25_Y35_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001111111111111101100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389_combout\);
-
--- Location: FF_X25_Y35_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~389_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\);
-
--- Location: MLABCELL_X28_Y35_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000001001111111111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388_combout\);
-
--- Location: FF_X28_Y35_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~388_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\);
-
--- Location: LABCELL_X24_Y35_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][6]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][6]~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][6]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][6]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\);
-
--- Location: LABCELL_X29_Y25_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[4]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1FetchIdx\(3)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1FetchIdx[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\);
-
--- Location: LABCELL_X26_Y35_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\
--- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111110100000000000000101111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393_combout\);
-
--- Location: FF_X26_Y35_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~393_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\);
-
--- Location: LABCELL_X26_Y35_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\
--- & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111110100000000000000101111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392_combout\);
-
--- Location: FF_X26_Y35_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~392_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\);
-
--- Location: LABCELL_X26_Y35_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][6]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000001111000011111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][6]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\);
-
--- Location: LABCELL_X29_Y35_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391_combout\);
-
--- Location: FF_X29_Y35_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~391_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\);
-
--- Location: LABCELL_X20_Y33_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001111111111111101100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390_combout\);
-
--- Location: FF_X20_Y33_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~390_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\);
-
--- Location: LABCELL_X26_Y36_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111110000000000000000111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][6]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\);
-
--- Location: MLABCELL_X28_Y35_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a6\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000001001111111111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394_combout\);
-
--- Location: FF_X28_Y35_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~394_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\);
-
--- Location: MLABCELL_X28_Y30_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a6\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a6\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395_combout\);
-
--- Location: FF_X28_Y30_N34
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~395_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\);
-
--- Location: LABCELL_X21_Y35_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][6]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][6]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111111110000111100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][6]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\);
-
--- Location: LABCELL_X26_Y36_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\)
--- ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~17_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~18_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~15_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~16_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010100001111001100110000000001010101000011110011001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~15_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~17_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~18_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~19_combout\);
-
--- Location: FF_X28_Y35_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~382_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][6]~q\);
-
--- Location: MLABCELL_X13_Y14_N48
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001111000010100000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\);
-
--- Location: MLABCELL_X23_Y14_N54
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node[1]\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1) = ( \myVirtualToplevel|BRAM_WREN~1_combout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & \myVirtualToplevel|LessThan3~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001000100010001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\,
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM2_WREN~0_combout\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1));
-
--- Location: MLABCELL_X23_Y14_N24
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\ = ( \myVirtualToplevel|BRAM_WREN~1_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) & ((!\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\) #
--- (!\myVirtualToplevel|LessThan3~0_combout\)))) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\) ) ) # ( !\myVirtualToplevel|BRAM_WREN~1_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100001111111011110000111111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\,
- datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM2_WREN~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16),
- dataf => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\);
-
--- Location: LABCELL_X20_Y11_N15
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\);
-
--- Location: LABCELL_X20_Y11_N27
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ & ( (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[1]~5_combout\);
-
--- Location: M10K_X30_Y10_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 1,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 1,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9_PORTBDATAOUT_bus\);
-
--- Location: MLABCELL_X23_Y14_N18
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node[0]\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0) = ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & ( (\myVirtualToplevel|BRAM_WREN~1_combout\
--- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & \myVirtualToplevel|LessThan3~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110001000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16),
- datad => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\,
- datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM2_WREN~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0));
-
--- Location: M10K_X38_Y14_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020220000002200000200200010029CD263F98326811812002008A88E01040414CA48421094F8005113000039BD582A64B42A41915E0803E3BA65C12181300001E00000062010D1EF815B28C5180020A00000305B321A02D20428D02362C3A4000000D612E2B1AC201385000CE3B829443C8D0A4EA82413408019",
- mem_init2 => "380600A47C02E4C0ACC0E140C43915AA950C0562070552CA01D9700B9208F803808307AA6414240907184181248888931444502A205448A144B686050400919C1419C60D874D56AA83A6AB551DD062749EA80066118A077F34332B0424869C06A0A55C00000000921E0410314DFECBB7374A3172E4AC2E49F7F686D8FA97191689DC5D3E7C70ADE208AA08E513C60913C6653F073553390456B3204CF89E71F1C3962C0DAAC10D9C7C100237430C82A00D6A2E1B62CADE8C953E16548342B940C104D092758953015CC3A068E24F4EC0D61B0050A4FC314E24900E2466510A41435B7BA00201F13A0C008C0D716E1102A41A421608531847CE63900F0011B594",
- mem_init1 => "543370ED6B131707C8083292E55010E9528000C7D88C5E8269A06A480CAA4164362666A69A6472A110BA3491580B042C8063016B4C800B17A4D313DA39669360AB5E808AF7409C85922F955EC048431DDA9701D28AA40024231008587993C278130CFCACBC0EC6846F493CAE0A5C826AEA1129A7E11E556880640D345245C42B4101825826750071E82F2B249851725043BC56980E9231120E968081E0A01D188508B010E4801301C17CC1A8AB84183760E0481D83DABC1598EF124121144E6862124310CFA042524805100010000037445F81F25232A2D11E1D3516322B3B0387A816DADA68650E18706C858384C8C201D4417E31E71540520C298A258B7885",
- mem_init0 => "4646420A9082C010A25A51844168005E18653EE960C25D86200A81000A11034819E29470AF0D859C1F8A09049D1640B4F7A514C2E0A2408052650A5841F04334A11B090D32562749A65089120088D0CA13C40B24C70703BD779F3E7CF9F3C48B08086610867CC210CF9842384261309864C77E4120950D77BA1418121065B19021A1981FF5242AA44AAAB49255460212CCD0B9012C902DE8024C0BF500002228000500111000A028400AA00140450108015140608C63A4000036002AAEEAEAEAEEEEEAAAEEAAEEEEC005801A00340068FFFFFFFFFFF924924DB6DB69249249FEF80000000000015024040416120601000000321B05030100032303147E1A0001",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 1,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 1,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1_PORTBDATAOUT_bus\);
-
--- Location: FF_X21_Y12_N38
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0));
-
--- Location: LABCELL_X14_Y14_N42
-\myVirtualToplevel|MEM_DATA_READ[17]~66\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[17]~66_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & (
--- (!\myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ & ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\) # (!\myVirtualToplevel|LessThan0~1_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ &
--- ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a9~portbdataout\) # (!\myVirtualToplevel|LessThan0~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & (
--- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & ( (!\myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ & !\myVirtualToplevel|LessThan0~1_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a1~portbdataout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & ( !\myVirtualToplevel|MEM_DATA_READ[17]~26_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100000000000011110000101000001111000010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a9~portbdataout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[17]~26_combout\,
- datad => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\,
- datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a1~portbdataout\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0),
- combout => \myVirtualToplevel|MEM_DATA_READ[17]~66_combout\);
-
--- Location: FF_X14_Y14_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG602\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|MEM_DATA_READ[17]~66_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM603\);
-
--- Location: FF_X9_Y18_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG598\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]~24_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM599\);
-
--- Location: FF_X9_Y18_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG594\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM595\);
-
--- Location: FF_X9_Y18_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_NEW_REG596\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Mux25~2_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[17]_OTERM597\);
-
--- Location: MLABCELL_X18_Y14_N54
-\myVirtualToplevel|MEM_DATA_READ[30]~20\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[30]~20_combout\ = ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( !\myVirtualToplevel|INTR0_CS~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\,
- dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[30]~20_combout\);
-
--- Location: MLABCELL_X18_Y14_N0
-\myVirtualToplevel|MEM_DATA_READ[27]~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[27]~21_combout\ = ( \myVirtualToplevel|LessThan0~0_combout\ & ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & \myVirtualToplevel|SD_CS~combout\) ) ) ) # (
--- !\myVirtualToplevel|LessThan0~0_combout\ & ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ & \myVirtualToplevel|SD_CS~combout\) ) ) ) # ( !\myVirtualToplevel|LessThan0~0_combout\ & ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\ &
--- (((!\myVirtualToplevel|IO_SELECT~combout\) # (\myVirtualToplevel|SD_CS~combout\)) # (\myVirtualToplevel|INTR0_CS~combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000101010101000000001010101001010101010101010000000010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\,
- datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datad => \myVirtualToplevel|ALT_INV_SD_CS~combout\,
- datae => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[27]~21_combout\);
-
--- Location: MLABCELL_X18_Y14_N36
-\myVirtualToplevel|MEM_DATA_READ[17]~23\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[17]~23_combout\ = ( \myVirtualToplevel|SD_CS~combout\ & ( !\myVirtualToplevel|LessThan0~0_combout\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\) ) ) # ( !\myVirtualToplevel|SD_CS~combout\ & (
--- (\myVirtualToplevel|LessThan0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001100000011000000111100001111000011110000111100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_LessThan0~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_SD_CS~combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[17]~23_combout\);
-
--- Location: FF_X13_Y11_N22
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~21_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(17));
-
--- Location: FF_X16_Y10_N35
-\myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1073\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(17),
- sload => VCC,
- ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ[17]_OTERM1074\);
-
--- Location: LABCELL_X16_Y10_N36
-\myVirtualToplevel|IO_DATA_READ[17]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[17]~2_combout\ = ( \myVirtualToplevel|Equal3~0_combout\ & ( (\myVirtualToplevel|TIMER0_CS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) $ (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000101000010100000010100001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ALT_INV_Equal3~0_combout\,
- combout => \myVirtualToplevel|IO_DATA_READ[17]~2_combout\);
-
--- Location: FF_X16_Y10_N37
-\myVirtualToplevel|IO_DATA_READ[17]_NEW_REG1079\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ[17]~2_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ[17]_OTERM1080\);
-
--- Location: LABCELL_X16_Y10_N9
-\myVirtualToplevel|IO_DATA_READ[17]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[17]~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( ((\myVirtualToplevel|TIMER0_CS~1_combout\ & !\myVirtualToplevel|Equal3~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( ((!\myVirtualToplevel|TIMER0_CS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & (!\myVirtualToplevel|Equal3~0_combout\))) #
--- (\myVirtualToplevel|UART1_CS~combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1110010011111111111001001111111101001111010011110100111101001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\,
- datab => \myVirtualToplevel|ALT_INV_Equal3~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- combout => \myVirtualToplevel|IO_DATA_READ[17]~1_combout\);
-
--- Location: LABCELL_X16_Y10_N6
-\myVirtualToplevel|IO_DATA_READ[17]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[17]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( ((\myVirtualToplevel|TIMER0_CS~1_combout\ & !\myVirtualToplevel|Equal3~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|UART1_CS~combout\) # ((!\myVirtualToplevel|TIMER0_CS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ &
--- (!\myVirtualToplevel|Equal3~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111100100111111111110010001001111010011110100111101001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\,
- datab => \myVirtualToplevel|ALT_INV_Equal3~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- combout => \myVirtualToplevel|IO_DATA_READ[17]~0_combout\);
-
--- Location: LABCELL_X14_Y8_N36
-\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1_combout\ = !\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0),
- combout => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1_combout\);
-
--- Location: MLABCELL_X13_Y10_N48
-\myVirtualToplevel|UART1|TX_RESET~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_RESET~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( \myVirtualToplevel|UART1_CS~combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( !\myVirtualToplevel|UART1_CS~combout\ )
--- ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( !\myVirtualToplevel|UART1_CS~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111111111111111100011111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|TX_RESET~0_combout\);
-
--- Location: FF_X13_Y10_N50
-\myVirtualToplevel|UART1|TX_RESET\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|TX_RESET~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_RESET~q\);
-
--- Location: LABCELL_X14_Y7_N24
-\myVirtualToplevel|UART1|TX_ENABLE~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_ENABLE~1_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\,
- combout => \myVirtualToplevel|UART1|TX_ENABLE~1_combout\);
-
--- Location: FF_X14_Y7_N26
-\myVirtualToplevel|UART1|TX_ENABLE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|TX_ENABLE~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_ENABLE~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_ENABLE~q\);
-
--- Location: MLABCELL_X13_Y9_N51
-\myVirtualToplevel|UART1|TX_OVERRUN~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_OVERRUN~0_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|UART1|TX_ENABLE~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & \myVirtualToplevel|UART1|Equal7~0_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011000000000000001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Equal7~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|TX_OVERRUN~0_combout\);
-
--- Location: LABCELL_X14_Y7_N27
-\myVirtualToplevel|UART1|TX_ENABLE_FIFO~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_ENABLE_FIFO~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\,
- combout => \myVirtualToplevel|UART1|TX_ENABLE_FIFO~0_combout\);
-
--- Location: FF_X14_Y7_N28
-\myVirtualToplevel|UART1|TX_ENABLE_FIFO\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|TX_ENABLE_FIFO~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_ENABLE~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\);
-
--- Location: MLABCELL_X13_Y9_N0
-\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\ = ( !\myVirtualToplevel|UART1|Equal6~4_combout\ & ( (\myVirtualToplevel|UART1|TX_OVERRUN~0_combout\ & !\myVirtualToplevel|UART1|TX_ENABLE_FIFO~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_OVERRUN~0_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE_FIFO~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Equal6~4_combout\,
- combout => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\);
-
--- Location: FF_X14_Y8_N38
-\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~1_combout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0));
-
--- Location: LABCELL_X14_Y8_N0
-\myVirtualToplevel|UART1|Add7~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add7~1_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) ) + ( !VCC ))
--- \myVirtualToplevel|UART1|Add7~2\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0),
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(1),
- cin => GND,
- sumout => \myVirtualToplevel|UART1|Add7~1_sumout\,
- cout => \myVirtualToplevel|UART1|Add7~2\);
-
--- Location: FF_X14_Y8_N1
-\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add7~1_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1));
-
--- Location: LABCELL_X14_Y8_N3
-\myVirtualToplevel|UART1|Add7~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add7~21_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~2\ ))
--- \myVirtualToplevel|UART1|Add7~22\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(2),
- cin => \myVirtualToplevel|UART1|Add7~2\,
- sumout => \myVirtualToplevel|UART1|Add7~21_sumout\,
- cout => \myVirtualToplevel|UART1|Add7~22\);
-
--- Location: FF_X14_Y8_N5
-\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add7~21_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2));
-
--- Location: LABCELL_X14_Y8_N6
-\myVirtualToplevel|UART1|Add7~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add7~13_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~22\ ))
--- \myVirtualToplevel|UART1|Add7~14\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(3),
- cin => \myVirtualToplevel|UART1|Add7~22\,
- sumout => \myVirtualToplevel|UART1|Add7~13_sumout\,
- cout => \myVirtualToplevel|UART1|Add7~14\);
-
--- Location: FF_X14_Y8_N7
-\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add7~13_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3));
-
--- Location: LABCELL_X14_Y8_N9
-\myVirtualToplevel|UART1|Add7~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add7~25_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~14\ ))
--- \myVirtualToplevel|UART1|Add7~26\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(4),
- cin => \myVirtualToplevel|UART1|Add7~14\,
- sumout => \myVirtualToplevel|UART1|Add7~25_sumout\,
- cout => \myVirtualToplevel|UART1|Add7~26\);
-
--- Location: FF_X14_Y8_N11
-\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add7~25_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4));
-
--- Location: LABCELL_X14_Y8_N12
-\myVirtualToplevel|UART1|Add7~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add7~17_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~26\ ))
--- \myVirtualToplevel|UART1|Add7~18\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(5),
- cin => \myVirtualToplevel|UART1|Add7~26\,
- sumout => \myVirtualToplevel|UART1|Add7~17_sumout\,
- cout => \myVirtualToplevel|UART1|Add7~18\);
-
--- Location: FF_X14_Y8_N14
-\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add7~17_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5));
-
--- Location: LABCELL_X14_Y8_N15
-\myVirtualToplevel|UART1|Add7~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add7~5_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~18\ ))
--- \myVirtualToplevel|UART1|Add7~6\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(6),
- cin => \myVirtualToplevel|UART1|Add7~18\,
- sumout => \myVirtualToplevel|UART1|Add7~5_sumout\,
- cout => \myVirtualToplevel|UART1|Add7~6\);
-
--- Location: FF_X14_Y8_N16
-\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add7~5_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6));
-
--- Location: MLABCELL_X13_Y8_N24
-\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1_combout\ = ( !\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111000000000000000011111111111111110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(0),
- combout => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1_combout\);
-
--- Location: FF_X13_Y8_N25
-\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1_combout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0));
-
--- Location: FF_X13_Y8_N26
-\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~1_combout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y8_N30
-\myVirtualToplevel|UART1|Add8~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add8~1_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1) ) + ( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( !VCC ))
--- \myVirtualToplevel|UART1|Add8~2\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1) ) + ( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~DUPLICATE_q\ ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(1),
- cin => GND,
- sumout => \myVirtualToplevel|UART1|Add8~1_sumout\,
- cout => \myVirtualToplevel|UART1|Add8~2\);
-
--- Location: FF_X13_Y8_N31
-\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add8~1_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1));
-
--- Location: LABCELL_X14_Y8_N45
-\myVirtualToplevel|UART1|Equal5~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal5~0_combout\ = ( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0)))) ) ) # (
--- !\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1001100100000000100110010000000000000000100110010000000010011001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0),
- datab => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(0),
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(1),
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(1),
- combout => \myVirtualToplevel|UART1|Equal5~0_combout\);
-
--- Location: MLABCELL_X13_Y8_N33
-\myVirtualToplevel|UART1|Add8~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add8~21_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~2\ ))
--- \myVirtualToplevel|UART1|Add8~22\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(2),
- cin => \myVirtualToplevel|UART1|Add8~2\,
- sumout => \myVirtualToplevel|UART1|Add8~21_sumout\,
- cout => \myVirtualToplevel|UART1|Add8~22\);
-
--- Location: FF_X13_Y8_N34
-\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add8~21_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2));
-
--- Location: MLABCELL_X13_Y8_N36
-\myVirtualToplevel|UART1|Add8~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add8~13_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~22\ ))
--- \myVirtualToplevel|UART1|Add8~14\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(3),
- cin => \myVirtualToplevel|UART1|Add8~22\,
- sumout => \myVirtualToplevel|UART1|Add8~13_sumout\,
- cout => \myVirtualToplevel|UART1|Add8~14\);
-
--- Location: FF_X13_Y8_N37
-\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add8~13_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3));
-
--- Location: MLABCELL_X13_Y8_N39
-\myVirtualToplevel|UART1|Add8~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add8~25_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~14\ ))
--- \myVirtualToplevel|UART1|Add8~26\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(4),
- cin => \myVirtualToplevel|UART1|Add8~14\,
- sumout => \myVirtualToplevel|UART1|Add8~25_sumout\,
- cout => \myVirtualToplevel|UART1|Add8~26\);
-
--- Location: FF_X13_Y8_N40
-\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add8~25_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4));
-
--- Location: LABCELL_X14_Y8_N57
-\myVirtualToplevel|UART1|Equal5~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal5~3_combout\ = ( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4) & ( (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2)))) ) ) # (
--- !\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4) & ( (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000001010000101000000101000000001010000001010000101000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(2),
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(4),
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(2),
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(4),
- combout => \myVirtualToplevel|UART1|Equal5~3_combout\);
-
--- Location: LABCELL_X14_Y8_N18
-\myVirtualToplevel|UART1|Add7~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add7~9_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add7~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(7),
- cin => \myVirtualToplevel|UART1|Add7~6\,
- sumout => \myVirtualToplevel|UART1|Add7~9_sumout\);
-
--- Location: FF_X14_Y8_N19
-\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add7~9_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7));
-
--- Location: MLABCELL_X13_Y8_N42
-\myVirtualToplevel|UART1|Add8~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add8~17_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~26\ ))
--- \myVirtualToplevel|UART1|Add8~18\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(5),
- cin => \myVirtualToplevel|UART1|Add8~26\,
- sumout => \myVirtualToplevel|UART1|Add8~17_sumout\,
- cout => \myVirtualToplevel|UART1|Add8~18\);
-
--- Location: FF_X13_Y8_N43
-\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add8~17_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5));
-
--- Location: MLABCELL_X13_Y8_N45
-\myVirtualToplevel|UART1|Add8~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add8~5_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~18\ ))
--- \myVirtualToplevel|UART1|Add8~6\ = CARRY(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(6),
- cin => \myVirtualToplevel|UART1|Add8~18\,
- sumout => \myVirtualToplevel|UART1|Add8~5_sumout\,
- cout => \myVirtualToplevel|UART1|Add8~6\);
-
--- Location: MLABCELL_X13_Y8_N48
-\myVirtualToplevel|UART1|Add8~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add8~9_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART1|Add8~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(7),
- cin => \myVirtualToplevel|UART1|Add8~6\,
- sumout => \myVirtualToplevel|UART1|Add8~9_sumout\);
-
--- Location: FF_X13_Y8_N49
-\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add8~9_sumout\,
- clrn => \myVirtualToplevel|UART1|TX_RESET~q\,
- ena => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7));
-
--- Location: LABCELL_X16_Y8_N18
-\myVirtualToplevel|UART1|Equal5~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal5~1_combout\ = ( \myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6) & ( (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7)))) ) ) # (
--- !\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6) & ( (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100001100000000110000110000000000000000110000110000000011000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(7),
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(7),
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(6),
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(6),
- combout => \myVirtualToplevel|UART1|Equal5~1_combout\);
-
--- Location: LABCELL_X14_Y8_N24
-\myVirtualToplevel|UART1|Equal5~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal5~2_combout\ = ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) & ( (\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5) & (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3) $ (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3)))) ) ) # (
--- !\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) & ( (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5) & (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3) $ (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010010100000000101001010000000000000000101001010000000010100101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(3),
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(3),
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(5),
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(5),
- combout => \myVirtualToplevel|UART1|Equal5~2_combout\);
-
--- Location: LABCELL_X14_Y8_N27
-\myVirtualToplevel|UART1|Equal5~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Equal5~4_combout\ = ( \myVirtualToplevel|UART1|Equal5~2_combout\ & ( (\myVirtualToplevel|UART1|Equal5~0_combout\ & (\myVirtualToplevel|UART1|Equal5~3_combout\ & \myVirtualToplevel|UART1|Equal5~1_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_Equal5~0_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Equal5~3_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Equal5~1_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Equal5~2_combout\,
- combout => \myVirtualToplevel|UART1|Equal5~4_combout\);
-
--- Location: LABCELL_X12_Y7_N57
-\myVirtualToplevel|UART1|TX_BUFFER[16]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_BUFFER[16]~9_combout\ = !\myVirtualToplevel|UART1|TX_STATE~q\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\,
- combout => \myVirtualToplevel|UART1|TX_BUFFER[16]~9_combout\);
-
--- Location: MLABCELL_X9_Y13_N0
-\myVirtualToplevel|UART1|Add0~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add0~61_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|UART1|Add0~62\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(0),
- cin => GND,
- sumout => \myVirtualToplevel|UART1|Add0~61_sumout\,
- cout => \myVirtualToplevel|UART1|Add0~62\);
-
--- Location: LABCELL_X14_Y7_N12
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100110011001100110011001100110011001100110011001100110011001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\,
- combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6_combout\);
-
--- Location: FF_X14_Y7_N14
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(0));
-
--- Location: LABCELL_X14_Y7_N15
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(0) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(0),
- combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell_combout\);
-
--- Location: MLABCELL_X13_Y9_N39
-\myVirtualToplevel|UART1|TX_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_COUNTER~0_combout\ = ( \myVirtualToplevel|UART1|Equal0~4_combout\ ) # ( !\myVirtualToplevel|UART1|Equal0~4_combout\ & ( !\myVirtualToplevel|UART1|TX_STATE~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_STATE~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Equal0~4_combout\,
- combout => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\);
-
--- Location: FF_X9_Y13_N2
-\myVirtualToplevel|UART1|TX_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add0~61_sumout\,
- asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[0]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_COUNTER\(0));
-
--- Location: MLABCELL_X9_Y13_N3
-\myVirtualToplevel|UART1|Add0~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add0~49_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~62\ ))
--- \myVirtualToplevel|UART1|Add0~50\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(1),
- cin => \myVirtualToplevel|UART1|Add0~62\,
- sumout => \myVirtualToplevel|UART1|Add0~49_sumout\,
- cout => \myVirtualToplevel|UART1|Add0~50\);
-
--- Location: FF_X10_Y13_N13
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(1));
-
--- Location: FF_X9_Y13_N5
-\myVirtualToplevel|UART1|TX_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add0~49_sumout\,
- asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(1),
- sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_COUNTER\(1));
-
--- Location: MLABCELL_X9_Y13_N6
-\myVirtualToplevel|UART1|Add0~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add0~53_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~50\ ))
--- \myVirtualToplevel|UART1|Add0~54\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(2),
- cin => \myVirtualToplevel|UART1|Add0~50\,
- sumout => \myVirtualToplevel|UART1|Add0~53_sumout\,
- cout => \myVirtualToplevel|UART1|Add0~54\);
-
--- Location: LABCELL_X10_Y13_N33
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\,
- combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5_combout\);
-
--- Location: FF_X10_Y13_N35
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(2));
-
--- Location: LABCELL_X10_Y13_N42
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell_combout\ = !\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(2)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(2),
- combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell_combout\);
-
--- Location: FF_X9_Y13_N8
-\myVirtualToplevel|UART1|TX_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add0~53_sumout\,
- asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[2]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_COUNTER\(2));
-
--- Location: MLABCELL_X9_Y13_N9
-\myVirtualToplevel|UART1|Add0~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add0~37_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~54\ ))
--- \myVirtualToplevel|UART1|Add0~38\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(3),
- cin => \myVirtualToplevel|UART1|Add0~54\,
- sumout => \myVirtualToplevel|UART1|Add0~37_sumout\,
- cout => \myVirtualToplevel|UART1|Add0~38\);
-
--- Location: FF_X12_Y18_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_NEW_REG905\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\);
-
--- Location: LABCELL_X7_Y20_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_NEW2773\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_OTERM2774\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(19) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011011000110110001101100011011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_OTERM2774\);
-
--- Location: FF_X7_Y20_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[19]_OTERM2774\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(19));
-
--- Location: LABCELL_X7_Y20_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_NEW2901\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_OTERM2902\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000101000000111111010111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_OTERM2902\);
-
--- Location: FF_X7_Y20_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[19]_OTERM2902\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19));
-
--- Location: LABCELL_X7_Y20_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_NEW2837\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_OTERM2838\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101010011010100110101001101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_OTERM2838\);
-
--- Location: FF_X7_Y20_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[19]_OTERM2838\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19));
-
--- Location: LABCELL_X7_Y20_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_NEW2709\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_OTERM2710\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000010100111111111101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_OTERM2710\);
-
--- Location: FF_X7_Y20_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[19]_OTERM2710\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19));
-
--- Location: LABCELL_X7_Y20_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(19))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(19)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(19))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(19) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(19) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001111110011111100000101111101010000010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(19),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(19),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(19),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\);
-
--- Location: LABCELL_X7_Y25_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_NEW3157\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_OTERM3158\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(19) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_OTERM3158\);
-
--- Location: FF_X7_Y25_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[19]_OTERM3158\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(19));
-
--- Location: LABCELL_X7_Y25_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_NEW3029\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_OTERM3030\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(19) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_OTERM3030\);
-
--- Location: FF_X7_Y25_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[19]_OTERM3030\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(19));
-
--- Location: LABCELL_X7_Y25_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_NEW2965\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_OTERM2966\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000001101011111111100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_OTERM2966\);
-
--- Location: FF_X7_Y25_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[19]_OTERM2966\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19));
-
--- Location: LABCELL_X7_Y25_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_NEW3093\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_OTERM3094\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(19))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\)))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(19))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_OTERM3094\);
-
--- Location: FF_X7_Y25_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[19]_OTERM3094\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(19));
-
--- Location: LABCELL_X7_Y25_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(19) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(19) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(19) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(19) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101000000001111111100110011001100110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(19),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(19),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(19),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(19),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\);
-
--- Location: LABCELL_X7_Y20_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\);
-
--- Location: LABCELL_X12_Y18_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000000000011001111110000111100111111000011110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\);
-
--- Location: LABCELL_X12_Y18_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\) ) ) ) # (
--- !\myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[19]~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux84~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Selector15~0_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000001010011101110000101000100010010111110111011101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector15~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux84~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0_combout\);
-
--- Location: FF_X12_Y18_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_NEW_REG907\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector273~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\);
-
--- Location: LABCELL_X12_Y18_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM906\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]_OTERM908\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101011111010111101010000010100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM906\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]_OTERM908\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\);
-
--- Location: LABCELL_X10_Y13_N6
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\,
- combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4_combout\);
-
--- Location: FF_X10_Y13_N8
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(3));
-
--- Location: LABCELL_X10_Y13_N9
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell_combout\ = ( !\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(3) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(3),
- combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell_combout\);
-
--- Location: FF_X9_Y13_N11
-\myVirtualToplevel|UART1|TX_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add0~37_sumout\,
- asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[3]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_COUNTER\(3));
-
--- Location: MLABCELL_X9_Y13_N12
-\myVirtualToplevel|UART1|Add0~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add0~33_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~38\ ))
--- \myVirtualToplevel|UART1|Add0~34\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(4),
- cin => \myVirtualToplevel|UART1|Add0~38\,
- sumout => \myVirtualToplevel|UART1|Add0~33_sumout\,
- cout => \myVirtualToplevel|UART1|Add0~34\);
-
--- Location: FF_X10_Y15_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_NEW_REG909\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\);
-
--- Location: FF_X19_Y17_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20));
-
--- Location: FF_X19_Y17_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(20));
-
--- Location: LABCELL_X19_Y17_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(20) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(20)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010101010000000001010101001010101111111110101010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(20),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\);
-
--- Location: LABCELL_X6_Y23_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_NEW3027\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_OTERM3028\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001111001100110000111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_OTERM3028\);
-
--- Location: FF_X6_Y23_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[20]_OTERM3028\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20));
-
--- Location: LABCELL_X6_Y23_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_NEW2963\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_OTERM2964\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000001101011111111100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_OTERM2964\);
-
--- Location: FF_X6_Y23_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[20]_OTERM2964\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20));
-
--- Location: LABCELL_X6_Y23_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_NEW3155\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_OTERM3156\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100100111001001110010011100100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_OTERM3156\);
-
--- Location: FF_X6_Y23_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[20]_OTERM3156\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20));
-
--- Location: LABCELL_X6_Y23_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_NEW3091\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_OTERM3092\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100100111001001110010011100100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_OTERM3092\);
-
--- Location: FF_X6_Y23_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[20]_OTERM3092\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20));
-
--- Location: LABCELL_X6_Y23_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20) &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(20) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(20) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(20))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(20)))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010011111100000101001100001111010100111111111101010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(20),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(20),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(20),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\);
-
--- Location: MLABCELL_X9_Y21_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_NEW2835\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_OTERM2836\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(20) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011011000110110001101100011011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_OTERM2836\);
-
--- Location: FF_X9_Y21_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[20]_OTERM2836\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(20));
-
--- Location: MLABCELL_X9_Y21_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_NEW2707\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_OTERM2708\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000001001111111111100100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_OTERM2708\);
-
--- Location: FF_X9_Y21_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[20]_OTERM2708\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20));
-
--- Location: MLABCELL_X9_Y21_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_NEW2771\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_OTERM2772\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(20) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011011000110110001101100011011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_OTERM2772\);
-
--- Location: FF_X9_Y21_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[20]_OTERM2772\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(20));
-
--- Location: MLABCELL_X9_Y21_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_NEW2899\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_OTERM2900\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000010000001111111001011110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_OTERM2900\);
-
--- Location: FF_X9_Y21_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[20]_OTERM2900\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20));
-
--- Location: MLABCELL_X9_Y21_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(20) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(20) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(20) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(20) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111001100110011001101010101010101010000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(20),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(20),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(20),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(20),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\);
-
--- Location: MLABCELL_X13_Y19_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~0_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\);
-
--- Location: LABCELL_X10_Y15_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector215~0_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux10~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010111110000111100001111010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector215~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux10~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\);
-
--- Location: LABCELL_X10_Y15_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\))) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) ) ) ) # ( \myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\))) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[20]~16_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector14~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux83~2_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000010001001111110001000100001100110111010011111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux83~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~16_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector14~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0_combout\);
-
--- Location: FF_X10_Y15_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_NEW_REG911\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector272~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\);
-
--- Location: LABCELL_X10_Y15_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM910\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]_OTERM912\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]_OTERM786\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101011111010111101010000010100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteAddr[2]_OTERM505~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]_OTERM786\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM910\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]_OTERM912\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\);
-
--- Location: LABCELL_X10_Y13_N0
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\,
- combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3_combout\);
-
--- Location: FF_X10_Y13_N2
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[6]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(4));
-
--- Location: LABCELL_X10_Y13_N3
-\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell_combout\ = !\myVirtualToplevel|UART1|TX_CLOCK_DIVISOR\(4)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_TX_CLOCK_DIVISOR\(4),
- combout => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell_combout\);
-
--- Location: FF_X9_Y13_N14
-\myVirtualToplevel|UART1|TX_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Add0~33_sumout\,
- asdata => \myVirtualToplevel|UART1|TX_CLOCK_DIVISOR[4]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART1|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|TX_COUNTER\(4));
-
--- Location: MLABCELL_X9_Y13_N15
-\myVirtualToplevel|UART1|Add0~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add0~29_sumout\ = SUM(( \myVirtualToplevel|UART1|TX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~34\ ))
--- \myVirtualToplevel|UART1|Add0~30\ = CARRY(( \myVirtualToplevel|UART1|TX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add0~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_COUNTER\(5),
- cin => \myVirtualToplevel|UART1|Add0~34\,
- sumout => \myVirtualToplevel|UART1|Add0~29_sumout\,
- cout => \myVirtualToplevel|UART1|Add0~30\);
-
--- Location: FF_X10_Y18_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_NEW_REG917\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]_OTERM918\);
-
--- Location: FF_X19_Y14_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~5_sumout\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[25]~0_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_ReadAddToTOS~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(21));
-
--- Location: LABCELL_X19_Y18_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder_combout\);
-
--- Location: FF_X19_Y18_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[4]~feeder_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(4));
-
--- Location: M10K_X30_Y13_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 4,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 4,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(1),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a12_PORTBDATAOUT_bus\);
-
--- Location: LABCELL_X21_Y13_N42
-\myVirtualToplevel|Mux92~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux92~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- combout => \myVirtualToplevel|Mux92~0_combout\);
-
--- Location: LABCELL_X21_Y13_N36
-\myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder_combout\ = ( \myVirtualToplevel|Mux92~0_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Mux92~0_combout\,
- combout => \myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder_combout\);
-
--- Location: FF_X21_Y13_N38
-\myVirtualToplevel|IO_DATA_READ_SOCCFG[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ_SOCCFG[4]~feeder_combout\,
- ena => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(4));
-
--- Location: FF_X17_Y11_N13
-\myVirtualToplevel|MILLISEC_UP_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~49_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(4));
-
--- Location: MLABCELL_X13_Y12_N30
-\myVirtualToplevel|Mux268~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux268~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(4))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) #
--- (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|MILLISEC_UP_COUNTER\(4))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|SECOND_DOWN_COUNTER\(4)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|MILLISEC_DOWN_COUNTER\(4) & ( (\myVirtualToplevel|MICROSEC_DOWN_COUNTER\(4) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100000000010101010000111100110011111111110101010100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(4),
- datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(4),
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(4),
- combout => \myVirtualToplevel|Mux268~0_combout\);
-
--- Location: MLABCELL_X9_Y12_N0
-\myVirtualToplevel|Mux268~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux268~1_combout\ = ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) & ( \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(4)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) & (
--- \myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- (\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) ) # ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) & (
--- !\myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- (\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) ) # ( !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(4) & (
--- !\myVirtualToplevel|RTC_MINUTE_COUNTER[4]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_MICROSEC_COUNTER\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- (\myVirtualToplevel|RTC_SECOND_COUNTER[4]~DUPLICATE_q\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000001010000001111110101000000110000010111110011111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[4]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(4),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datae => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(4),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER[4]~DUPLICATE_q\,
- combout => \myVirtualToplevel|Mux268~1_combout\);
-
--- Location: FF_X6_Y11_N43
-\myVirtualToplevel|RTC_YEAR_COUNTER[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_YEAR_COUNTER[3]_OTERM1757\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_YEAR_COUNTER\(3));
-
--- Location: LABCELL_X6_Y11_N9
-\myVirtualToplevel|Add11~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add11~33_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add11~38\ ))
--- \myVirtualToplevel|Add11~34\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add11~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add11~38\,
- sumout => \myVirtualToplevel|Add11~33_sumout\,
- cout => \myVirtualToplevel|Add11~34\);
-
--- Location: LABCELL_X6_Y11_N42
-\myVirtualToplevel|RTC_YEAR_COUNTER[3]_NEW1756\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_YEAR_COUNTER[3]_OTERM1757\ = ( \myVirtualToplevel|Add11~33_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(3))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ &
--- ((!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3))))) ) ) # ( !\myVirtualToplevel|Add11~33_sumout\ & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ &
--- (((\myVirtualToplevel|RTC_YEAR_COUNTER\(3))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111001101000000011100110100100011111011110010001111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3),
- datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(3),
- dataf => \myVirtualToplevel|ALT_INV_Add11~33_sumout\,
- combout => \myVirtualToplevel|RTC_YEAR_COUNTER[3]_OTERM1757\);
-
--- Location: FF_X6_Y11_N44
-\myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_YEAR_COUNTER[3]_OTERM1757\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_YEAR_COUNTER[3]~DUPLICATE_q\);
-
--- Location: LABCELL_X6_Y11_N12
-\myVirtualToplevel|Add11~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add11~1_sumout\ = SUM(( \myVirtualToplevel|RTC_YEAR_COUNTER\(4) ) + ( GND ) + ( \myVirtualToplevel|Add11~34\ ))
--- \myVirtualToplevel|Add11~2\ = CARRY(( \myVirtualToplevel|RTC_YEAR_COUNTER\(4) ) + ( GND ) + ( \myVirtualToplevel|Add11~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(4),
- cin => \myVirtualToplevel|Add11~34\,
- sumout => \myVirtualToplevel|Add11~1_sumout\,
- cout => \myVirtualToplevel|Add11~2\);
-
--- Location: LABCELL_X7_Y11_N3
-\myVirtualToplevel|RTC_YEAR_COUNTER[4]_NEW1772\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|RTC_YEAR_COUNTER[4]_OTERM1773\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & ( (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(4))))) #
--- (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|Add11~1_sumout\)) # (\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4) & (
--- (!\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (((\myVirtualToplevel|RTC_YEAR_COUNTER\(4))))) # (\myVirtualToplevel|RTC_YEAR_COUNTER[6]~1_combout\ & (!\myVirtualToplevel|RTC_YEAR_COUNTER~0_combout\ & (\myVirtualToplevel|Add11~1_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001011001110000000101100111000010011110111110001001111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER[6]~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_Add11~1_sumout\,
- datad => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4),
- combout => \myVirtualToplevel|RTC_YEAR_COUNTER[4]_OTERM1773\);
-
--- Location: FF_X7_Y11_N5
-\myVirtualToplevel|RTC_YEAR_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|RTC_YEAR_COUNTER[4]_OTERM1773\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|RTC_YEAR_COUNTER\(4));
-
--- Location: LABCELL_X7_Y11_N36
-\myVirtualToplevel|IO_DATA_READ[4]~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[4]~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_DAY_COUNTER\(4)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- (\myVirtualToplevel|RTC_YEAR_COUNTER\(4))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & \myVirtualToplevel|RTC_HOUR_COUNTER\(4)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000100010001000100010001000000101101011110000010110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datab => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(4),
- datac => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(4),
- datad => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER\(4),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- combout => \myVirtualToplevel|IO_DATA_READ[4]~34_combout\);
-
--- Location: MLABCELL_X9_Y12_N6
-\myVirtualToplevel|IO_DATA_READ[4]~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[4]~35_combout\ = ( \myVirtualToplevel|IO_DATA_READ[4]~34_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|Mux268~0_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (((\myVirtualToplevel|Mux268~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\))) ) ) # ( !\myVirtualToplevel|IO_DATA_READ[4]~34_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & (\myVirtualToplevel|Mux268~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5) & ((\myVirtualToplevel|Mux268~1_combout\))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100001001100000010000100110000011001010111010001100101011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_Mux268~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_Mux268~1_combout\,
- dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~34_combout\,
- combout => \myVirtualToplevel|IO_DATA_READ[4]~35_combout\);
-
--- Location: FF_X13_Y6_N53
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_BUFFER\(5),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(21));
-
--- Location: FF_X13_Y6_N7
-\myVirtualToplevel|UART1|RX_FIFO~22\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_BUFFER\(5),
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO~22_q\);
-
--- Location: MLABCELL_X13_Y6_N6
-\myVirtualToplevel|UART1|RX_DATA~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA~4_combout\ = ( \myVirtualToplevel|UART1|RX_BUFFER\(5) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) # (\myVirtualToplevel|UART1|RX_FIFO~22_q\) ) ) ) # (
--- !\myVirtualToplevel|UART1|RX_BUFFER\(5) & ( \myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (\myVirtualToplevel|UART1|RX_FIFO~22_q\ & \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\) ) ) ) # ( \myVirtualToplevel|UART1|RX_BUFFER\(5) & (
--- !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(21))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ &
--- ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a4\))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_BUFFER\(5) & ( !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ &
--- (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(21))) # (\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a4\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001011111010100000101111100000011000000111111001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(21),
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~22_q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\,
- datad => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\,
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(5),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\,
- combout => \myVirtualToplevel|UART1|RX_DATA~4_combout\);
-
--- Location: MLABCELL_X13_Y6_N3
-\myVirtualToplevel|UART1|RX_DATA[4]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA[4]~5_combout\ = ( \myVirtualToplevel|UART1|RX_DATA\(4) & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\) # ((!\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\) # (\myVirtualToplevel|UART1|RX_DATA~4_combout\)) ) ) # (
--- !\myVirtualToplevel|UART1|RX_DATA\(4) & ( (\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & (\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ & \myVirtualToplevel|UART1|RX_DATA~4_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100000001111011111110111100000001000000011110111111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~4_combout\,
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(4),
- combout => \myVirtualToplevel|UART1|RX_DATA[4]~5_combout\);
-
--- Location: FF_X13_Y6_N4
-\myVirtualToplevel|UART1|RX_DATA[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_DATA[4]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_DATA\(4));
-
--- Location: LABCELL_X16_Y5_N30
-\myVirtualToplevel|UART1|Add5~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add5~26_cout\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1),
- cin => GND,
- cout => \myVirtualToplevel|UART1|Add5~26_cout\);
-
--- Location: LABCELL_X16_Y5_N33
-\myVirtualToplevel|UART1|Add5~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add5~17_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~26_cout\ ))
--- \myVirtualToplevel|UART1|Add5~18\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~26_cout\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(2),
- cin => \myVirtualToplevel|UART1|Add5~26_cout\,
- sumout => \myVirtualToplevel|UART1|Add5~17_sumout\,
- cout => \myVirtualToplevel|UART1|Add5~18\);
-
--- Location: LABCELL_X16_Y5_N36
-\myVirtualToplevel|UART1|Add5~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add5~21_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~18\ ))
--- \myVirtualToplevel|UART1|Add5~22\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3),
- cin => \myVirtualToplevel|UART1|Add5~18\,
- sumout => \myVirtualToplevel|UART1|Add5~21_sumout\,
- cout => \myVirtualToplevel|UART1|Add5~22\);
-
--- Location: LABCELL_X16_Y5_N39
-\myVirtualToplevel|UART1|Add5~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add5~9_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~22\ ))
--- \myVirtualToplevel|UART1|Add5~10\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4),
- cin => \myVirtualToplevel|UART1|Add5~22\,
- sumout => \myVirtualToplevel|UART1|Add5~9_sumout\,
- cout => \myVirtualToplevel|UART1|Add5~10\);
-
--- Location: LABCELL_X16_Y5_N42
-\myVirtualToplevel|UART1|Add5~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add5~13_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~10\ ))
--- \myVirtualToplevel|UART1|Add5~14\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(5),
- cin => \myVirtualToplevel|UART1|Add5~10\,
- sumout => \myVirtualToplevel|UART1|Add5~13_sumout\,
- cout => \myVirtualToplevel|UART1|Add5~14\);
-
--- Location: LABCELL_X16_Y5_N45
-\myVirtualToplevel|UART1|Add5~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add5~1_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~14\ ))
--- \myVirtualToplevel|UART1|Add5~2\ = CARRY(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(6),
- cin => \myVirtualToplevel|UART1|Add5~14\,
- sumout => \myVirtualToplevel|UART1|Add5~1_sumout\,
- cout => \myVirtualToplevel|UART1|Add5~2\);
-
--- Location: LABCELL_X16_Y5_N48
-\myVirtualToplevel|UART1|Add5~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add5~5_sumout\ = SUM(( \myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART1|Add5~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(7),
- cin => \myVirtualToplevel|UART1|Add5~2\,
- sumout => \myVirtualToplevel|UART1|Add5~5_sumout\);
-
--- Location: LABCELL_X14_Y5_N0
-\myVirtualToplevel|UART1|RX_INTR~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_INTR~2_combout\ = ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( (\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) $ (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1))))
--- ) ) # ( !\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(0) & ( (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR[0]~DUPLICATE_q\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(1) $ (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010100000101000001010000010100000010100000101000001010000010100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR[0]~DUPLICATE_q\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(1),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(1),
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(0),
- combout => \myVirtualToplevel|UART1|RX_INTR~2_combout\);
-
--- Location: LABCELL_X16_Y5_N21
-\myVirtualToplevel|UART1|RX_INTR~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_INTR~3_combout\ = ( \myVirtualToplevel|UART1|Add5~21_sumout\ & ( (\myVirtualToplevel|UART1|RX_INTR~2_combout\ & (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) $
--- (\myVirtualToplevel|UART1|Add5~17_sumout\)))) ) ) # ( !\myVirtualToplevel|UART1|Add5~21_sumout\ & ( (\myVirtualToplevel|UART1|RX_INTR~2_combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(2) $
--- (\myVirtualToplevel|UART1|Add5~17_sumout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000000010000000000100000000100100000000100000000001000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(2),
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~2_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add5~17_sumout\,
- datae => \myVirtualToplevel|UART1|ALT_INV_Add5~21_sumout\,
- combout => \myVirtualToplevel|UART1|RX_INTR~3_combout\);
-
--- Location: LABCELL_X16_Y5_N6
-\myVirtualToplevel|UART1|RX_INTR~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_INTR~1_combout\ = ( \myVirtualToplevel|UART1|Add5~9_sumout\ & ( (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) $ (\myVirtualToplevel|UART1|Add5~13_sumout\))) ) ) # (
--- !\myVirtualToplevel|UART1|Add5~9_sumout\ & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(5) $ (\myVirtualToplevel|UART1|Add5~13_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000001010101000000000101001010000000001010101000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(5),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add5~13_sumout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Add5~9_sumout\,
- combout => \myVirtualToplevel|UART1|RX_INTR~1_combout\);
-
--- Location: LABCELL_X16_Y5_N24
-\myVirtualToplevel|UART1|RX_INTR~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_INTR~4_combout\ = ( \myVirtualToplevel|UART1|RX_INTR~3_combout\ & ( \myVirtualToplevel|UART1|RX_INTR~1_combout\ & ( (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART1|Add5~1_sumout\ &
--- (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) $ (\myVirtualToplevel|UART1|Add5~5_sumout\)))) # (\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(6) & (\myVirtualToplevel|UART1|Add5~1_sumout\ & (!\myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(7) $
--- (\myVirtualToplevel|UART1|Add5~5_sumout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001000001001000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(6),
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(7),
- datac => \myVirtualToplevel|UART1|ALT_INV_Add5~5_sumout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Add5~1_sumout\,
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~3_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~1_combout\,
- combout => \myVirtualToplevel|UART1|RX_INTR~4_combout\);
-
--- Location: LABCELL_X16_Y6_N12
-\myVirtualToplevel|UART1|RX_INTR~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_INTR~5_combout\ = ( \myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & ( (\myVirtualToplevel|UART1|RX_INTR~0_combout\ & ((\myVirtualToplevel|UART1|RX_INTR~4_combout\) # (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\))) ) ) # (
--- !\myVirtualToplevel|UART1|RX_DATA_READY~DUPLICATE_q\ & ( (\myVirtualToplevel|UART1|RX_INTR~0_combout\ & (((\myVirtualToplevel|UART1|RX_INTR~4_combout\) # (\myVirtualToplevel|UART1|Equal2~4_combout\)) # (\myVirtualToplevel|UART1|RX_ENABLE_FIFO~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001010101010101000101010101010100010001010101010001000101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~0_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE_FIFO~q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_Equal2~4_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~4_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_DATA_READY~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART1|RX_INTR~5_combout\);
-
--- Location: FF_X16_Y6_N13
-\myVirtualToplevel|UART1|RX_INTR\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_INTR~5_combout\,
- clrn => \myVirtualToplevel|UART1|RX_RESET~q\,
- ena => \myVirtualToplevel|UART1|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_INTR~q\);
-
--- Location: LABCELL_X12_Y6_N51
-\myVirtualToplevel|UART0|RX_INTR~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_INTR~2_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) $ (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1))))
--- ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(0) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(1) $ (!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101101000000000010110100000000000000000010110100000000001011010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(1),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(0),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART0|RX_INTR~2_combout\);
-
--- Location: MLABCELL_X9_Y6_N0
-\myVirtualToplevel|UART0|Add5~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add5~26_cout\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(1),
- cin => GND,
- cout => \myVirtualToplevel|UART0|Add5~26_cout\);
-
--- Location: MLABCELL_X9_Y6_N3
-\myVirtualToplevel|UART0|Add5~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add5~17_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~26_cout\ ))
--- \myVirtualToplevel|UART0|Add5~18\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~26_cout\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(2),
- cin => \myVirtualToplevel|UART0|Add5~26_cout\,
- sumout => \myVirtualToplevel|UART0|Add5~17_sumout\,
- cout => \myVirtualToplevel|UART0|Add5~18\);
-
--- Location: MLABCELL_X9_Y6_N6
-\myVirtualToplevel|UART0|Add5~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add5~21_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~18\ ))
--- \myVirtualToplevel|UART0|Add5~22\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3),
- cin => \myVirtualToplevel|UART0|Add5~18\,
- sumout => \myVirtualToplevel|UART0|Add5~21_sumout\,
- cout => \myVirtualToplevel|UART0|Add5~22\);
-
--- Location: MLABCELL_X9_Y6_N54
-\myVirtualToplevel|UART0|RX_INTR~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_INTR~3_combout\ = ( \myVirtualToplevel|UART0|Add5~21_sumout\ & ( (\myVirtualToplevel|UART0|RX_INTR~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) $
--- (\myVirtualToplevel|UART0|Add5~17_sumout\)))) ) ) # ( !\myVirtualToplevel|UART0|Add5~21_sumout\ & ( (\myVirtualToplevel|UART0|RX_INTR~2_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(2) $
--- (\myVirtualToplevel|UART0|Add5~17_sumout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100000000010000010000000001000000000100000000010000010000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~2_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(2),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3),
- datad => \myVirtualToplevel|UART0|ALT_INV_Add5~17_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_Add5~21_sumout\,
- combout => \myVirtualToplevel|UART0|RX_INTR~3_combout\);
-
--- Location: MLABCELL_X9_Y6_N9
-\myVirtualToplevel|UART0|Add5~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add5~9_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~22\ ))
--- \myVirtualToplevel|UART0|Add5~10\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4),
- cin => \myVirtualToplevel|UART0|Add5~22\,
- sumout => \myVirtualToplevel|UART0|Add5~9_sumout\,
- cout => \myVirtualToplevel|UART0|Add5~10\);
-
--- Location: MLABCELL_X9_Y6_N12
-\myVirtualToplevel|UART0|Add5~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add5~13_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~10\ ))
--- \myVirtualToplevel|UART0|Add5~14\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(5),
- cin => \myVirtualToplevel|UART0|Add5~10\,
- sumout => \myVirtualToplevel|UART0|Add5~13_sumout\,
- cout => \myVirtualToplevel|UART0|Add5~14\);
-
--- Location: MLABCELL_X9_Y6_N15
-\myVirtualToplevel|UART0|Add5~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add5~1_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~14\ ))
--- \myVirtualToplevel|UART0|Add5~2\ = CARRY(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(6),
- cin => \myVirtualToplevel|UART0|Add5~14\,
- sumout => \myVirtualToplevel|UART0|Add5~1_sumout\,
- cout => \myVirtualToplevel|UART0|Add5~2\);
-
--- Location: MLABCELL_X9_Y6_N36
-\myVirtualToplevel|UART0|RX_INTR~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_INTR~1_combout\ = ( \myVirtualToplevel|UART0|Add5~9_sumout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART0|Add5~13_sumout\ $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5)))) ) ) # (
--- !\myVirtualToplevel|UART0|Add5~9_sumout\ & ( (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) & (!\myVirtualToplevel|UART0|Add5~13_sumout\ $ (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(5)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100001100000000110000110000000000000000110000110000000011000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_Add5~13_sumout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(5),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4),
- dataf => \myVirtualToplevel|UART0|ALT_INV_Add5~9_sumout\,
- combout => \myVirtualToplevel|UART0|RX_INTR~1_combout\);
-
--- Location: MLABCELL_X9_Y6_N18
-\myVirtualToplevel|UART0|Add5~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add5~5_sumout\ = SUM(( \myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add5~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(7),
- cin => \myVirtualToplevel|UART0|Add5~2\,
- sumout => \myVirtualToplevel|UART0|Add5~5_sumout\);
-
--- Location: MLABCELL_X9_Y6_N48
-\myVirtualToplevel|UART0|RX_INTR~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_INTR~4_combout\ = ( \myVirtualToplevel|UART0|RX_INTR~1_combout\ & ( \myVirtualToplevel|UART0|Add5~5_sumout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) & (\myVirtualToplevel|UART0|RX_INTR~3_combout\ &
--- (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|UART0|Add5~1_sumout\)))) ) ) ) # ( \myVirtualToplevel|UART0|RX_INTR~1_combout\ & ( !\myVirtualToplevel|UART0|Add5~5_sumout\ & ( (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(7) &
--- (\myVirtualToplevel|UART0|RX_INTR~3_combout\ & (!\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|UART0|Add5~1_sumout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000010000000010000000000000000000000001000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(6),
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(7),
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~3_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_Add5~1_sumout\,
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~1_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_Add5~5_sumout\,
- combout => \myVirtualToplevel|UART0|RX_INTR~4_combout\);
-
--- Location: MLABCELL_X9_Y6_N24
-\myVirtualToplevel|UART0|RX_INTR~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_INTR~5_combout\ = ( \myVirtualToplevel|UART0|RX_DATA_READY~q\ & ( (\myVirtualToplevel|UART0|RX_INTR~0_combout\ & ((\myVirtualToplevel|UART0|RX_INTR~4_combout\) # (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\))) ) ) # (
--- !\myVirtualToplevel|UART0|RX_DATA_READY~q\ & ( (\myVirtualToplevel|UART0|RX_INTR~0_combout\ & (((\myVirtualToplevel|UART0|RX_INTR~4_combout\) # (\myVirtualToplevel|UART0|RX_ENABLE_FIFO~DUPLICATE_q\)) # (\myVirtualToplevel|UART0|Equal2~4_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001111111000000000111111100000000001111110000000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Equal2~4_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE_FIFO~DUPLICATE_q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~4_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~0_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA_READY~q\,
- combout => \myVirtualToplevel|UART0|RX_INTR~5_combout\);
-
--- Location: FF_X9_Y6_N26
-\myVirtualToplevel|UART0|RX_INTR\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_INTR~5_combout\,
- clrn => \myVirtualToplevel|UART0|RX_RESET~q\,
- ena => \myVirtualToplevel|UART0|ALT_INV_RX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_INTR~q\);
-
--- Location: FF_X10_Y5_N5
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_BUFFER\(5),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(21));
-
--- Location: FF_X10_Y5_N32
-\myVirtualToplevel|UART0|RX_FIFO~22\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_BUFFER\(5),
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO~22_q\);
-
--- Location: LABCELL_X10_Y5_N30
-\myVirtualToplevel|UART0|RX_DATA~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA~4_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(5) & ( \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ &
--- ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a4\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO~22_q\)) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(5) & (
--- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ((\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a4\))) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ &
--- (\myVirtualToplevel|UART0|RX_FIFO~22_q\)) ) ) ) # ( \myVirtualToplevel|UART0|RX_BUFFER\(5) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) # (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(21)) ) )
--- ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(5) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(21) & !\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010000010111110101111100000011111100110000001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(21),
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~22_q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\,
- datad => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a4\,
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(5),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA~4_combout\);
-
--- Location: MLABCELL_X9_Y5_N36
-\myVirtualToplevel|UART0|RX_DATA[4]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA[4]~5_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~4_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\ & \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(4)) ) ) # (
--- !\myVirtualToplevel|UART0|RX_DATA~4_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(4) & ((!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(4),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~4_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA[4]~5_combout\);
-
--- Location: FF_X9_Y5_N37
-\myVirtualToplevel|UART0|RX_DATA[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_DATA[4]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_DATA\(4));
-
--- Location: LABCELL_X12_Y9_N9
-\myVirtualToplevel|IO_DATA_READ~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~33_combout\ = ( \myVirtualToplevel|UART0|RX_DATA\(4) & ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|UART0|RX_INTR~q\) ) ) ) # (
--- !\myVirtualToplevel|UART0|RX_DATA\(4) & ( \myVirtualToplevel|UART0_CS~combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|UART0|RX_INTR~q\) ) ) ) # ( \myVirtualToplevel|UART0|RX_DATA\(4) & ( !\myVirtualToplevel|UART0_CS~combout\
--- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|UART1|RX_DATA\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|RX_INTR~q\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_DATA\(4) & (
--- !\myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|UART1|RX_DATA\(4))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|UART1|RX_INTR~q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010011100100111001001110010011100000000010101011010101011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(4),
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_INTR~q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_INTR~q\,
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(4),
- dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\,
- combout => \myVirtualToplevel|IO_DATA_READ~33_combout\);
-
--- Location: LABCELL_X10_Y7_N33
-\myVirtualToplevel|UART1|Add9~24\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~24_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(4) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(4) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(4),
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(4),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add9~24_combout\);
-
--- Location: LABCELL_X12_Y7_N27
-\myVirtualToplevel|UART1|Add9~28\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~28_combout\ = ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) ) ) ) # ( !\myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & (
--- \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|RX_FIFO_WR_ADDR\(3) ) ) ) # ( \myVirtualToplevel|UART0|RX_FIFO_WR_ADDR\(3) & ( !\myVirtualToplevel|UART1_CS~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_WR_ADDR\(3),
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_WR_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add9~28_combout\);
-
--- Location: MLABCELL_X13_Y7_N12
-\myVirtualToplevel|UART1|Add9~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~17_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~28_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3))))) ) + ( \myVirtualToplevel|UART1|Add9~22\ ))
--- \myVirtualToplevel|UART1|Add9~18\ = CARRY(( \myVirtualToplevel|UART1|Add9~28_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(3)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(3))))) ) + ( \myVirtualToplevel|UART1|Add9~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000011110111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(3),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add9~28_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(3),
- cin => \myVirtualToplevel|UART1|Add9~22\,
- sumout => \myVirtualToplevel|UART1|Add9~17_sumout\,
- cout => \myVirtualToplevel|UART1|Add9~18\);
-
--- Location: MLABCELL_X13_Y7_N15
-\myVirtualToplevel|UART1|Add9~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add9~1_sumout\ = SUM(( \myVirtualToplevel|UART1|Add9~24_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4))))) ) + ( \myVirtualToplevel|UART1|Add9~18\ ))
--- \myVirtualToplevel|UART1|Add9~2\ = CARRY(( \myVirtualToplevel|UART1|Add9~24_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|RX_FIFO_RD_ADDR\(4)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|RX_FIFO_RD_ADDR\(4))))) ) + ( \myVirtualToplevel|UART1|Add9~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000011110111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_RD_ADDR\(4),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add9~24_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_RD_ADDR\(4),
- cin => \myVirtualToplevel|UART1|Add9~18\,
- sumout => \myVirtualToplevel|UART1|Add9~1_sumout\,
- cout => \myVirtualToplevel|UART1|Add9~2\);
-
--- Location: LABCELL_X12_Y10_N30
-\myVirtualToplevel|IO_DATA_READ[4]~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[4]~36_combout\ = ( \myVirtualToplevel|IO_DATA_READ~33_combout\ & ( \myVirtualToplevel|UART1|Add9~1_sumout\ & ( (!\myVirtualToplevel|TIMER0_CS~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & (((\myVirtualToplevel|IO_DATA_READ[4]~35_combout\)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~33_combout\ & ( \myVirtualToplevel|UART1|Add9~1_sumout\ & (
--- (!\myVirtualToplevel|TIMER0_CS~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ & (((\myVirtualToplevel|IO_DATA_READ[4]~35_combout\)))) ) ) ) # (
--- \myVirtualToplevel|IO_DATA_READ~33_combout\ & ( !\myVirtualToplevel|UART1|Add9~1_sumout\ & ( (!\myVirtualToplevel|TIMER0_CS~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) # (\myVirtualToplevel|TIMER0_CS~1_combout\ &
--- ((\myVirtualToplevel|IO_DATA_READ[4]~35_combout\))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~33_combout\ & ( !\myVirtualToplevel|UART1|Add9~1_sumout\ & ( (\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|IO_DATA_READ[4]~35_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111101000001010111101000000010011111110000011101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\,
- datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ[4]~35_combout\,
- datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~33_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Add9~1_sumout\,
- combout => \myVirtualToplevel|IO_DATA_READ[4]~36_combout\);
-
--- Location: FF_X12_Y10_N31
-\myVirtualToplevel|IO_DATA_READ[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ[4]~36_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ\(4));
-
--- Location: LABCELL_X20_Y13_N57
-\myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739_BDD8740\ = ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(4) ) ) # ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(4) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(4),
- datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(4),
- dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[4]~90_RESYN8739_BDD8740\);
-
--- Location: LABCELL_X25_Y9_N0
-\myVirtualToplevel|TIMER:TIMER1|Add0~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~57_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~58\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(0),
- cin => GND,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~57_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~58\);
-
--- Location: FF_X25_Y9_N2
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~57_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(0));
-
--- Location: LABCELL_X25_Y9_N3
-\myVirtualToplevel|TIMER:TIMER1|Add0~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~45_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(1) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~58\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~46\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(1) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(1),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~58\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~45_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~46\);
-
--- Location: FF_X25_Y9_N5
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~45_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(1));
-
--- Location: LABCELL_X25_Y9_N6
-\myVirtualToplevel|TIMER:TIMER1|Add0~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~41_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(2) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~46\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~42\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(2) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(2),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~46\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~41_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~42\);
-
--- Location: FF_X25_Y9_N8
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~41_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(2));
-
--- Location: LABCELL_X25_Y9_N9
-\myVirtualToplevel|TIMER:TIMER1|Add0~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~29_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~42\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~30\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~42\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~29_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~30\);
-
--- Location: FF_X25_Y9_N11
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~29_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]~DUPLICATE_q\);
-
--- Location: LABCELL_X25_Y9_N12
-\myVirtualToplevel|TIMER:TIMER1|Add0~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~25_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(4) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~30\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~26\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(4) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(4),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~30\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~25_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~26\);
-
--- Location: FF_X25_Y9_N14
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~25_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(4));
-
--- Location: LABCELL_X25_Y9_N15
-\myVirtualToplevel|TIMER:TIMER1|Add0~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~37_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(5) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~26\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~38\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(5) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(5),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~26\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~37_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~38\);
-
--- Location: FF_X25_Y9_N17
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~37_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(5));
-
--- Location: LABCELL_X25_Y9_N18
-\myVirtualToplevel|TIMER:TIMER1|Add0~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~21_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(6) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~38\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~22\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(6) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(6),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~38\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~21_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~22\);
-
--- Location: FF_X25_Y9_N20
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~21_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(6));
-
--- Location: LABCELL_X25_Y9_N21
-\myVirtualToplevel|TIMER:TIMER1|Add0~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~61_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(7) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~22\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~62\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(7) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(7),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~22\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~61_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~62\);
-
--- Location: FF_X25_Y9_N23
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~61_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(7));
-
--- Location: LABCELL_X25_Y9_N24
-\myVirtualToplevel|TIMER:TIMER1|Add0~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~17_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(8) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~62\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~18\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(8) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(8),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~62\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~17_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~18\);
-
--- Location: FF_X25_Y9_N26
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~17_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(8));
-
--- Location: LABCELL_X25_Y9_N27
-\myVirtualToplevel|TIMER:TIMER1|Add0~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~33_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(9) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~18\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~34\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(9) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(9),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~18\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~33_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~34\);
-
--- Location: FF_X25_Y9_N29
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~33_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(9));
-
--- Location: LABCELL_X25_Y9_N30
-\myVirtualToplevel|TIMER:TIMER1|Add0~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~13_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~34\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~14\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[10]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~34\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~13_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~14\);
-
--- Location: FF_X25_Y9_N32
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~13_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]~DUPLICATE_q\);
-
--- Location: LABCELL_X25_Y9_N33
-\myVirtualToplevel|TIMER:TIMER1|Add0~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~9_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(11) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~14\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~10\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(11) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(11),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~14\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~9_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~10\);
-
--- Location: FF_X25_Y9_N35
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~9_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(11));
-
--- Location: LABCELL_X25_Y9_N36
-\myVirtualToplevel|TIMER:TIMER1|Add0~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~5_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(12) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~10\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~6\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(12) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(12),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~10\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~5_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~6\);
-
--- Location: FF_X25_Y9_N37
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~5_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(12));
-
--- Location: LABCELL_X25_Y9_N39
-\myVirtualToplevel|TIMER:TIMER1|Add0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~1_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(13) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~6\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~2\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(13) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(13),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~6\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~1_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~2\);
-
--- Location: FF_X25_Y9_N41
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~1_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(13));
-
--- Location: LABCELL_X25_Y9_N42
-\myVirtualToplevel|TIMER:TIMER1|Add0~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~53_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(14) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~2\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add0~54\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(14) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(14),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~2\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~53_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add0~54\);
-
--- Location: FF_X25_Y9_N44
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~53_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(14));
-
--- Location: LABCELL_X25_Y9_N45
-\myVirtualToplevel|TIMER:TIMER1|Add0~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add0~49_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(15) ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add0~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(15),
- cin => \myVirtualToplevel|TIMER:TIMER1|Add0~54\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add0~49_sumout\);
-
--- Location: FF_X25_Y9_N47
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~49_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(15));
-
--- Location: LABCELL_X25_Y9_N57
-\myVirtualToplevel|TIMER:TIMER1|Equal0~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Equal0~3_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(14) & ( (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(0) & (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(15) &
--- !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(7))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(0),
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(15),
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(7),
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(14),
- combout => \myVirtualToplevel|TIMER:TIMER1|Equal0~3_combout\);
-
--- Location: FF_X25_Y9_N10
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~29_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(3));
-
--- Location: LABCELL_X25_Y9_N51
-\myVirtualToplevel|TIMER:TIMER1|Equal0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Equal0~1_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(8) & ( (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(6) & (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(4) &
--- !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(3))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000000000101000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(6),
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(4),
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(3),
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(8),
- combout => \myVirtualToplevel|TIMER:TIMER1|Equal0~1_combout\);
-
--- Location: LABCELL_X25_Y9_N54
-\myVirtualToplevel|TIMER:TIMER1|Equal0~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Equal0~2_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(2) & ( (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(5) & (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(9) &
--- !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(1))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1100000000000000110000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(5),
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(9),
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(1),
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(2),
- combout => \myVirtualToplevel|TIMER:TIMER1|Equal0~2_combout\);
-
--- Location: FF_X25_Y9_N31
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~13_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter\(10));
-
--- Location: FF_X25_Y9_N40
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~1_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE_q\);
-
--- Location: FF_X25_Y9_N34
-\myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add0~9_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y9_N12
-\myVirtualToplevel|TIMER:TIMER1|Equal0~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Equal0~0_combout\ = ( !\myVirtualToplevel|TIMER:TIMER1|prescale_counter[11]~DUPLICATE_q\ & ( !\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(12) & ( (!\myVirtualToplevel|TIMER:TIMER1|prescale_counter\(10) &
--- !\myVirtualToplevel|TIMER:TIMER1|prescale_counter[13]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000010100000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(10),
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[13]~DUPLICATE_q\,
- datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter[11]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescale_counter\(12),
- combout => \myVirtualToplevel|TIMER:TIMER1|Equal0~0_combout\);
-
--- Location: LABCELL_X25_Y9_N48
-\myVirtualToplevel|TIMER:TIMER1|Equal0~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Equal0~0_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|Equal0~3_combout\ & (\myVirtualToplevel|TIMER:TIMER1|Equal0~1_combout\ &
--- \myVirtualToplevel|TIMER:TIMER1|Equal0~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000110000000000000011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~3_combout\,
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~1_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~2_combout\,
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Equal0~0_combout\,
- combout => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\);
-
--- Location: FF_X25_Y9_N49
-\myVirtualToplevel|TIMER:TIMER1|prescaled_tick\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Equal0~4_combout\,
- ena => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|prescaled_tick~q\);
-
--- Location: LABCELL_X21_Y11_N18
-\myVirtualToplevel|TIMER_REG_REQ~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER_REG_REQ~feeder_combout\ = VCC
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- combout => \myVirtualToplevel|TIMER_REG_REQ~feeder_combout\);
-
--- Location: LABCELL_X16_Y11_N45
-\myVirtualToplevel|process_0~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|process_0~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & ( (\myVirtualToplevel|TIMER0_CS~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- combout => \myVirtualToplevel|process_0~0_combout\);
-
--- Location: FF_X21_Y11_N19
-\myVirtualToplevel|TIMER_REG_REQ\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER_REG_REQ~feeder_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|process_0~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER_REG_REQ~q\);
-
--- Location: LABCELL_X14_Y11_N42
-\myVirtualToplevel|TIMER:TIMER1|Mux2~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[1]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[1]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\);
-
--- Location: LABCELL_X14_Y11_N0
-\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) ) ) # ( \myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|TIMER_REG_REQ~q\) # ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)))) ) ) ) # (
--- !\myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|TIMER_REG_REQ~q\ & (\myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100000000111011111111111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_TIMER_REG_REQ~q\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1_combout\);
-
--- Location: FF_X14_Y11_N1
-\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0));
-
--- Location: LABCELL_X20_Y11_N6
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_enabled\(0) & ( \myVirtualToplevel|TIMER:TIMER1|prescaled_tick~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_prescaled_tick~q\,
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled\(0),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\);
-
--- Location: LABCELL_X19_Y8_N0
-\myVirtualToplevel|TIMER:TIMER1|Add1~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~85_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~86\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][0]~DUPLICATE_q\,
- cin => GND,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~85_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~86\);
-
--- Location: MLABCELL_X18_Y11_N54
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ = ( \myVirtualToplevel|RESET_n~q\ & ( \myVirtualToplevel|TIMER_REG_REQ~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- dataf => \myVirtualToplevel|ALT_INV_TIMER_REG_REQ~q\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\);
-
--- Location: LABCELL_X14_Y11_N54
-\myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_index\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) ) ) # ( \myVirtualToplevel|TIMER:TIMER1|timer_index\(0) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) # ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0)))) ) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|timer_index\(0) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ &
--- (\myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001111111111110111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_index\(0),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0_combout\);
-
--- Location: FF_X14_Y11_N55
-\myVirtualToplevel|TIMER:TIMER1|timer_index[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_index[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_index\(0));
-
--- Location: MLABCELL_X18_Y9_N45
-\myVirtualToplevel|TIMER:TIMER1|Mux2~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- combout => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\);
-
--- Location: MLABCELL_X18_Y9_N6
-\myVirtualToplevel|TIMER:TIMER1|Mux2~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|Mux2~1_combout\ & !\myVirtualToplevel|TIMER:TIMER1|timer_index\(0)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100000011000000000000000000000011000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~1_combout\,
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_index\(0),
- datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~0_combout\,
- combout => \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\);
-
--- Location: MLABCELL_X18_Y7_N9
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22_combout\);
-
--- Location: FF_X18_Y7_N10
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~22_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\);
-
--- Location: FF_X19_Y8_N2
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~85_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][0]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N3
-\myVirtualToplevel|TIMER:TIMER1|Add1~97\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~97_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~86\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~98\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][1]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~86\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~97_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~98\);
-
--- Location: MLABCELL_X18_Y8_N45
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(1) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][1]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(1),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25_combout\);
-
--- Location: FF_X18_Y8_N46
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~25_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\);
-
--- Location: FF_X19_Y8_N5
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~97_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][1]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][1]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N6
-\myVirtualToplevel|TIMER:TIMER1|Add1~101\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~101_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~98\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~102\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~98\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][2]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~98\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~101_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~102\);
-
--- Location: LABCELL_X17_Y8_N6
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26_combout\ = (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\)))) # (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ &
--- ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\))) # (\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(2)))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111101111000000011110111100000001111011110000000111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(2),
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][2]~q\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26_combout\);
-
--- Location: FF_X17_Y8_N7
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~26_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\);
-
--- Location: FF_X19_Y8_N8
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~101_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][2]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][2]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N9
-\myVirtualToplevel|TIMER:TIMER1|Add1~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~69_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~102\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~70\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~102\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~102\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~69_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~70\);
-
--- Location: MLABCELL_X18_Y7_N18
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(3) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(3),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18_combout\);
-
--- Location: FF_X18_Y7_N19
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~18_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\);
-
--- Location: FF_X19_Y8_N11
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~69_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][3]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][3]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N12
-\myVirtualToplevel|TIMER:TIMER1|Add1~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~73_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~70\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~74\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][4]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~70\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~73_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~74\);
-
--- Location: MLABCELL_X18_Y8_N12
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19_combout\ = (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & (((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\)))) # (\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ &
--- ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\))) # (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(4)))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111101111000000011110111100000001111011110000000111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(4),
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][4]~q\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19_combout\);
-
--- Location: FF_X18_Y8_N13
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~19_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\);
-
--- Location: FF_X19_Y8_N14
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~73_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][4]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][4]~q\);
-
--- Location: LABCELL_X19_Y8_N15
-\myVirtualToplevel|TIMER:TIMER1|Add1~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~77_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~74\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~78\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][5]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~74\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~77_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~78\);
-
--- Location: LABCELL_X20_Y8_N33
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\ & ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5)) ) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\ & ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(5)) ) ) ) # ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\ & ( !\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000010101011010101011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(5),
- datae => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][5]~q\,
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20_combout\);
-
--- Location: FF_X20_Y8_N35
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~20_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\);
-
--- Location: FF_X19_Y8_N17
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~77_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][5]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][5]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N18
-\myVirtualToplevel|TIMER:TIMER1|Add1~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~89_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~78\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~90\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~78\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~89_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~90\);
-
--- Location: MLABCELL_X18_Y8_N3
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][6]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23_combout\);
-
--- Location: FF_X18_Y8_N4
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~23_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\);
-
--- Location: FF_X19_Y8_N20
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~89_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][6]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][6]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N21
-\myVirtualToplevel|TIMER:TIMER1|Add1~93\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~93_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~90\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~94\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~90\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][7]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~90\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~93_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~94\);
-
--- Location: MLABCELL_X18_Y8_N9
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24_combout\);
-
--- Location: FF_X18_Y8_N10
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~24_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\);
-
--- Location: FF_X19_Y8_N23
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~93_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][7]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N24
-\myVirtualToplevel|TIMER:TIMER1|Add1~113\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~113_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~94\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~114\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~94\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][8]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~94\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~113_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~114\);
-
--- Location: MLABCELL_X18_Y8_N6
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][8]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29_combout\);
-
--- Location: FF_X18_Y8_N7
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~29_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\);
-
--- Location: FF_X19_Y8_N26
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~113_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][8]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][8]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N27
-\myVirtualToplevel|TIMER:TIMER1|Add1~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~9_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~114\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~10\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~114\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][9]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~114\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~9_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~10\);
-
--- Location: MLABCELL_X18_Y7_N36
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][9]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[9]~DUPLICATE_q\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3_combout\);
-
--- Location: FF_X18_Y7_N37
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~3_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\);
-
--- Location: FF_X19_Y8_N29
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~9_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][9]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][9]~q\);
-
--- Location: LABCELL_X19_Y8_N30
-\myVirtualToplevel|TIMER:TIMER1|Add1~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~13_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~10\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~14\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][10]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~10\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~13_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~14\);
-
--- Location: MLABCELL_X18_Y7_N21
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][10]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(10),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4_combout\);
-
--- Location: FF_X18_Y7_N22
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~4_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\);
-
--- Location: FF_X19_Y8_N31
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~13_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][10]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][10]~q\);
-
--- Location: LABCELL_X19_Y8_N33
-\myVirtualToplevel|TIMER:TIMER1|Add1~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~33_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~14\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~34\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][11]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~14\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~33_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~34\);
-
--- Location: MLABCELL_X18_Y8_N33
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\))) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11))) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000011110011110000001111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(11),
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][11]~q\,
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9_combout\);
-
--- Location: FF_X18_Y8_N34
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~9_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\);
-
--- Location: FF_X19_Y8_N35
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~33_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][11]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][11]~q\);
-
--- Location: LABCELL_X19_Y8_N36
-\myVirtualToplevel|TIMER:TIMER1|Add1~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~81_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~34\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~82\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~34\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~81_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~82\);
-
--- Location: MLABCELL_X18_Y8_N42
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][12]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(12),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21_combout\);
-
--- Location: FF_X18_Y8_N43
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~21_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\);
-
--- Location: FF_X19_Y8_N38
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~81_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][12]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][12]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N39
-\myVirtualToplevel|TIMER:TIMER1|Add1~105\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~105_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~82\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~106\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][13]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~82\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~105_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~106\);
-
--- Location: MLABCELL_X18_Y8_N30
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][13]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(13),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27_combout\);
-
--- Location: FF_X18_Y8_N31
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~27_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\);
-
--- Location: FF_X19_Y8_N41
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~105_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][13]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][13]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N42
-\myVirtualToplevel|TIMER:TIMER1|Add1~109\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~109_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~106\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~110\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~106\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][14]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~106\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~109_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~110\);
-
--- Location: MLABCELL_X18_Y8_N0
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28_combout\ = (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & (((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\)))) # (\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ &
--- ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\))) # (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111101111000000011110111100000001111011110000000111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][14]~q\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28_combout\);
-
--- Location: FF_X18_Y8_N1
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~28_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\);
-
--- Location: FF_X19_Y8_N43
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~109_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][14]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][14]~q\);
-
--- Location: LABCELL_X19_Y8_N45
-\myVirtualToplevel|TIMER:TIMER1|Add1~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~41_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~110\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~42\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~110\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][15]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~110\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~41_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~42\);
-
--- Location: MLABCELL_X18_Y8_N15
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15) & ( ((\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15) & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][15]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(15),
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11_combout\);
-
--- Location: FF_X18_Y8_N16
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~11_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\);
-
--- Location: FF_X19_Y8_N47
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~41_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][15]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][15]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N48
-\myVirtualToplevel|TIMER:TIMER1|Add1~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~45_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~42\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~46\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][16]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~42\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~45_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~46\);
-
--- Location: LABCELL_X20_Y8_N12
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111010000000001111101000000101111111110000010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][16]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12_combout\);
-
--- Location: FF_X20_Y8_N13
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~12_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\);
-
--- Location: FF_X19_Y8_N50
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~45_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][16]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][16]~q\);
-
--- Location: LABCELL_X19_Y8_N51
-\myVirtualToplevel|TIMER:TIMER1|Add1~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~65_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~46\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~66\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][17]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~46\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~65_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~66\);
-
--- Location: LABCELL_X20_Y8_N15
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\))) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\)) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000101101011110000010110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][17]~q\,
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17_combout\);
-
--- Location: FF_X20_Y8_N17
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~17_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\);
-
--- Location: FF_X19_Y8_N52
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~65_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][17]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][17]~q\);
-
--- Location: LABCELL_X19_Y8_N54
-\myVirtualToplevel|TIMER:TIMER1|Add1~117\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~117_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~66\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~118\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][18]~DUPLICATE_q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~66\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~117_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~118\);
-
--- Location: LABCELL_X17_Y8_N9
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][18]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30_combout\);
-
--- Location: FF_X17_Y8_N10
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~30_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\);
-
--- Location: FF_X19_Y8_N56
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~117_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][18]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][18]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y8_N57
-\myVirtualToplevel|TIMER:TIMER1|Add1~121\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~121_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~118\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~122\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~118\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][19]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~118\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~121_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~122\);
-
--- Location: LABCELL_X20_Y8_N0
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( (!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\))) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\)) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\ & ( \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000011111100110000001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\,
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][19]~q\,
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31_combout\);
-
--- Location: FF_X20_Y8_N1
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~31_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\);
-
--- Location: FF_X19_Y8_N59
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~121_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][19]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][19]~q\);
-
--- Location: LABCELL_X19_Y7_N0
-\myVirtualToplevel|TIMER:TIMER1|Add1~125\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~125_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~122\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~126\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~122\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][20]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~122\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~125_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~126\);
-
--- Location: MLABCELL_X18_Y7_N12
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][20]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32_combout\);
-
--- Location: FF_X18_Y7_N13
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~32_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\);
-
--- Location: FF_X19_Y7_N1
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~125_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][20]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][20]~q\);
-
--- Location: LABCELL_X19_Y7_N3
-\myVirtualToplevel|TIMER:TIMER1|Add1~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~25_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~126\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~26\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~126\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][21]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~126\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~25_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~26\);
-
--- Location: MLABCELL_X18_Y7_N54
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ & ( ((\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\ & \myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\)) #
--- (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ & ( (\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\ & ((!\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][0]~0_combout\) #
--- (!\myVirtualToplevel|TIMER:TIMER1|Mux2~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011101110000000001110111000010001111111110001000111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][0]~0_combout\,
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_Mux2~2_combout\,
- datad => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_limit[0][21]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\,
- combout => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7_combout\);
-
--- Location: FF_X18_Y7_N55
-\myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~7_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\);
-
--- Location: FF_X19_Y7_N5
-\myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|TIMER:TIMER1|Add1~25_sumout\,
- asdata => \myVirtualToplevel|TIMER:TIMER1|timer_limit[0][21]~q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|TIMER:TIMER1|Equal1~8_combout\,
- ena => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][21]~q\);
-
--- Location: LABCELL_X19_Y7_N6
-\myVirtualToplevel|TIMER:TIMER1|Add1~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|TIMER:TIMER1|Add1~61_sumout\ = SUM(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~26\ ))
--- \myVirtualToplevel|TIMER:TIMER1|Add1~62\ = CARRY(( \myVirtualToplevel|TIMER:TIMER1|timer_counter[0][22]~q\ ) + ( VCC ) + ( \myVirtualToplevel|TIMER:TIMER1|Add1~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_counter[0][22]~q\,
- cin => \myVirtualToplevel|TIMER:TIMER1|Add1~26\,
- sumout => \myVirtualToplevel|TIMER:TIMER1|Add1~61_sumout\,
- cout => \myVirtualToplevel|TIMER:TIMER1|Add1~62\);
-
--- Location: FF_X9_Y18_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_NEW_REG913\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]_OTERM914\);
-
--- Location: FF_X18_Y12_N5
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_NEW_REG72\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\);
-
--- Location: FF_X19_Y12_N14
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|Mux94~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y12_N57
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[6]_OTERM47\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\ ) ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\ ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]_OTERM73\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010101010101010101010000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[22]_OTERM73\,
- datad => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[6]_OTERM47\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[22]~6_combout\);
-
--- Location: LABCELL_X20_Y10_N45
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\ ) ) # (
--- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(6) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(6),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[22]~16_combout\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[6]~2_combout\);
-
--- Location: M10K_X22_Y12_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 6,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 6,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14_PORTBDATAOUT_bus\);
-
--- Location: M10K_X30_Y12_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002222222222200000000E1001F6FB3DEFDB8F177BBED818006E75B773EF6779FDEF7BDEBB5E99025400399DBEBBEF7F7AF77BD75F7DDEEEF7F57BFD7574005FFFE025C0B5B71FBA9F90D21E0190E87E1D9A4B38D848D81020C08334E7D2000000D6FD51EF4D2A70E7110E71D851261CBDC7869B07013CAA1F",
- mem_init2 => "208E646650468C2063EAE0D8293EFE990D82433E5743716891D9411A211CA0A7EB73C79B3AB6326CB2BC58B4B84A498AC2C291410208A41395AEA5228C948F9C0E414263D6C2AAADEBA15556F74C105E1E442532849E064A583ACE4624B04F4AE27494010465C9907827BE450CC9381B667B61B1D6A25BDE4C9796A454CF0709875E849A8089D01C2D6EE6441D50B51D50848538F5D2601258EED828E6A1F1614C125C6BC18B2D1C234A13FBC825CA048AD0F5CF4E8EA88B9F22E75417D25C0555356E9A7419D12D4B447A0A45654D14F51D0F18BA6974C25EA02688C2275BCA467C23D54390C62AAC4AA650A54C74848FF35E1C9453CC6DEC61D60E80A3A21D",
- mem_init1 => "13204000B01B4A0C528919E5C41C56A0D4DA13C909832EA93F314E481B0A69C4043525653286C2A468A2923A4C38FF6440630C4100A8BF11A6C214C7FA28C3312090CCCD42491E0202E792DF18928C3774166203EE886C56BE3049591180C03C5A48A14D4927C8852201EA28F09D2382FA8420540310B3A85046222C0F0CC884C7B2DBDC37E49A811485D0051D417F0E191E3451591BB905290D144B30582D802112101880A97215245B518CAEE72E25B2D14C4F03FA4D048AC40261251C4354982B99D4C7BE6288F28C2222804651C2850819410A1AA38528E18D4ADC95CCA88419C0504BF530201472B88C460A342BE2D712E100F504655B0CE75663088565",
- mem_init0 => "4B72C463C1AF521006BF82D0D7A1080A4C38DAC0394EF01A290C784C22008029D163F2618509059E3E80A93D999E54FAFDBF088A5662B8D05F854E0C015234E2A952414E7A70555304D48B01009197CB8A0CBF2496382B22643871E3C3862611F9D0A2416A34482D4689059400C0603010E22463CD652F24518B286745598306BA458C1038C6304500002A4924840E35D17181722FB97B6297424E090AA02AAC100504109894B0280042B4556265054008595140D8F2E000015402AAEAAAAEEEAAAAAAAAEEAEEEEE805500AA017402E8FFFFFFFFFFF8000000000000000000FEFB00000000000118684040051106010010000105010200000141012003110000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 6,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 6,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6_PORTBDATAOUT_bus\);
-
--- Location: MLABCELL_X18_Y12_N0
-\myVirtualToplevel|MEM_DATA_READ[22]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[22]~12_combout\ = ( \myVirtualToplevel|LessThan0~1_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6~portbdataout\ & (
--- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14~portbdataout\) ) ) ) # ( \myVirtualToplevel|LessThan0~1_combout\ & (
--- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a6~portbdataout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) &
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a14~portbdataout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000111100000000000000001111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0),
- datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a14~portbdataout\,
- datae => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a6~portbdataout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[22]~12_combout\);
-
--- Location: LABCELL_X12_Y9_N15
-\myVirtualToplevel|UART0|TX_ENABLE_FIFO~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_ENABLE_FIFO~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[17]~6_combout\,
- combout => \myVirtualToplevel|UART0|TX_ENABLE_FIFO~0_combout\);
-
--- Location: FF_X12_Y9_N17
-\myVirtualToplevel|UART0|TX_ENABLE_FIFO\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|TX_ENABLE_FIFO~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_ENABLE~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\);
-
--- Location: LABCELL_X10_Y8_N30
-\myVirtualToplevel|UART0|Add8~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add8~9_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|UART0|Add8~10\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0),
- cin => GND,
- sumout => \myVirtualToplevel|UART0|Add8~9_sumout\,
- cout => \myVirtualToplevel|UART0|Add8~10\);
-
--- Location: LABCELL_X12_Y9_N21
-\myVirtualToplevel|UART0|TX_RESET~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_RESET~0_combout\ = ( \myVirtualToplevel|UART0_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\))) ) ) # ( !\myVirtualToplevel|UART0_CS~combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111111010101111111111101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ALT_INV_UART0_CS~combout\,
- combout => \myVirtualToplevel|UART0|TX_RESET~0_combout\);
-
--- Location: FF_X12_Y9_N23
-\myVirtualToplevel|UART0|TX_RESET\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|TX_RESET~0_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_RESET~q\);
-
--- Location: LABCELL_X10_Y8_N24
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1_combout\ = !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000011111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0),
- combout => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1_combout\);
-
--- Location: LABCELL_X17_Y13_N6
-\myVirtualToplevel|Equal3~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Equal3~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(7) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(9) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[11]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(10) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[8]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000100000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(6),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[11]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(10),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[8]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(7),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(9),
- combout => \myVirtualToplevel|Equal3~1_combout\);
-
--- Location: LABCELL_X12_Y9_N12
-\myVirtualToplevel|UART0|TX_ENABLE~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_ENABLE~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\,
- combout => \myVirtualToplevel|UART0|TX_ENABLE~1_combout\);
-
--- Location: FF_X12_Y9_N14
-\myVirtualToplevel|UART0|TX_ENABLE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|TX_ENABLE~1_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_ENABLE~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_ENABLE~q\);
-
--- Location: LABCELL_X12_Y9_N36
-\myVirtualToplevel|UART0|TX_OVERRUN~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_OVERRUN~0_combout\ = ( !\myVirtualToplevel|UART0|TX_ENABLE~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_ENABLE~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100010000000000010001000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_ENABLE~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\,
- combout => \myVirtualToplevel|UART0|TX_OVERRUN~0_combout\);
-
--- Location: LABCELL_X14_Y13_N0
-\myVirtualToplevel|UART0|TX_OVERRUN~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\ = ( \myVirtualToplevel|Equal3~1_combout\ & ( \myVirtualToplevel|UART0|TX_OVERRUN~0_combout\ & ( (\myVirtualToplevel|IO_SELECT~0_combout\ & (\myVirtualToplevel|Equal3~0_combout\ &
--- (\myVirtualToplevel|IO_SELECT~2_combout\ & \myVirtualToplevel|IO_SELECT~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_IO_SELECT~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_Equal3~0_combout\,
- datac => \myVirtualToplevel|ALT_INV_IO_SELECT~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_IO_SELECT~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_Equal3~1_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~0_combout\,
- combout => \myVirtualToplevel|UART0|TX_OVERRUN~1_combout\);
-
--- Location: LABCELL_X12_Y8_N30
-\myVirtualToplevel|UART0|Add6~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add6~22\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0),
- cin => GND,
- cout => \myVirtualToplevel|UART0|Add6~22\);
-
--- Location: LABCELL_X12_Y8_N33
-\myVirtualToplevel|UART0|Add6~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add6~25_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~22\ ))
--- \myVirtualToplevel|UART0|Add6~26\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(1),
- cin => \myVirtualToplevel|UART0|Add6~22\,
- sumout => \myVirtualToplevel|UART0|Add6~25_sumout\,
- cout => \myVirtualToplevel|UART0|Add6~26\);
-
--- Location: LABCELL_X12_Y8_N36
-\myVirtualToplevel|UART0|Add6~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add6~29_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~26\ ))
--- \myVirtualToplevel|UART0|Add6~30\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(2),
- cin => \myVirtualToplevel|UART0|Add6~26\,
- sumout => \myVirtualToplevel|UART0|Add6~29_sumout\,
- cout => \myVirtualToplevel|UART0|Add6~30\);
-
--- Location: LABCELL_X12_Y8_N39
-\myVirtualToplevel|UART0|Add6~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add6~9_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~30\ ))
--- \myVirtualToplevel|UART0|Add6~10\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(3),
- cin => \myVirtualToplevel|UART0|Add6~30\,
- sumout => \myVirtualToplevel|UART0|Add6~9_sumout\,
- cout => \myVirtualToplevel|UART0|Add6~10\);
-
--- Location: LABCELL_X12_Y8_N42
-\myVirtualToplevel|UART0|Add6~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add6~13_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~10\ ))
--- \myVirtualToplevel|UART0|Add6~14\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(4),
- cin => \myVirtualToplevel|UART0|Add6~10\,
- sumout => \myVirtualToplevel|UART0|Add6~13_sumout\,
- cout => \myVirtualToplevel|UART0|Add6~14\);
-
--- Location: LABCELL_X12_Y8_N45
-\myVirtualToplevel|UART0|Add6~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add6~17_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~14\ ))
--- \myVirtualToplevel|UART0|Add6~18\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(5),
- cin => \myVirtualToplevel|UART0|Add6~14\,
- sumout => \myVirtualToplevel|UART0|Add6~17_sumout\,
- cout => \myVirtualToplevel|UART0|Add6~18\);
-
--- Location: LABCELL_X12_Y8_N48
-\myVirtualToplevel|UART0|Add6~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add6~1_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~18\ ))
--- \myVirtualToplevel|UART0|Add6~2\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(6),
- cin => \myVirtualToplevel|UART0|Add6~18\,
- sumout => \myVirtualToplevel|UART0|Add6~1_sumout\,
- cout => \myVirtualToplevel|UART0|Add6~2\);
-
--- Location: LABCELL_X10_Y8_N48
-\myVirtualToplevel|UART0|Add8~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add8~1_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~30\ ))
--- \myVirtualToplevel|UART0|Add8~2\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(6),
- cin => \myVirtualToplevel|UART0|Add8~30\,
- sumout => \myVirtualToplevel|UART0|Add8~1_sumout\,
- cout => \myVirtualToplevel|UART0|Add8~2\);
-
--- Location: LABCELL_X10_Y8_N51
-\myVirtualToplevel|UART0|Add8~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add8~5_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add8~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(7),
- cin => \myVirtualToplevel|UART0|Add8~2\,
- sumout => \myVirtualToplevel|UART0|Add8~5_sumout\);
-
--- Location: FF_X10_Y8_N53
-\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add8~5_sumout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7));
-
--- Location: LABCELL_X12_Y8_N51
-\myVirtualToplevel|UART0|Add6~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add6~5_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add6~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(7),
- cin => \myVirtualToplevel|UART0|Add6~2\,
- sumout => \myVirtualToplevel|UART0|Add6~5_sumout\);
-
--- Location: FF_X7_Y8_N4
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add7~13_sumout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\);
-
--- Location: LABCELL_X7_Y8_N0
-\myVirtualToplevel|UART0|Add7~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add7~9_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) ) + ( !VCC ))
--- \myVirtualToplevel|UART0|Add7~10\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) ) + ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0),
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1),
- cin => GND,
- sumout => \myVirtualToplevel|UART0|Add7~9_sumout\,
- cout => \myVirtualToplevel|UART0|Add7~10\);
-
--- Location: FF_X7_Y8_N1
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add7~9_sumout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1));
-
--- Location: LABCELL_X12_Y8_N54
-\myVirtualToplevel|UART0|Equal6~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal6~1_combout\ = ( \myVirtualToplevel|UART0|Add6~29_sumout\ & ( \myVirtualToplevel|UART0|Add6~25_sumout\ & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) &
--- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|UART0|Add6~29_sumout\ & ( \myVirtualToplevel|UART0|Add6~25_sumout\ & (
--- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) ) ) ) # (
--- \myVirtualToplevel|UART0|Add6~29_sumout\ & ( !\myVirtualToplevel|UART0|Add6~25_sumout\ & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) $
--- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|UART0|Add6~29_sumout\ & ( !\myVirtualToplevel|UART0|Add6~25_sumout\ & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) $ (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0110000000000000000001100000000000000000011000000000000000000110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0),
- datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0),
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1),
- datae => \myVirtualToplevel|UART0|ALT_INV_Add6~29_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_Add6~25_sumout\,
- combout => \myVirtualToplevel|UART0|Equal6~1_combout\);
-
--- Location: FF_X7_Y8_N13
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add7~25_sumout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\);
-
--- Location: LABCELL_X12_Y8_N24
-\myVirtualToplevel|UART0|Equal6~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal6~0_combout\ = ( \myVirtualToplevel|UART0|Add6~17_sumout\ & ( \myVirtualToplevel|UART0|Add6~9_sumout\ & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ &
--- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|UART0|Add6~13_sumout\)))) ) ) ) # ( !\myVirtualToplevel|UART0|Add6~17_sumout\ & ( \myVirtualToplevel|UART0|Add6~9_sumout\ & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) &
--- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|UART0|Add6~13_sumout\)))) ) ) ) # ( \myVirtualToplevel|UART0|Add6~17_sumout\ & ( !\myVirtualToplevel|UART0|Add6~9_sumout\ & (
--- (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|UART0|Add6~13_sumout\)))) ) ) ) # ( !\myVirtualToplevel|UART0|Add6~17_sumout\
--- & ( !\myVirtualToplevel|UART0|Add6~9_sumout\ & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) $ (\myVirtualToplevel|UART0|Add6~13_sumout\)))) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000001000001000000000001001000000000001000001000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3),
- datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\,
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4),
- datad => \myVirtualToplevel|UART0|ALT_INV_Add6~13_sumout\,
- datae => \myVirtualToplevel|UART0|ALT_INV_Add6~17_sumout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_Add6~9_sumout\,
- combout => \myVirtualToplevel|UART0|Equal6~0_combout\);
-
--- Location: LABCELL_X12_Y8_N0
-\myVirtualToplevel|UART0|Equal6~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal6~2_combout\ = ( \myVirtualToplevel|UART0|Equal6~1_combout\ & ( \myVirtualToplevel|UART0|Equal6~0_combout\ & ( (!\myVirtualToplevel|UART0|Add6~1_sumout\ & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) &
--- (!\myVirtualToplevel|UART0|Add6~5_sumout\ $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7))))) # (\myVirtualToplevel|UART0|Add6~1_sumout\ & (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) & (!\myVirtualToplevel|UART0|Add6~5_sumout\ $
--- (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001001000000001001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_Add6~1_sumout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6),
- datac => \myVirtualToplevel|UART0|ALT_INV_Add6~5_sumout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7),
- datae => \myVirtualToplevel|UART0|ALT_INV_Equal6~1_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_Equal6~0_combout\,
- combout => \myVirtualToplevel|UART0|Equal6~2_combout\);
-
--- Location: MLABCELL_X9_Y8_N18
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\ = ( !\myVirtualToplevel|UART0|Equal6~2_combout\ & ( (\myVirtualToplevel|UART0|TX_OVERRUN~1_combout\ & !\myVirtualToplevel|UART0|TX_ENABLE_FIFO~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_OVERRUN~1_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE_FIFO~q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_Equal6~2_combout\,
- combout => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\);
-
--- Location: FF_X10_Y8_N25
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~1_combout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0));
-
--- Location: LABCELL_X7_Y8_N3
-\myVirtualToplevel|UART0|Add7~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add7~13_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~10\ ))
--- \myVirtualToplevel|UART0|Add7~14\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(2) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(2),
- cin => \myVirtualToplevel|UART0|Add7~10\,
- sumout => \myVirtualToplevel|UART0|Add7~13_sumout\,
- cout => \myVirtualToplevel|UART0|Add7~14\);
-
--- Location: FF_X7_Y8_N5
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add7~13_sumout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(2));
-
--- Location: LABCELL_X7_Y8_N6
-\myVirtualToplevel|UART0|Add7~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add7~17_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~14\ ))
--- \myVirtualToplevel|UART0|Add7~18\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3),
- cin => \myVirtualToplevel|UART0|Add7~14\,
- sumout => \myVirtualToplevel|UART0|Add7~17_sumout\,
- cout => \myVirtualToplevel|UART0|Add7~18\);
-
--- Location: FF_X7_Y8_N7
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add7~17_sumout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3));
-
--- Location: LABCELL_X7_Y8_N9
-\myVirtualToplevel|UART0|Add7~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add7~21_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~18\ ))
--- \myVirtualToplevel|UART0|Add7~22\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4),
- cin => \myVirtualToplevel|UART0|Add7~18\,
- sumout => \myVirtualToplevel|UART0|Add7~21_sumout\,
- cout => \myVirtualToplevel|UART0|Add7~22\);
-
--- Location: FF_X7_Y8_N10
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add7~21_sumout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4));
-
--- Location: LABCELL_X7_Y8_N12
-\myVirtualToplevel|UART0|Add7~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add7~25_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~22\ ))
--- \myVirtualToplevel|UART0|Add7~26\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(5) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(5),
- cin => \myVirtualToplevel|UART0|Add7~22\,
- sumout => \myVirtualToplevel|UART0|Add7~25_sumout\,
- cout => \myVirtualToplevel|UART0|Add7~26\);
-
--- Location: FF_X7_Y8_N14
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add7~25_sumout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(5));
-
--- Location: LABCELL_X7_Y8_N15
-\myVirtualToplevel|UART0|Add7~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add7~1_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~26\ ))
--- \myVirtualToplevel|UART0|Add7~2\ = CARRY(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6),
- cin => \myVirtualToplevel|UART0|Add7~26\,
- sumout => \myVirtualToplevel|UART0|Add7~1_sumout\,
- cout => \myVirtualToplevel|UART0|Add7~2\);
-
--- Location: FF_X7_Y8_N17
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add7~1_sumout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6));
-
--- Location: LABCELL_X7_Y8_N18
-\myVirtualToplevel|UART0|Add7~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add7~5_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) ) + ( GND ) + ( \myVirtualToplevel|UART0|Add7~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7),
- cin => \myVirtualToplevel|UART0|Add7~2\,
- sumout => \myVirtualToplevel|UART0|Add7~5_sumout\);
-
--- Location: FF_X7_Y8_N19
-\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add7~5_sumout\,
- clrn => \myVirtualToplevel|UART0|TX_RESET~q\,
- ena => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7));
-
--- Location: MLABCELL_X9_Y8_N27
-\myVirtualToplevel|UART0|Equal5~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal5~0_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7) & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6)))) ) ) # (
--- !\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7) & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) & (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) $ (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000000001010101000000000101001010000000001010101000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7),
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6),
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(6),
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(7),
- combout => \myVirtualToplevel|UART0|Equal5~0_combout\);
-
--- Location: LABCELL_X10_Y8_N54
-\myVirtualToplevel|UART0|Equal5~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal5~1_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) & ( (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) &
--- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( \myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) & (
--- (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0))))) ) ) ) # (
--- \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) & (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0)
--- $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0))))) ) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ & ( !\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1) & ( (!\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) &
--- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000100000000010000000001001000000000100000000010000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1),
- datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0),
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(2),
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0),
- datae => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(1),
- combout => \myVirtualToplevel|UART0|Equal5~1_combout\);
-
--- Location: LABCELL_X10_Y8_N0
-\myVirtualToplevel|UART0|Equal5~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Equal5~2_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) & (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) &
--- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4))))) ) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & (
--- (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4))))) ) ) ) # ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & (
--- !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) & (\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) $
--- (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4))))) ) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) & ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ & ( (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5) &
--- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3) & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4) $ (\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000010000000000000000001000010000100001000000000000000000100001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(4),
- datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(5),
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4),
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(3),
- datae => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3),
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\,
- combout => \myVirtualToplevel|UART0|Equal5~2_combout\);
-
--- Location: LABCELL_X10_Y9_N0
-\myVirtualToplevel|UART0|Add0~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add0~37_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
--- \myVirtualToplevel|UART0|Add0~38\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(0) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(0),
- cin => GND,
- sumout => \myVirtualToplevel|UART0|Add0~37_sumout\,
- cout => \myVirtualToplevel|UART0|Add0~38\);
-
--- Location: LABCELL_X12_Y9_N27
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~4_combout\,
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4_combout\);
-
--- Location: FF_X12_Y9_N29
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(0));
-
--- Location: LABCELL_X12_Y9_N24
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell_combout\ = !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(0)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(0),
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell_combout\);
-
--- Location: LABCELL_X5_Y8_N51
-\myVirtualToplevel|UART0|TX_COUNTER~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_COUNTER~0_combout\ = ( \myVirtualToplevel|UART0|Equal0~4_combout\ & ( \myVirtualToplevel|UART0|TX_STATE~q\ ) ) # ( \myVirtualToplevel|UART0|Equal0~4_combout\ & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) ) # (
--- !\myVirtualToplevel|UART0|Equal0~4_combout\ & ( !\myVirtualToplevel|UART0|TX_STATE~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|UART0|ALT_INV_Equal0~4_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_STATE~q\,
- combout => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\);
-
--- Location: FF_X10_Y9_N2
-\myVirtualToplevel|UART0|TX_COUNTER[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add0~37_sumout\,
- asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[0]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_COUNTER\(0));
-
--- Location: LABCELL_X10_Y9_N3
-\myVirtualToplevel|UART0|Add0~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add0~21_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~38\ ))
--- \myVirtualToplevel|UART0|Add0~22\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(1) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(1),
- cin => \myVirtualToplevel|UART0|Add0~38\,
- sumout => \myVirtualToplevel|UART0|Add0~21_sumout\,
- cout => \myVirtualToplevel|UART0|Add0~22\);
-
--- Location: FF_X12_Y9_N52
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(1));
-
--- Location: FF_X10_Y9_N5
-\myVirtualToplevel|UART0|TX_COUNTER[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add0~21_sumout\,
- asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(1),
- sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_COUNTER\(1));
-
--- Location: LABCELL_X10_Y9_N6
-\myVirtualToplevel|UART0|Add0~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add0~25_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~22\ ))
--- \myVirtualToplevel|UART0|Add0~26\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(2) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(2),
- cin => \myVirtualToplevel|UART0|Add0~22\,
- sumout => \myVirtualToplevel|UART0|Add0~25_sumout\,
- cout => \myVirtualToplevel|UART0|Add0~26\);
-
--- Location: LABCELL_X12_Y9_N33
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[18]~5_combout\,
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2_combout\);
-
--- Location: FF_X12_Y9_N35
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~2_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(2));
-
--- Location: LABCELL_X12_Y9_N30
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(2) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(2),
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell_combout\);
-
--- Location: FF_X10_Y9_N8
-\myVirtualToplevel|UART0|TX_COUNTER[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add0~25_sumout\,
- asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[2]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_COUNTER\(2));
-
--- Location: LABCELL_X10_Y9_N9
-\myVirtualToplevel|UART0|Add0~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add0~29_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~26\ ))
--- \myVirtualToplevel|UART0|Add0~30\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|UART0|Add0~26\,
- sumout => \myVirtualToplevel|UART0|Add0~29_sumout\,
- cout => \myVirtualToplevel|UART0|Add0~30\);
-
--- Location: MLABCELL_X9_Y9_N18
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3_combout\ = !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[19]~19_combout\,
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3_combout\);
-
--- Location: FF_X9_Y9_N20
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~3_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(3));
-
--- Location: MLABCELL_X9_Y9_N21
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(3) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(3),
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell_combout\);
-
--- Location: FF_X10_Y9_N11
-\myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add0~29_sumout\,
- asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[3]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_COUNTER[3]~DUPLICATE_q\);
-
--- Location: LABCELL_X10_Y9_N12
-\myVirtualToplevel|UART0|Add0~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add0~49_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~30\ ))
--- \myVirtualToplevel|UART0|Add0~50\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(4) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(4),
- cin => \myVirtualToplevel|UART0|Add0~30\,
- sumout => \myVirtualToplevel|UART0|Add0~49_sumout\,
- cout => \myVirtualToplevel|UART0|Add0~50\);
-
--- Location: MLABCELL_X9_Y9_N9
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[20]~17_combout\,
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5_combout\);
-
--- Location: FF_X9_Y9_N11
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(4));
-
--- Location: MLABCELL_X9_Y9_N6
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(4) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(4),
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell_combout\);
-
--- Location: FF_X10_Y9_N14
-\myVirtualToplevel|UART0|TX_COUNTER[4]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add0~49_sumout\,
- asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[4]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_COUNTER\(4));
-
--- Location: LABCELL_X10_Y9_N15
-\myVirtualToplevel|UART0|Add0~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add0~53_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~50\ ))
--- \myVirtualToplevel|UART0|Add0~54\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(5) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(5),
- cin => \myVirtualToplevel|UART0|Add0~50\,
- sumout => \myVirtualToplevel|UART0|Add0~53_sumout\,
- cout => \myVirtualToplevel|UART0|Add0~54\);
-
--- Location: MLABCELL_X9_Y9_N39
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[21]~15_combout\,
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6_combout\);
-
--- Location: FF_X9_Y9_N41
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(5));
-
--- Location: MLABCELL_X9_Y9_N36
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell_combout\ = ( !\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(5) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_CLOCK_DIVISOR\(5),
- combout => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell_combout\);
-
--- Location: FF_X10_Y9_N17
-\myVirtualToplevel|UART0|TX_COUNTER[5]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add0~53_sumout\,
- asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[5]~_wirecell_combout\,
- sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_COUNTER\(5));
-
--- Location: LABCELL_X10_Y9_N18
-\myVirtualToplevel|UART0|Add0~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add0~1_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~54\ ))
--- \myVirtualToplevel|UART0|Add0~2\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(6) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(6),
- cin => \myVirtualToplevel|UART0|Add0~54\,
- sumout => \myVirtualToplevel|UART0|Add0~1_sumout\,
- cout => \myVirtualToplevel|UART0|Add0~2\);
-
--- Location: FF_X9_Y9_N55
-\myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR[7]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(6));
-
--- Location: FF_X10_Y9_N20
-\myVirtualToplevel|UART0|TX_COUNTER[6]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|Add0~1_sumout\,
- asdata => \myVirtualToplevel|UART0|TX_CLOCK_DIVISOR\(6),
- sload => \myVirtualToplevel|UART0|TX_COUNTER~0_combout\,
- ena => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|TX_COUNTER\(6));
-
--- Location: LABCELL_X10_Y9_N21
-\myVirtualToplevel|UART0|Add0~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|Add0~33_sumout\ = SUM(( \myVirtualToplevel|UART0|TX_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~2\ ))
--- \myVirtualToplevel|UART0|Add0~34\ = CARRY(( \myVirtualToplevel|UART0|TX_COUNTER\(7) ) + ( VCC ) + ( \myVirtualToplevel|UART0|Add0~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_COUNTER\(7),
- cin => \myVirtualToplevel|UART0|Add0~2\,
- sumout => \myVirtualToplevel|UART0|Add0~33_sumout\,
- cout => \myVirtualToplevel|UART0|Add0~34\);
-
--- Location: LABCELL_X19_Y17_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[23]~feeder_combout\);
-
--- Location: LABCELL_X16_Y29_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000010000000000000001000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\);
-
--- Location: LABCELL_X17_Y29_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000011000000000000001100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\);
-
--- Location: LABCELL_X17_Y27_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000100000000000000000000000000000000000000000000001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\);
-
--- Location: LABCELL_X17_Y27_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~4_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000010000000000000001000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\);
-
--- Location: LABCELL_X17_Y29_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100001001110010101111001111001100001100001001010100001111000010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\);
-
--- Location: LABCELL_X16_Y29_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101000100010000000000000000010101010001000000000001000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\);
-
--- Location: LABCELL_X16_Y29_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_RESYN12768_BDD12769\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011100000110000001100000011000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_RESYN12768_BDD12769\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\);
-
--- Location: LABCELL_X17_Y22_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000010110000000000001011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~7_combout\);
-
--- Location: MLABCELL_X18_Y28_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000101000000000000010001000000100000000000000011000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\);
-
--- Location: LABCELL_X17_Y24_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ & !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001010101000000000101010100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~9_combout\);
-
--- Location: MLABCELL_X18_Y27_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1001000000000000101000000000000010111000000000000100000000101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\);
-
--- Location: LABCELL_X17_Y26_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~8_combout\);
-
--- Location: LABCELL_X17_Y32_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~20_Duplicate_22\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux249~20_Duplicate_22\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000100000000000000010000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~20_Duplicate_22\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux249~20_Duplicate_22\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\);
-
--- Location: LABCELL_X17_Y28_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Equal141~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector499~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector973~6_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000000000000000000001111000011111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector973~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal141~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector499~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\);
-
--- Location: MLABCELL_X18_Y25_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000010000000000000001000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\);
-
--- Location: LABCELL_X16_Y24_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010111000011110000111101011111010111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector982~12_combout\);
-
--- Location: LABCELL_X19_Y17_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder_combout\);
-
--- Location: FF_X19_Y17_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[22]~feeder_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(22));
-
--- Location: FF_X18_Y17_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[22]~13_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(22));
-
--- Location: LABCELL_X19_Y17_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(22) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(22) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(22),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\);
-
--- Location: LABCELL_X21_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\
--- ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100000000000000000011000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~4_combout\);
-
--- Location: MLABCELL_X18_Y25_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000010000000000000001000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\);
-
--- Location: LABCELL_X16_Y9_N0
-\myVirtualToplevel|SD_ADDR[0][0]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_ADDR[0][0]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- combout => \myVirtualToplevel|SD_ADDR[0][0]~feeder_combout\);
-
--- Location: FF_X16_Y9_N1
-\myVirtualToplevel|SD_ADDR[0][0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_ADDR[0][0]~feeder_combout\,
- ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_ADDR[0][0]~q\);
-
--- Location: FF_X24_Y5_N16
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \SDCARD_MISO[0]~input_o\,
- sload => VCC,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o[3]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(0));
-
--- Location: LABCELL_X19_Y9_N6
-\myVirtualToplevel|Mux83~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux83~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(0) & ( (\myVirtualToplevel|SD_ADDR[0][0]~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|data_o\(0) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|SD_ADDR[0][0]~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001010000010100000101001011111010111110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datac => \myVirtualToplevel|ALT_INV_SD_ADDR[0][0]~q\,
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_data_o\(0),
- combout => \myVirtualToplevel|Mux83~0_combout\);
-
--- Location: FF_X19_Y9_N7
-\myVirtualToplevel|IO_DATA_READ_SD[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Mux83~0_combout\,
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3),
- ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SD\(0));
-
--- Location: FF_X13_Y12_N46
-\myVirtualToplevel|INT_ENABLE[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|INT_ENABLE[16]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|INT_ENABLE\(0));
-
--- Location: FF_X20_Y13_N14
-\myVirtualToplevel|IO_DATA_READ_INTRCTL[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|INT_ENABLE\(0),
- sclr => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- sload => VCC,
- ena => \myVirtualToplevel|IO_DATA_READ_INTRCTL[0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_INTRCTL\(0));
-
--- Location: LABCELL_X21_Y12_N36
-\myVirtualToplevel|Mux86~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux86~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010000010100000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- combout => \myVirtualToplevel|Mux86~0_combout\);
-
--- Location: LABCELL_X21_Y13_N48
-\myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder_combout\ = ( \myVirtualToplevel|Mux86~0_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ALT_INV_Mux86~0_combout\,
- combout => \myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder_combout\);
-
--- Location: FF_X21_Y13_N50
-\myVirtualToplevel|IO_DATA_READ_SOCCFG[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ_SOCCFG[0]~feeder_combout\,
- ena => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(0));
-
--- Location: LABCELL_X10_Y5_N0
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder_combout\ = \myVirtualToplevel|UART0|RX_BUFFER\(1)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(1),
- combout => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder_combout\);
-
--- Location: FF_X10_Y5_N1
-\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass[17]~feeder_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(17));
-
--- Location: FF_X10_Y5_N14
-\myVirtualToplevel|UART0|RX_FIFO~18\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|RX_BUFFER\(1),
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_FIFO~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_FIFO~18_q\);
-
--- Location: LABCELL_X10_Y5_N12
-\myVirtualToplevel|UART0|RX_DATA~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA~16_combout\ = ( \myVirtualToplevel|UART0|RX_BUFFER\(1) & ( \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ &
--- (\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\)) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & ((\myVirtualToplevel|UART0|RX_FIFO~18_q\))) ) ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(1) & (
--- \myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & (\myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\)) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ &
--- ((\myVirtualToplevel|UART0|RX_FIFO~18_q\))) ) ) ) # ( \myVirtualToplevel|UART0|RX_BUFFER\(1) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (\myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(17)) # (\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\) )
--- ) ) # ( !\myVirtualToplevel|UART0|RX_BUFFER\(1) & ( !\myVirtualToplevel|UART0|RX_DATA[7]~3_combout\ & ( (!\myVirtualToplevel|UART0|RX_DATA[7]~2_combout\ & \myVirtualToplevel|UART0|RX_FIFO_rtl_0_bypass\(17)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000100010011101110111011100001010010111110000101001011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~2_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO_rtl_0_bypass\(17),
- datac => \myVirtualToplevel|UART0|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_FIFO~18_q\,
- datae => \myVirtualToplevel|UART0|ALT_INV_RX_BUFFER\(1),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~3_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA~16_combout\);
-
--- Location: MLABCELL_X9_Y5_N3
-\myVirtualToplevel|UART0|RX_DATA[0]~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART0|RX_DATA[0]~17_combout\ = ( \myVirtualToplevel|UART0|RX_DATA~16_combout\ & ( ((\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\ & \myVirtualToplevel|UART0|RX_DATA[7]~0_combout\)) # (\myVirtualToplevel|UART0|RX_DATA\(0)) ) ) # (
--- !\myVirtualToplevel|UART0|RX_DATA~16_combout\ & ( (\myVirtualToplevel|UART0|RX_DATA\(0) & ((!\myVirtualToplevel|UART0|RX_DATA[0]~1_combout\) # (!\myVirtualToplevel|UART0|RX_DATA[7]~0_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111100000000001111110000000011111111110000001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[0]~1_combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_RX_DATA[7]~0_combout\,
- datad => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(0),
- dataf => \myVirtualToplevel|UART0|ALT_INV_RX_DATA~16_combout\,
- combout => \myVirtualToplevel|UART0|RX_DATA[0]~17_combout\);
-
--- Location: FF_X9_Y5_N5
-\myVirtualToplevel|UART0|RX_DATA[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART0|RX_DATA[0]~17_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_DATA\(0));
-
--- Location: FF_X10_Y6_N13
-\myVirtualToplevel|UART0|RX_EMPTY_V\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART0|Equal2~4_combout\,
- sload => VCC,
- ena => \myVirtualToplevel|UART0|RX_DATA[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART0|RX_EMPTY_V~q\);
-
--- Location: FF_X16_Y6_N56
-\myVirtualToplevel|UART1|RX_EMPTY_V\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|Equal2~4_combout\,
- ena => \myVirtualToplevel|UART1|RX_DATA[0]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_EMPTY_V~q\);
-
--- Location: FF_X14_Y6_N29
-\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_BUFFER\(1),
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(17));
-
--- Location: FF_X14_Y6_N44
-\myVirtualToplevel|UART1|RX_FIFO~18\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|UART1|RX_BUFFER\(1),
- sload => VCC,
- ena => \myVirtualToplevel|UART1|RX_FIFO~34_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_FIFO~18_q\);
-
--- Location: LABCELL_X14_Y6_N42
-\myVirtualToplevel|UART1|RX_DATA~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA~16_combout\ = ( \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ( \myVirtualToplevel|UART1|RX_BUFFER\(1) & ( (!\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ &
--- ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\))) # (\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART1|RX_FIFO~18_q\)) ) ) ) # ( !\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & (
--- \myVirtualToplevel|UART1|RX_BUFFER\(1) & ( (\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\) # (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(17)) ) ) ) # ( \myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ( !\myVirtualToplevel|UART1|RX_BUFFER\(1) & (
--- (!\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & ((\myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ram_block1a0~portbdataout\))) # (\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\ & (\myVirtualToplevel|UART1|RX_FIFO~18_q\)) ) ) ) # (
--- !\myVirtualToplevel|UART1|RX_DATA[0]~3_combout\ & ( !\myVirtualToplevel|UART1|RX_BUFFER\(1) & ( (\myVirtualToplevel|UART1|RX_FIFO_rtl_0_bypass\(17) & !\myVirtualToplevel|UART1|RX_DATA[0]~2_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010100000000000011110011001101010101111111110000111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO_rtl_0_bypass\(17),
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_FIFO~18_q\,
- datac => \myVirtualToplevel|UART1|RX_FIFO_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~2_combout\,
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~3_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_RX_BUFFER\(1),
- combout => \myVirtualToplevel|UART1|RX_DATA~16_combout\);
-
--- Location: MLABCELL_X13_Y6_N45
-\myVirtualToplevel|UART1|RX_DATA[0]~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|RX_DATA[0]~17_combout\ = (!\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & (((\myVirtualToplevel|UART1|RX_DATA\(0))))) # (\myVirtualToplevel|UART1|RX_DATA[0]~1_combout\ & ((!\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ &
--- ((\myVirtualToplevel|UART1|RX_DATA\(0)))) # (\myVirtualToplevel|UART1|RX_DATA[0]~0_combout\ & (\myVirtualToplevel|UART1|RX_DATA~16_combout\))))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111101111000000011110111100000001111011110000000111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~1_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_DATA[0]~0_combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_RX_DATA~16_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(0),
- combout => \myVirtualToplevel|UART1|RX_DATA[0]~17_combout\);
-
--- Location: FF_X13_Y6_N46
-\myVirtualToplevel|UART1|RX_DATA[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|UART1|RX_DATA[0]~17_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|UART1|RX_DATA\(0));
-
--- Location: LABCELL_X14_Y9_N42
-\myVirtualToplevel|IO_DATA_READ~92\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~92_combout\ = ( \myVirtualToplevel|UART1|RX_DATA\(0) & ( \myVirtualToplevel|UART1_CS~combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) #
--- (\myVirtualToplevel|UART1|RX_EMPTY_V~q\))) ) ) ) # ( !\myVirtualToplevel|UART1|RX_DATA\(0) & ( \myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|UART1|RX_EMPTY_V~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( \myVirtualToplevel|UART1|RX_DATA\(0) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|UART0|RX_EMPTY_V~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # (
--- !\myVirtualToplevel|UART1|RX_DATA\(0) & ( !\myVirtualToplevel|UART1_CS~combout\ & ( (\myVirtualToplevel|UART0|RX_EMPTY_V~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010100000000010101010000000000000011000000001111001100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_RX_EMPTY_V~q\,
- datab => \myVirtualToplevel|UART1|ALT_INV_RX_EMPTY_V~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datae => \myVirtualToplevel|UART1|ALT_INV_RX_DATA\(0),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|IO_DATA_READ~92_combout\);
-
--- Location: LABCELL_X7_Y11_N24
-\myVirtualToplevel|IO_DATA_READ~88\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~88_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( (\myVirtualToplevel|RTC_YEAR_COUNTER\(0) & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|RTC_HOUR_COUNTER\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- (!\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) # (\myVirtualToplevel|RTC_YEAR_COUNTER\(0)) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|RTC_MONTH_COUNTER\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((\myVirtualToplevel|RTC_HOUR_COUNTER\(0)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- (!\myVirtualToplevel|RTC_DAY_COUNTER[0]~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000011111100110111011101110100110000111111000001000100010001",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_RTC_YEAR_COUNTER\(0),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datac => \myVirtualToplevel|ALT_INV_RTC_DAY_COUNTER[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_RTC_HOUR_COUNTER\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MONTH_COUNTER\(0),
- combout => \myVirtualToplevel|IO_DATA_READ~88_combout\);
-
--- Location: FF_X13_Y12_N1
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~89_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\);
-
--- Location: FF_X12_Y12_N1
-\myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add19~41_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|SECOND_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|SECOND_DOWN_COUNTER[8]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE_q\);
-
--- Location: LABCELL_X16_Y11_N33
-\myVirtualToplevel|IO_DATA_READ~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~89_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|SECOND_DOWN_COUNTER[0]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MILLISEC_DOWN_COUNTER\(0) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(0) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011010101010101010100000000111111110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(0),
- datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_SECOND_DOWN_COUNTER[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_MILLISEC_DOWN_COUNTER\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- combout => \myVirtualToplevel|IO_DATA_READ~89_combout\);
-
--- Location: LABCELL_X10_Y12_N24
-\myVirtualToplevel|IO_DATA_READ~90\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~90_combout\ = ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(0) & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(0))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ((\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(0) & ( \myVirtualToplevel|RTC_MILLISEC_COUNTER\(0)
--- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- ((\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( \myVirtualToplevel|RTC_MINUTE_COUNTER\(0) & (
--- !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- ((\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))) ) ) ) # ( !\myVirtualToplevel|RTC_MINUTE_COUNTER\(0) & (
--- !\myVirtualToplevel|RTC_MILLISEC_COUNTER\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (\myVirtualToplevel|RTC_MICROSEC_COUNTER\(0))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) &
--- ((\myVirtualToplevel|RTC_SECOND_COUNTER[0]~DUPLICATE_q\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100000101010000110010011101101001100011011100101110101111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ALT_INV_RTC_MICROSEC_COUNTER\(0),
- datad => \myVirtualToplevel|ALT_INV_RTC_SECOND_COUNTER[0]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ALT_INV_RTC_MINUTE_COUNTER\(0),
- dataf => \myVirtualToplevel|ALT_INV_RTC_MILLISEC_COUNTER\(0),
- combout => \myVirtualToplevel|IO_DATA_READ~90_combout\);
-
--- Location: LABCELL_X14_Y11_N18
-\myVirtualToplevel|IO_DATA_READ~91\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~91_combout\ = ( \myVirtualToplevel|IO_DATA_READ~90_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5)) # (\myVirtualToplevel|IO_DATA_READ~89_combout\))))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (\myVirtualToplevel|IO_DATA_READ~88_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))))) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~90_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (((\myVirtualToplevel|IO_DATA_READ~89_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ &
--- (\myVirtualToplevel|IO_DATA_READ~88_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(5))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000010001000011000001000100001100110111010000110011011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ~88_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ~89_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(5),
- dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ~90_combout\,
- combout => \myVirtualToplevel|IO_DATA_READ~91_combout\);
-
--- Location: LABCELL_X14_Y9_N36
-\myVirtualToplevel|IO_DATA_READ~93\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~93_combout\ = ( \myVirtualToplevel|IO_DATA_READ~91_combout\ & ( \myVirtualToplevel|UART1|Add9~36_sumout\ & ( (!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\) # ((!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ &
--- ((\myVirtualToplevel|IO_DATA_READ~92_combout\))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(0)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~91_combout\ & ( \myVirtualToplevel|UART1|Add9~36_sumout\ & (
--- (!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & (((\myVirtualToplevel|IO_DATA_READ[0]~70_combout\)))) # (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ((!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ &
--- ((\myVirtualToplevel|IO_DATA_READ~92_combout\))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(0))))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ~91_combout\ & ( !\myVirtualToplevel|UART1|Add9~36_sumout\ & (
--- (!\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & (((!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\)))) # (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ((!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ &
--- ((\myVirtualToplevel|IO_DATA_READ~92_combout\))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(0))))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ~91_combout\ & ( !\myVirtualToplevel|UART1|Add9~36_sumout\ & (
--- (\myVirtualToplevel|IO_DATA_READ[0]~46_combout\ & ((!\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & ((\myVirtualToplevel|IO_DATA_READ~92_combout\))) # (\myVirtualToplevel|IO_DATA_READ[0]~70_combout\ & (\myVirtualToplevel|UART0|RX_DATA\(0))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000101010001101000011111000100001011010110111010101111111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~46_combout\,
- datab => \myVirtualToplevel|UART0|ALT_INV_RX_DATA\(0),
- datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[0]~70_combout\,
- datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ~92_combout\,
- datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~91_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Add9~36_sumout\,
- combout => \myVirtualToplevel|IO_DATA_READ~93_combout\);
-
--- Location: FF_X14_Y9_N37
-\myVirtualToplevel|IO_DATA_READ[0]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ~93_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ\(0));
-
--- Location: LABCELL_X20_Y13_N51
-\myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ = ( \myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ_SOCCFG\(0) ) ) # ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( \myVirtualToplevel|IO_DATA_READ\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(0),
- datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(0),
- dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\);
-
--- Location: LABCELL_X20_Y13_N12
-\myVirtualToplevel|MEM_DATA_READ[0]~94\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ = ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(0) & ( \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\) #
--- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(0) & ( \myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ & (
--- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\) # ((!\myVirtualToplevel|IO_SELECT~combout\)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ &
--- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_INTRCTL\(0) & ( !\myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ & (
--- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|IO_SELECT~combout\)) # (\myVirtualToplevel|INTR0_CS~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ &
--- (((\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_INTRCTL\(0) & ( !\myVirtualToplevel|MEM_DATA_READ[0]~94_RESYN8743_BDD8744\ & (
--- (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((!\myVirtualToplevel|IO_SELECT~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000110011111101010011001111111010001100111111111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\,
- datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\,
- datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_INTRCTL\(0),
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_RESYN8743_BDD8744\,
- combout => \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\);
-
--- Location: M10K_X22_Y19_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E01150A0426087860C0AA494890000246582636303300842108410401308000015508E71653D19FB292449355A00509140015554007FFFFFFFA00034C1083D04909C201208CC33100130A088C840A182873EE413FF557F7354AA0A17ABD572128F79FE54806CFC2A4282A7451EB34F",
- mem_init2 => "47567802628B140805C870046E1F3E134040F02E53F210D86CE98E6C516CC56EF269E39313622A9AB5F13C7AC63962CDE388416981100703C08DE3038A8E9468C3541359E8534C13F429F60979BBF3A94DED9F8902AA40530B07C25FEDB9B92F9BB6B7EDB6F4E9C2E3109F331BA0C0FC2AE7BDAD05E857C1A9BDBC2A6AA5F09C7CA21BF70F4C09E72B894E7250094290096A7308E3D104C0BD3FC42E564008E953952661A151C383EAE800E7A635E34FEA9A63DC07B7AE6402037392B0C856506175288C32E6ED86D6C67CAB55353D603D60ED874FD91E1C7A00164733B3ADD2012EBA6E3048A9881DBDF6AA912312E067ED760FC8F1AB14E5312284C221950C",
- mem_init1 => "B1C888705767256D982A1DF0888FA7A0663822622E948625171286A2020E30C2461C81BAB4E22C38706E15008528BC64205195447F4A0194AA6BC265F50546998B625061D865C917C6691BA4644032202F6871F18686A2125BCE228E48AA54453B177DE4C4203B433181E500799583EADE6449760028781C1112519959C5EC7990B5C05A0DF4E5F5E27CA8E00BA19A8FC84E676AE7AEE84AD45D254CF81E84A1F2AF138A24004C805133D0875775961A687C0421A9D8E45048BABE108E2E10C80B80C06C190F635029CB133081A64082001E5E3C022761D4D8CCE0A409CAD3C02A11C625C4AF0600E96D2A6E61105288F2638DB9C44283A219C2F99319259FFB",
- mem_init0 => "C4051351F98A3EA90243245DC529548AEAA2896C0C9811ED099B282F1B55C4C6D246AB48D0817207390A4490D0CE671397E9E6F82739C318529DB38A91C2B5078D26C401A5D6B3EB53121A22B609C386C8D49B925B1BDDADB5A3468F1E3ED1400638D18C1D103183A2063066941A0D068244106B0581BD4228336302B220BC1D540DF04AAC04215295543124D7DAAD9AAB58D8E1BBC682BC84392E87A5434451492802A2254A0840833100A68900129066263920279B1C8011A223444444444444444444444444444468885100A22145FFFFFFFFFFFB6DA4936DA4936DA492FEFF0000000000006D450606120600030101092F1906010000035103036E0E0000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram0_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM0_rtl_0|altsyncram_d902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 0,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 0,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|decode2|eq_node\(0),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);
-
--- Location: LABCELL_X19_Y16_N0
-\myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ = ( !\myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (\myVirtualToplevel|IO_DATA_READ_SD\(0) &
--- (((\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ &
--- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a0~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\)))))) ) ) # (
--- \myVirtualToplevel|MEM_DATA_READ[0]~94_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\ & ((((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\))) # (\myVirtualToplevel|IO_DATA_READ_SD\(0)))) # (\myVirtualToplevel|MEM_DATA_READ[10]~2_combout\
--- & (((!\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a8~portbdataout\)) # (\myVirtualToplevel|MEM_DATA_READ[10]~1_combout\ &
--- ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[0]~34_combout\)))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "on",
- lut_mask => "0000010100100010101011110010001000000101011101111010111101110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~2_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(0),
- datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[10]~1_combout\,
- datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~94_combout\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[0]~34_combout\,
- datag => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\);
-
--- Location: MLABCELL_X18_Y16_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Selector351~0_combout\) # ((\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\)) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ & ( (\myVirtualToplevel|MEM_DATA_READ[16]~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~5_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011111100001111001100000000001100111111000011110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[16]~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector351~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~5_combout\,
- datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~95_Duplicate_161\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\);
-
--- Location: LABCELL_X17_Y12_N30
-\myVirtualToplevel|IO_DATA_READ[26]~78\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[26]~78_combout\ = ( \myVirtualToplevel|INTR0_CS~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & \myVirtualToplevel|TIMER0_CS~2_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000010100000000000001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datad => \myVirtualToplevel|ALT_INV_TIMER0_CS~2_combout\,
- dataf => \myVirtualToplevel|ALT_INV_INTR0_CS~0_combout\,
- combout => \myVirtualToplevel|IO_DATA_READ[26]~78_combout\);
-
--- Location: LABCELL_X14_Y10_N6
-\myVirtualToplevel|IO_DATA_READ[24]~86\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[24]~86_combout\ = ( \myVirtualToplevel|UART0_CS~combout\ & ( !\myVirtualToplevel|TIMER0_CS~1_combout\ & ( (!\myVirtualToplevel|UART0|TX_RESET~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) ) # (
--- !\myVirtualToplevel|UART0_CS~combout\ & ( !\myVirtualToplevel|TIMER0_CS~1_combout\ & ( (!\myVirtualToplevel|UART1|TX_RESET~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001010101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_RESET~q\,
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_RESET~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datae => \myVirtualToplevel|ALT_INV_UART0_CS~combout\,
- dataf => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\,
- combout => \myVirtualToplevel|IO_DATA_READ[24]~86_combout\);
-
--- Location: LABCELL_X17_Y11_N21
-\myVirtualToplevel|Add17~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~73_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add17~70\ ))
--- \myVirtualToplevel|Add17~74\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(7) ) + ( GND ) + ( \myVirtualToplevel|Add17~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(7),
- cin => \myVirtualToplevel|Add17~70\,
- sumout => \myVirtualToplevel|Add17~73_sumout\,
- cout => \myVirtualToplevel|Add17~74\);
-
--- Location: FF_X17_Y11_N23
-\myVirtualToplevel|MILLISEC_UP_COUNTER[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~73_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(7));
-
--- Location: LABCELL_X17_Y11_N24
-\myVirtualToplevel|Add17~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~77_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~74\ ))
--- \myVirtualToplevel|Add17~78\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[8]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add17~74\,
- sumout => \myVirtualToplevel|Add17~77_sumout\,
- cout => \myVirtualToplevel|Add17~78\);
-
--- Location: FF_X17_Y11_N26
-\myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~77_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER[8]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y11_N27
-\myVirtualToplevel|Add17~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~57_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(9) ) + ( GND ) + ( \myVirtualToplevel|Add17~78\ ))
--- \myVirtualToplevel|Add17~58\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(9) ) + ( GND ) + ( \myVirtualToplevel|Add17~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(9),
- cin => \myVirtualToplevel|Add17~78\,
- sumout => \myVirtualToplevel|Add17~57_sumout\,
- cout => \myVirtualToplevel|Add17~58\);
-
--- Location: FF_X17_Y11_N29
-\myVirtualToplevel|MILLISEC_UP_COUNTER[9]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~57_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[9]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(9));
-
--- Location: LABCELL_X17_Y11_N30
-\myVirtualToplevel|Add17~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~61_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(10) ) + ( GND ) + ( \myVirtualToplevel|Add17~58\ ))
--- \myVirtualToplevel|Add17~62\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(10) ) + ( GND ) + ( \myVirtualToplevel|Add17~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(10),
- cin => \myVirtualToplevel|Add17~58\,
- sumout => \myVirtualToplevel|Add17~61_sumout\,
- cout => \myVirtualToplevel|Add17~62\);
-
--- Location: FF_X17_Y11_N32
-\myVirtualToplevel|MILLISEC_UP_COUNTER[10]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~61_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(10),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(10));
-
--- Location: LABCELL_X17_Y11_N33
-\myVirtualToplevel|Add17~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~65_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(11) ) + ( GND ) + ( \myVirtualToplevel|Add17~62\ ))
--- \myVirtualToplevel|Add17~66\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(11) ) + ( GND ) + ( \myVirtualToplevel|Add17~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(11),
- cin => \myVirtualToplevel|Add17~62\,
- sumout => \myVirtualToplevel|Add17~65_sumout\,
- cout => \myVirtualToplevel|Add17~66\);
-
--- Location: FF_X17_Y11_N35
-\myVirtualToplevel|MILLISEC_UP_COUNTER[11]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~65_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(11),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(11));
-
--- Location: LABCELL_X17_Y11_N36
-\myVirtualToplevel|Add17~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~33_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~66\ ))
--- \myVirtualToplevel|Add17~34\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add17~66\,
- sumout => \myVirtualToplevel|Add17~33_sumout\,
- cout => \myVirtualToplevel|Add17~34\);
-
--- Location: FF_X17_Y11_N38
-\myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~33_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(12),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER[12]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y11_N39
-\myVirtualToplevel|Add17~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~37_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(13) ) + ( GND ) + ( \myVirtualToplevel|Add17~34\ ))
--- \myVirtualToplevel|Add17~38\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(13) ) + ( GND ) + ( \myVirtualToplevel|Add17~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(13),
- cin => \myVirtualToplevel|Add17~34\,
- sumout => \myVirtualToplevel|Add17~37_sumout\,
- cout => \myVirtualToplevel|Add17~38\);
-
--- Location: FF_X17_Y11_N41
-\myVirtualToplevel|MILLISEC_UP_COUNTER[13]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~37_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(13),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(13));
-
--- Location: LABCELL_X17_Y11_N42
-\myVirtualToplevel|Add17~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~41_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(14) ) + ( GND ) + ( \myVirtualToplevel|Add17~38\ ))
--- \myVirtualToplevel|Add17~42\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(14) ) + ( GND ) + ( \myVirtualToplevel|Add17~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(14),
- cin => \myVirtualToplevel|Add17~38\,
- sumout => \myVirtualToplevel|Add17~41_sumout\,
- cout => \myVirtualToplevel|Add17~42\);
-
--- Location: FF_X17_Y11_N44
-\myVirtualToplevel|MILLISEC_UP_COUNTER[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~41_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[14]~DUPLICATE_q\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(14));
-
--- Location: LABCELL_X17_Y11_N45
-\myVirtualToplevel|Add17~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~45_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~42\ ))
--- \myVirtualToplevel|Add17~46\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[15]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add17~42\,
- sumout => \myVirtualToplevel|Add17~45_sumout\,
- cout => \myVirtualToplevel|Add17~46\);
-
--- Location: FF_X17_Y11_N47
-\myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~45_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(15),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER[15]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y11_N48
-\myVirtualToplevel|Add17~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~1_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(16) ) + ( GND ) + ( \myVirtualToplevel|Add17~46\ ))
--- \myVirtualToplevel|Add17~2\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(16) ) + ( GND ) + ( \myVirtualToplevel|Add17~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(16),
- cin => \myVirtualToplevel|Add17~46\,
- sumout => \myVirtualToplevel|Add17~1_sumout\,
- cout => \myVirtualToplevel|Add17~2\);
-
--- Location: FF_X17_Y11_N50
-\myVirtualToplevel|MILLISEC_UP_COUNTER[16]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~1_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~4_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(16));
-
--- Location: LABCELL_X17_Y11_N51
-\myVirtualToplevel|Add17~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~21_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(17) ) + ( GND ) + ( \myVirtualToplevel|Add17~2\ ))
--- \myVirtualToplevel|Add17~22\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(17) ) + ( GND ) + ( \myVirtualToplevel|Add17~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(17),
- cin => \myVirtualToplevel|Add17~2\,
- sumout => \myVirtualToplevel|Add17~21_sumout\,
- cout => \myVirtualToplevel|Add17~22\);
-
--- Location: FF_X17_Y11_N52
-\myVirtualToplevel|MILLISEC_UP_COUNTER[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~21_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[17]~6_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(17));
-
--- Location: LABCELL_X17_Y11_N54
-\myVirtualToplevel|Add17~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~25_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~22\ ))
--- \myVirtualToplevel|Add17~26\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[18]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add17~22\,
- sumout => \myVirtualToplevel|Add17~25_sumout\,
- cout => \myVirtualToplevel|Add17~26\);
-
--- Location: FF_X17_Y11_N56
-\myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~25_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[18]~5_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER[18]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y11_N57
-\myVirtualToplevel|Add17~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~29_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~26\ ))
--- \myVirtualToplevel|Add17~30\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[19]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add17~26\,
- sumout => \myVirtualToplevel|Add17~29_sumout\,
- cout => \myVirtualToplevel|Add17~30\);
-
--- Location: FF_X17_Y11_N59
-\myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~29_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER[19]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y10_N0
-\myVirtualToplevel|Add17~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~13_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~30\ ))
--- \myVirtualToplevel|Add17~14\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[20]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add17~30\,
- sumout => \myVirtualToplevel|Add17~13_sumout\,
- cout => \myVirtualToplevel|Add17~14\);
-
--- Location: FF_X17_Y10_N2
-\myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~13_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER[20]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y10_N3
-\myVirtualToplevel|Add17~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~5_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~14\ ))
--- \myVirtualToplevel|Add17~6\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[21]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add17~14\,
- sumout => \myVirtualToplevel|Add17~5_sumout\,
- cout => \myVirtualToplevel|Add17~6\);
-
--- Location: FF_X17_Y10_N5
-\myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~5_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER[21]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y10_N6
-\myVirtualToplevel|Add17~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~9_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(22) ) + ( GND ) + ( \myVirtualToplevel|Add17~6\ ))
--- \myVirtualToplevel|Add17~10\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(22) ) + ( GND ) + ( \myVirtualToplevel|Add17~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(22),
- cin => \myVirtualToplevel|Add17~6\,
- sumout => \myVirtualToplevel|Add17~9_sumout\,
- cout => \myVirtualToplevel|Add17~10\);
-
--- Location: FF_X17_Y10_N7
-\myVirtualToplevel|MILLISEC_UP_COUNTER[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~9_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(22));
-
--- Location: LABCELL_X17_Y10_N9
-\myVirtualToplevel|Add17~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~17_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(23) ) + ( GND ) + ( \myVirtualToplevel|Add17~10\ ))
--- \myVirtualToplevel|Add17~18\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(23) ) + ( GND ) + ( \myVirtualToplevel|Add17~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(23),
- cin => \myVirtualToplevel|Add17~10\,
- sumout => \myVirtualToplevel|Add17~17_sumout\,
- cout => \myVirtualToplevel|Add17~18\);
-
--- Location: FF_X17_Y10_N11
-\myVirtualToplevel|MILLISEC_UP_COUNTER[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~17_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(23));
-
--- Location: LABCELL_X17_Y10_N12
-\myVirtualToplevel|Add17~121\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~121_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(24) ) + ( GND ) + ( \myVirtualToplevel|Add17~18\ ))
--- \myVirtualToplevel|Add17~122\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(24) ) + ( GND ) + ( \myVirtualToplevel|Add17~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(24),
- cin => \myVirtualToplevel|Add17~18\,
- sumout => \myVirtualToplevel|Add17~121_sumout\,
- cout => \myVirtualToplevel|Add17~122\);
-
--- Location: FF_X18_Y16_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(24));
-
--- Location: FF_X19_Y18_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(24));
-
--- Location: LABCELL_X19_Y18_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(24) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(24) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(24),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\);
-
--- Location: LABCELL_X6_Y22_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_NEW3035\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_OTERM3036\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_OTERM3036\);
-
--- Location: FF_X6_Y22_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[24]_OTERM3036\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24));
-
--- Location: LABCELL_X6_Y22_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_NEW3163\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_OTERM3164\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_OTERM3164\);
-
--- Location: FF_X6_Y22_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[24]_OTERM3164\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24));
-
--- Location: LABCELL_X12_Y22_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_NEW2971\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_OTERM2972\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010001000000111101110111001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_OTERM2972\);
-
--- Location: FF_X12_Y22_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[24]_OTERM2972\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24));
-
--- Location: LABCELL_X6_Y22_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_NEW3099\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_OTERM3100\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_OTERM3100\);
-
--- Location: FF_X6_Y22_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[24]_OTERM3100\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24));
-
--- Location: LABCELL_X6_Y22_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(24) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(24) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(24))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110001000100000011000111011100111111010001000011111101110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(24),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(24),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(24),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0_combout\);
-
--- Location: LABCELL_X6_Y22_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_NEW2715\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_OTERM2716\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000111011111111100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_OTERM2716\);
-
--- Location: FF_X6_Y22_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[24]_OTERM2716\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24));
-
--- Location: LABCELL_X6_Y22_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_NEW2843\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_OTERM2844\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(24) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_OTERM2844\);
-
--- Location: FF_X6_Y22_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[24]_OTERM2844\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(24));
-
--- Location: LABCELL_X12_Y22_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_NEW2907\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_OTERM2908\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010000000100111101110011011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_OTERM2908\);
-
--- Location: FF_X12_Y22_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[24]_OTERM2908\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24));
-
--- Location: LABCELL_X6_Y22_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_NEW2779\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_OTERM2780\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_OTERM2780\);
-
--- Location: FF_X6_Y22_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[24]_OTERM2780\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24));
-
--- Location: LABCELL_X6_Y22_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(24)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(24) & !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(24) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(24)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(24))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111101010101001100110000000000001111010101010011001111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(24),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(24),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(24),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(24),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1_combout\);
-
--- Location: LABCELL_X6_Y22_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~0_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\);
-
--- Location: LABCELL_X10_Y14_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24))))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux18~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110011000000001111001100000101111101110000010111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux18~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22_combout\);
-
--- Location: FF_X10_Y14_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[24]~22_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24));
-
--- Location: FF_X17_Y10_N14
-\myVirtualToplevel|MILLISEC_UP_COUNTER[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~121_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(24));
-
--- Location: LABCELL_X17_Y10_N57
-\myVirtualToplevel|IO_DATA_READ[24]~87\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ[24]~87_combout\ = ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(24) & ( (((!\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|UART1|Mux0~0_combout\)) # (\myVirtualToplevel|IO_DATA_READ[24]~86_combout\)) #
--- (\myVirtualToplevel|IO_DATA_READ[26]~78_combout\) ) ) # ( !\myVirtualToplevel|MILLISEC_UP_COUNTER\(24) & ( ((!\myVirtualToplevel|TIMER0_CS~1_combout\ & \myVirtualToplevel|UART1|Mux0~0_combout\)) # (\myVirtualToplevel|IO_DATA_READ[24]~86_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111111001111000011111100111101011111110111110101111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[26]~78_combout\,
- datab => \myVirtualToplevel|ALT_INV_TIMER0_CS~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[24]~86_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Mux0~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(24),
- combout => \myVirtualToplevel|IO_DATA_READ[24]~87_combout\);
-
--- Location: FF_X17_Y10_N58
-\myVirtualToplevel|IO_DATA_READ[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ[24]~87_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ\(24));
-
--- Location: LABCELL_X21_Y12_N27
-\myVirtualToplevel|Mux87~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux87~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) $
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000011000000001100001100000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[6]~DUPLICATE_q\,
- combout => \myVirtualToplevel|Mux87~0_combout\);
-
--- Location: FF_X18_Y12_N14
-\myVirtualToplevel|IO_DATA_READ_SOCCFG[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|Mux87~0_combout\,
- sload => VCC,
- ena => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(24));
-
--- Location: LABCELL_X24_Y9_N6
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) &
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\) ) ) ) # ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & (
--- (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\) ) ) ) # ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8) & (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & ( (!\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\) # (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0)) ) ) ) # (
--- !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8) & ( !\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector3~1_combout\ & ( (\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(0) & \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v~84_combout\) ) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111111111110000111100000000000011110000000000001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_rx_v\(0),
- datad => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v~84_combout\,
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(8),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_Selector3~1_combout\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0_combout\);
-
--- Location: FF_X24_Y9_N7
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[8]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector7~0_combout\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8));
-
--- Location: LABCELL_X21_Y9_N45
-\myVirtualToplevel|IO_DATA_READ_SD[24]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ_SD[24]~feeder_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(8) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(8),
- combout => \myVirtualToplevel|IO_DATA_READ_SD[24]~feeder_combout\);
-
--- Location: LABCELL_X16_Y9_N57
-\myVirtualToplevel|SD_ADDR[0][24]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SD_ADDR[0][24]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24),
- combout => \myVirtualToplevel|SD_ADDR[0][24]~feeder_combout\);
-
--- Location: FF_X16_Y9_N58
-\myVirtualToplevel|SD_ADDR[0][24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SD_ADDR[0][24]~feeder_combout\,
- ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_ADDR[0][24]~q\);
-
--- Location: FF_X21_Y9_N46
-\myVirtualToplevel|IO_DATA_READ_SD[24]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ_SD[24]~feeder_combout\,
- asdata => \myVirtualToplevel|SD_ADDR[0][24]~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SD\(24));
-
--- Location: LABCELL_X20_Y12_N9
-\myVirtualToplevel|MEM_DATA_READ[18]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ = ( !\myVirtualToplevel|SOCCFG_CS~combout\ & ( !\myVirtualToplevel|SD_CS~combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_SD_CS~combout\,
- dataf => \myVirtualToplevel|ALT_INV_SOCCFG_CS~combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\);
-
--- Location: MLABCELL_X18_Y12_N42
-\myVirtualToplevel|MEM_DATA_READ[24]~60\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\ = ( \myVirtualToplevel|IO_DATA_READ_SD\(24) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((!\myVirtualToplevel|INTR0_CS~combout\))) #
--- (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ\(24))) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SD\(24) & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ &
--- ((!\myVirtualToplevel|INTR0_CS~combout\))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ\(24))) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ_SD\(24) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & (
--- (\myVirtualToplevel|IO_DATA_READ_SOCCFG\(24)) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) ) ) ) # ( !\myVirtualToplevel|IO_DATA_READ_SD\(24) & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\
--- & \myVirtualToplevel|IO_DATA_READ_SOCCFG\(24)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000011111111111111000101110001011100010111000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ\(24),
- datab => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\,
- datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(24),
- datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(24),
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\);
-
--- Location: FF_X18_Y12_N49
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG14\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM15\);
-
--- Location: IOIBUF_X19_Y0_N1
-\SDRAM_DQ[8]~input\ : cyclonev_io_ibuf
--- pragma translate_off
-GENERIC MAP (
- bus_hold => "false",
- simulate_z_as => "z")
--- pragma translate_on
-PORT MAP (
- i => SDRAM_DQ(8),
- o => \SDRAM_DQ[8]~input_o\);
-
--- Location: DDIOINCELL_X19_Y0_N14
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_NEW_REG16\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- d => \SDRAM_DQ[8]~input_o\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\);
-
--- Location: MLABCELL_X18_Y12_N33
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM15\)) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM17\))) ) ) # (
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM15\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100100111001001110010011100100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM15\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM17\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\);
-
--- Location: MLABCELL_X13_Y14_N42
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(0) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(1) &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000011100000111000001110000011101000111010001110100011101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(0),
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\);
-
--- Location: MLABCELL_X23_Y14_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node[1]\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1) = ( \myVirtualToplevel|BRAM_WREN~1_combout\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & \myVirtualToplevel|LessThan3~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001000100010001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\,
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\,
- datae => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~1_combout\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1));
-
--- Location: MLABCELL_X23_Y14_N48
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\ = ( \myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & ( ((!\myVirtualToplevel|BRAM_WREN~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16) &
--- !\myVirtualToplevel|LessThan3~0_combout\))) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\) ) ) # ( !\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & ( ((!\myVirtualToplevel|BRAM_WREN~1_combout\) #
--- (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111011111110111111101111111011111110111111100111111011111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16),
- datab => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~1_combout\,
- datac => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\,
- datad => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\,
- dataf => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\);
-
--- Location: MLABCELL_X9_Y14_N12
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(0) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_BYTE~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(24))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_WRITE_HWORD~q\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(8))))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000110011000010100011001101011111001100110101111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_BYTE~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(8),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(24),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_WRITE_HWORD~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(0),
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_DATA[0]~7_combout\);
-
--- Location: M10K_X11_Y11_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 0,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 0,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(1),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8_PORTBDATAOUT_bus\);
-
--- Location: MLABCELL_X23_Y14_N6
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node[0]\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0) = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[15]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~1_combout\ & ( (\myVirtualToplevel|BRAM_WREN~1_combout\
--- & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(16)) # ((\myVirtualToplevel|TIMER:TIMER1|timer_enabled[0]~0_combout\ & \myVirtualToplevel|LessThan3~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001000100011000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(16),
- datab => \myVirtualToplevel|ALT_INV_BRAM_WREN~1_combout\,
- datac => \myVirtualToplevel|TIMER:TIMER1|ALT_INV_timer_enabled[0]~0_combout\,
- datad => \myVirtualToplevel|ALT_INV_LessThan3~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[15]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~1_combout\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0));
-
--- Location: M10K_X3_Y16_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002222222222222222222225EE180094DF70AC92870E1012A0B9298830E70349C349EB5A5294920530228084B31D8412A832522A0165C851C24404C1221D7800126000006D80A5701F9A248070260110F80604BA090B8BC3DB060D59B129E7D2000000E71451DA8C61D10239DCE7B92932949D02063D191B899C11",
- mem_init2 => "E6CC54F457669496FB05EDE4887C72BF1E09D7D96FD7929873D1D59E1098A2C510D22F3E3C746398EFA266C484B8D493024C4221831044B5CDF79DAA18B1B9DD030D46BCA69961EA53ECB1F5229C0F3A9D807D0480174C211443546B67F139B7BB2C4BFEDFB870DB946F948380DCA7C7251CDC1091C42C38D92E2F8C5C568F13DEDE75AC775782D29A1915C4B10280B10276536607BD6E38FE1100D6926061B835A772D963C4161746009690E8E987F016EC2637C0E291E236A88E2BF3F63E230CCE493CFFDD19A38C598BB8A88A328957DDD716A472E0670E3A0A2EE4A00204416A29B8D66546B7001A8BA973EE912A8076B710E1871EE1EAE08B9E227570B8",
- mem_init1 => "5DA568E101D611104934107CE4BB82DF2D1F3A3244904E404A7F5E5A2290F3FC006C449524CE6130341226441BC0D508A997038520227061B772CC8C8947F14F7265C59C1B2C3C010907C9DF5501834E6341042AC8AD9D87378AEAFC5180D87C30911C2EA291298E154104EC0F4C4AA2F0A000B227C85B882C4E8895569704F11407CC0E17012B3E5B1DEF421A60BAC4609F0603CB5C0262BA8E29C848724D35FA0AFFB3C418F80808D891F79AC56AE964C54E0623110B55D64A7921249E4EF062903A7587285AA5F2172804FEAD048628106CD5801493A99943B91286230A138BA6809A1244744EA7DA8298FD4D00CE02CC99820493465839BCE004B2B2CA72",
- mem_init0 => "8122000836C14C0875058DAB6082051DEA783602010C6FCBA077048581E4078D34E78C1BF1D3D614DB0C6041192233A7C201827B28B0809FD5ACD9233C34EA4EFEAFCD0D638FA4A436E6B056DACFD81A82A5EFB6E378B1A8B53875E3D78E1C6198510206207440C40E8818B440D0683402F130314061CF132D0199A11419F8159105DBDFF4631A354AA89049361EB405BC64034A54D3A119EE1EA7BD5540B328208508507228A8A840A2A008045509001455626390E72F002014446EAEEEEAAAEEEEEEEEAAEAAAAA880D110A20344468FFFFFFFFFFFFFEDB6DB6DB6DB6DB6FFEFB0000000100018E760C0C03150602011414510E0E0001000667063CFF1D0001",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram3_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM3_rtl_0|altsyncram_g902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 0,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 0,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|decode2|eq_node\(0),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~2_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);
-
--- Location: MLABCELL_X18_Y12_N15
-\myVirtualToplevel|MEM_DATA_READ[24]~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ = ( \myVirtualToplevel|LessThan0~1_combout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & (
--- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0)) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8~portbdataout\) ) ) ) # ( \myVirtualToplevel|LessThan0~1_combout\ & (
--- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a0~portbdataout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|address_reg_b\(0) &
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ram_block1a8~portbdataout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000101010100000000000000001010101011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_address_reg_b\(0),
- datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a8~portbdataout\,
- datae => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a0~portbdataout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\);
-
--- Location: MLABCELL_X18_Y12_N27
-\myVirtualToplevel|MEM_DATA_READ[24]~62\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ & (
--- \myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ &
--- \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]~33_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[24]~61_combout\ & (
--- (\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & \myVirtualToplevel|MEM_DATA_READ[24]~60_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000100010001000100011111111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\,
- datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~60_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]~33_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~61_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\);
-
--- Location: MLABCELL_X18_Y16_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ & (
--- \myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector358~0_combout\ & (
--- !\myVirtualToplevel|MEM_DATA_READ[24]~62_combout\ & ( (\myVirtualToplevel|MEM_DATA_READ[8]~103_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[7]~3_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001010000111100001111000000001111010111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[8]~103_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[7]~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector358~0_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[24]~62_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1_combout\);
-
--- Location: FF_X20_Y22_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1347~4_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y16_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add7~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~89_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\)) ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[0]~95_Duplicate_161\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\)) ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111110100101000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[0]~95_Duplicate_161\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\,
- cin => GND,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~89_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\);
-
--- Location: FF_X18_Y16_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector358~1_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~89_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y18_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111110000111111111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\);
-
--- Location: LABCELL_X19_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~98\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~98_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\) ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110000001100000000000000000000000011111111000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- cin => GND,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~98_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\);
-
--- Location: LABCELL_X19_Y23_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~103\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~103_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~99\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~103_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\);
-
--- Location: LABCELL_X19_Y23_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~94\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~104\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~94_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\);
-
--- Location: LABCELL_X19_Y23_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~89_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~95\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~89_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\);
-
--- Location: LABCELL_X19_Y23_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~52\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~90\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~52_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\);
-
--- Location: LABCELL_X19_Y23_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~57_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~53\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\);
-
--- Location: LABCELL_X19_Y23_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~75\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~75_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~75_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\);
-
--- Location: LABCELL_X19_Y23_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~80\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~80_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~76\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~80_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\);
-
--- Location: LABCELL_X19_Y23_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~81\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~85_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\);
-
--- Location: LABCELL_X19_Y23_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~61_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\);
-
--- Location: LABCELL_X19_Y23_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~66\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~66_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~66_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\);
-
--- Location: LABCELL_X19_Y23_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~71\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~71_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~67\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~71_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\);
-
--- Location: LABCELL_X19_Y23_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~72\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~35_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\);
-
--- Location: LABCELL_X19_Y23_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~39_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~36\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~39_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\);
-
--- Location: LABCELL_X19_Y23_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~40\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~43_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\);
-
--- Location: LABCELL_X19_Y23_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~47\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~47_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~44\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~47_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\);
-
--- Location: LABCELL_X19_Y23_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~48\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\);
-
--- Location: LABCELL_X19_Y23_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~22_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~22_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\);
-
--- Location: LABCELL_X19_Y23_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~23\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~26_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\);
-
--- Location: LABCELL_X19_Y23_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~27\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~30_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\);
-
--- Location: LABCELL_X19_Y22_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011110011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~31\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~14_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\);
-
--- Location: LABCELL_X19_Y22_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011110011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~15\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~6_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\);
-
--- Location: LABCELL_X19_Y22_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011110011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~7\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\);
-
--- Location: LABCELL_X21_Y23_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~77_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000000000000110000000000000011000011110000001100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~77_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\);
-
--- Location: FF_X6_Y25_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~17_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\);
-
--- Location: FF_X6_Y25_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[17]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17));
-
--- Location: FF_X9_Y25_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~8_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\);
-
--- Location: MLABCELL_X4_Y25_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\);
-
--- Location: MLABCELL_X4_Y25_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[16]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\);
-
--- Location: MLABCELL_X4_Y25_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add19~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add19~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add19~22\);
-
--- Location: LABCELL_X6_Y25_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|sp~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add19~21_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111110000111111111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add19~21_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~21_combout\);
-
--- Location: LABCELL_X6_Y25_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\);
-
--- Location: LABCELL_X6_Y25_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~41_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(14) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(14),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\);
-
--- Location: LABCELL_X6_Y25_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\);
-
--- Location: LABCELL_X6_Y25_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(16),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\);
-
--- Location: LABCELL_X6_Y25_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add21~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add21~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) ) + ( VCC ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add21~22\);
-
--- Location: LABCELL_X7_Y26_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(16) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(16),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\);
-
--- Location: LABCELL_X7_Y26_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add20~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add20~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[17]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add20~22\);
-
--- Location: LABCELL_X6_Y25_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|sp~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add20~21_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add21~21_sumout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~5_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp~21_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101001100110011001100001111000011110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~21_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add21~21_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add20~21_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\);
-
--- Location: LABCELL_X6_Y25_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(17)) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp~22_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|sp\(17) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[23]~3_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111010000000001111101000000101111111110000010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[23]~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(17),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp~22_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23_combout\);
-
--- Location: FF_X6_Y25_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~23_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\);
-
--- Location: FF_X10_Y24_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~53_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y38_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|debugState.Debug_Idle~q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|inBreak~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001000100010001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_debugState.Debug_Idle~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_inBreak~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\);
-
--- Location: FF_X10_Y26_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|sp~68_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].addr[1]~56_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\);
-
--- Location: LABCELL_X14_Y26_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\ ) + ( !VCC ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[2]~DUPLICATE_q\ ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- cin => GND,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~85_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\);
-
--- Location: LABCELL_X14_Y26_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(3) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(3),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\);
-
--- Location: LABCELL_X14_Y26_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(4) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(4),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\);
-
--- Location: LABCELL_X14_Y26_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[5]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[5]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\);
-
--- Location: LABCELL_X14_Y26_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~69_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[6]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[6]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\);
-
--- Location: LABCELL_X14_Y26_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(7) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(7),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\);
-
--- Location: LABCELL_X14_Y26_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(8) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(8),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\);
-
--- Location: LABCELL_X14_Y26_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[9]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[9]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\);
-
--- Location: LABCELL_X14_Y26_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[10]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[10]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\);
-
--- Location: LABCELL_X14_Y26_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(11) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(11),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\);
-
--- Location: LABCELL_X14_Y25_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[12]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[12]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\);
-
--- Location: LABCELL_X14_Y25_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[13]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[13]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\);
-
--- Location: LABCELL_X14_Y25_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp[14]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[14]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\);
-
--- Location: LABCELL_X14_Y25_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) + ( !\myVirtualToplevel|ZPUEVO:ZPU0|sp\(15) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(15),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\);
-
--- Location: LABCELL_X14_Y25_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[16]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[16]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\);
-
--- Location: LABCELL_X14_Y25_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[17]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[17]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\);
-
--- Location: LABCELL_X14_Y25_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(18) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(18),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\);
-
--- Location: LABCELL_X14_Y25_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp\(19) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp\(19),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\);
-
--- Location: LABCELL_X14_Y25_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|sp[20]~DUPLICATE_q\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010101000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[20]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\);
-
--- Location: LABCELL_X14_Y25_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[21]~11_combout\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[21]~11_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\);
-
--- Location: LABCELL_X14_Y25_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add35~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add35~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add35~10\);
-
--- Location: LABCELL_X21_Y23_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add35~9_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111110101010111100001010000011001100100010001100000010000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add35~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\);
-
--- Location: LABCELL_X21_Y23_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~36_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add36~10_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010000000000000000000011111111111100000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~36_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add36~10_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7_combout\);
-
--- Location: LABCELL_X21_Y23_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ $
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~1_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000100110011001100100001111000011111001111110011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8_combout\);
-
--- Location: LABCELL_X21_Y23_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~8_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~10_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~10_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~9_combout\);
-
--- Location: LABCELL_X21_Y16_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111111100001111000000001111000011111111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\);
-
--- Location: LABCELL_X17_Y25_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~13_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~13_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\);
-
--- Location: LABCELL_X19_Y24_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|idimFlag~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000001000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_idimFlag~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\);
-
--- Location: LABCELL_X17_Y25_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000000000000000000000000000000100000000000000000000000000100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\);
-
--- Location: LABCELL_X20_Y21_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111101010101010111110101010101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\);
-
--- Location: LABCELL_X20_Y21_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RESULT~1_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector983~0_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|sp[22]~14_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111110000101010101010000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RESULT~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_sp[22]~14_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector983~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector983~1_combout\);
-
--- Location: FF_X29_Y30_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~337_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\);
-
--- Location: MLABCELL_X13_Y16_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\ & (
--- \myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux17~2_combout\ & (
--- !\myVirtualToplevel|MEM_DATA_READ[25]~53_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_Idle~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_WriteToAddr~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111110101010100000000101010101111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_WriteToAddr~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxState.MemXact_Idle~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux17~2_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[25]~53_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\);
-
--- Location: MLABCELL_X9_Y16_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector300~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25) & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111010000000001111101000000101111111110000010111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(25),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector300~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18_combout\);
-
--- Location: FF_X9_Y16_N34
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[25]~18_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25));
-
--- Location: LABCELL_X7_Y16_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & (
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(1) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[9]~19_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(25) & (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000000000001100001111000000111111000011110011111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(25),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[9]~19_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_DATA[1]~7_combout\);
-
--- Location: LABCELL_X20_Y18_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[26]~feeder_combout\);
-
--- Location: LABCELL_X19_Y27_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000010011000100100000000000000010000000000101000000000000110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8_combout\);
-
--- Location: LABCELL_X19_Y27_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan15~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|divStart~0_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~13_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~8_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000001000100000001000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_divStart~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~13_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~8_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan15~20_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~22_combout\);
-
--- Location: LABCELL_X14_Y24_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector1324~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|READY~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector1324~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\);
-
--- Location: MLABCELL_X13_Y24_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|state.State_Execute~q\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~12_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000010100000111100001010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_state.State_Execute~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_RESYN9009_BDD9010\);
-
--- Location: MLABCELL_X18_Y27_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~6_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000001010000000010100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\);
-
--- Location: MLABCELL_X18_Y17_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[31]~feeder_combout\);
-
--- Location: LABCELL_X17_Y10_N15
-\myVirtualToplevel|Add17~109\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~109_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(25) ) + ( GND ) + ( \myVirtualToplevel|Add17~122\ ))
--- \myVirtualToplevel|Add17~110\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(25) ) + ( GND ) + ( \myVirtualToplevel|Add17~122\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(25),
- cin => \myVirtualToplevel|Add17~122\,
- sumout => \myVirtualToplevel|Add17~109_sumout\,
- cout => \myVirtualToplevel|Add17~110\);
-
--- Location: FF_X17_Y10_N17
-\myVirtualToplevel|MILLISEC_UP_COUNTER[25]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~109_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(25),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER\(25));
-
--- Location: LABCELL_X17_Y10_N18
-\myVirtualToplevel|Add17~113\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~113_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~110\ ))
--- \myVirtualToplevel|Add17~114\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|Add17~110\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER[26]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add17~110\,
- sumout => \myVirtualToplevel|Add17~113_sumout\,
- cout => \myVirtualToplevel|Add17~114\);
-
--- Location: LABCELL_X10_Y14_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[31]~9_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[8]~7_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux16~2_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000101001101110000010100110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[31]~9_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[8]~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux16~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(26),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21_combout\);
-
--- Location: FF_X10_Y14_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[26]~21_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26));
-
--- Location: FF_X17_Y10_N20
-\myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add17~113_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(26),
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ALT_INV_Equal34~4_combout\,
- ena => \myVirtualToplevel|MILLISEC_UP_COUNTER[10]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MILLISEC_UP_COUNTER[26]~DUPLICATE_q\);
-
--- Location: LABCELL_X17_Y10_N21
-\myVirtualToplevel|Add17~117\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add17~117_sumout\ = SUM(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(27) ) + ( GND ) + ( \myVirtualToplevel|Add17~114\ ))
--- \myVirtualToplevel|Add17~118\ = CARRY(( \myVirtualToplevel|MILLISEC_UP_COUNTER\(27) ) + ( GND ) + ( \myVirtualToplevel|Add17~114\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(27),
- cin => \myVirtualToplevel|Add17~114\,
- sumout => \myVirtualToplevel|Add17~117_sumout\,
- cout => \myVirtualToplevel|Add17~118\);
-
--- Location: LABCELL_X16_Y27_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~33_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.valid~combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~34_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010101010101000001010101010101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.valid~combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~34_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~33_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\);
-
--- Location: FF_X18_Y17_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[27]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[27]~59_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(27));
-
--- Location: MLABCELL_X18_Y17_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder_combout\);
-
--- Location: FF_X18_Y17_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~feeder_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE_q\);
-
--- Location: MLABCELL_X18_Y17_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(27) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[27]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(27),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word[27]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\);
-
--- Location: LABCELL_X16_Y28_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993_BDD8994\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\) # (\myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|WideOr168~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101111111111111111101010101111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_WideOr168~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~20_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993_BDD8994\);
-
--- Location: LABCELL_X17_Y25_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000100000000000000000000000000000000000001000000000000100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\);
-
--- Location: MLABCELL_X18_Y28_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux148~10_Duplicate_12\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux146~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux144~10_Duplicate_12\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux145~10_Duplicate_12\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux143~10_Duplicate_12\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010000000001000001000000000000000001000001000000000001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux146~10_Duplicate_12\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux144~10_Duplicate_12\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux145~10_Duplicate_12\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux143~10_Duplicate_12\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux148~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\);
-
--- Location: MLABCELL_X13_Y25_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~11_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101010101010101010101010101010101010101010101010101010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\);
-
--- Location: LABCELL_X16_Y27_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\))))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010001010100010101000101010001010100010101100001010001010110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\);
-
--- Location: LABCELL_X16_Y28_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Selector974~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_RESYN8993_BDD8994\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Selector989~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~4_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000011111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector989~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~9_RESYN8993_BDD8994\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector974~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~9_combout\);
-
--- Location: MLABCELL_X13_Y25_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~0_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ $ (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010110100101101000001111000011110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector978~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~7_combout\);
-
--- Location: MLABCELL_X28_Y33_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000101111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256_combout\);
-
--- Location: FF_X28_Y33_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\);
-
--- Location: MLABCELL_X28_Y33_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257_combout\);
-
--- Location: FF_X28_Y33_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~257_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\);
-
--- Location: MLABCELL_X28_Y32_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249_combout\);
-
--- Location: FF_X28_Y32_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\);
-
--- Location: MLABCELL_X28_Y32_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111101111111100000001000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248_combout\);
-
--- Location: FF_X28_Y32_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~248_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\);
-
--- Location: LABCELL_X29_Y33_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111111111110000111101010101001100110101010100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\);
-
--- Location: LABCELL_X26_Y33_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268_combout\);
-
--- Location: FF_X26_Y33_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~268_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\);
-
--- Location: FF_X23_Y35_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\);
-
--- Location: MLABCELL_X23_Y35_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261_combout\);
-
--- Location: FF_X23_Y35_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~261_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\);
-
--- Location: FF_X26_Y33_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\);
-
--- Location: LABCELL_X26_Y33_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000001001111111111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269_combout\);
-
--- Location: FF_X26_Y33_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~269_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X23_Y35_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260_combout\);
-
--- Location: FF_X23_Y35_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~260_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\);
-
--- Location: LABCELL_X31_Y33_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111001100110011001101010101010101010000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\);
-
--- Location: FF_X28_Y32_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_OTERM1841\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~q\);
-
--- Location: LABCELL_X32_Y23_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~1_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add18~5_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~1_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\);
-
--- Location: LABCELL_X31_Y25_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|l1State.State_Decode~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & \myVirtualToplevel|RESET_n~q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000101000001010000010100000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\,
- datac => \myVirtualToplevel|ALT_INV_RESET_n~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_l1State.State_Decode~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\);
-
--- Location: MLABCELL_X23_Y28_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~18_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2Invalid~11_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100010011000000000000000000000011000100110000001100010011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~18_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2Invalid~11_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\);
-
--- Location: FF_X26_Y24_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx[14]_OTERM3293\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14));
-
--- Location: LABCELL_X24_Y24_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add11~81_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2FetchIdx\(14) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2FetchIdx\(14),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add11~81_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\);
-
--- Location: MLABCELL_X23_Y28_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~18_combout\) # (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~15_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~4_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111111111111111111111001111110111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~15_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~18_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_RESYN13468_BDD13469\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\);
-
--- Location: MLABCELL_X23_Y28_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Equal135~10_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~11_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~1_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~0_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~21_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111111111110000101110111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal135~10_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~21_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~11_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\);
-
--- Location: MLABCELL_X23_Y28_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9315_BDD9316\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9313_BDD9314\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~22_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_RESYN9311_BDD9312\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~25_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000010000000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~22_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9311_BDD9312\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~25_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9315_BDD9316\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_RESYN9313_BDD9314\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\);
-
--- Location: MLABCELL_X23_Y28_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~3_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal136~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add18~13_sumout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~438_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~437_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111111111111101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~13_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal136~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add18~9_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~438_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~437_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\);
-
--- Location: MLABCELL_X28_Y32_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_NEW1840\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_OTERM1841\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_OTERM1841\);
-
--- Location: FF_X28_Y32_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]_OTERM1841\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y32_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_NEW1838\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_OTERM1839\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_OTERM1839\);
-
--- Location: FF_X28_Y32_N4
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_OTERM1839\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\);
-
--- Location: FF_X28_Y33_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\);
-
--- Location: MLABCELL_X28_Y33_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253_combout\);
-
--- Location: FF_X28_Y33_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~253_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y33_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000101111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252_combout\);
-
--- Location: FF_X28_Y33_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~252_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\);
-
--- Location: MLABCELL_X28_Y33_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101001100110011001100000000111111110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\);
-
--- Location: FF_X23_Y35_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\);
-
--- Location: MLABCELL_X23_Y35_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265_combout\);
-
--- Location: FF_X23_Y35_N34
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~265_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X23_Y35_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264_combout\);
-
--- Location: FF_X23_Y35_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~264_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\);
-
--- Location: LABCELL_X26_Y33_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) )
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000001111111111110111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273_combout\);
-
--- Location: FF_X26_Y33_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\);
-
--- Location: LABCELL_X26_Y33_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272_combout\);
-
--- Location: FF_X26_Y33_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~272_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\);
-
--- Location: LABCELL_X31_Y33_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001101100011011000110110001101100000000010101011010101011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\);
-
--- Location: LABCELL_X29_Y33_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~8_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~5_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001101000100110011110100010000000011011101111100111101110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~8_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\);
-
--- Location: MLABCELL_X28_Y33_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259_combout\);
-
--- Location: FF_X28_Y33_N1
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\);
-
--- Location: LABCELL_X26_Y33_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000001001111111111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275_combout\);
-
--- Location: FF_X26_Y33_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\);
-
--- Location: LABCELL_X26_Y33_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\
--- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271_combout\);
-
--- Location: FF_X26_Y33_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\);
-
--- Location: MLABCELL_X28_Y33_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255_combout\);
-
--- Location: FF_X28_Y33_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~255_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\);
-
--- Location: LABCELL_X32_Y33_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111010101010101010100001111000011110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\);
-
--- Location: FF_X28_Y33_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\);
-
--- Location: MLABCELL_X28_Y33_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000101111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254_combout\);
-
--- Location: FF_X28_Y33_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~254_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y33_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270_combout\);
-
--- Location: FF_X26_Y33_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\);
-
--- Location: LABCELL_X26_Y33_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274_combout\);
-
--- Location: FF_X26_Y33_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\);
-
--- Location: MLABCELL_X28_Y33_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\
--- ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000101111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258_combout\);
-
--- Location: FF_X28_Y33_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~258_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\);
-
--- Location: LABCELL_X29_Y33_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010100000000001100110000111101010101111111110011001100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\);
-
--- Location: MLABCELL_X23_Y35_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266_combout\);
-
--- Location: FF_X23_Y35_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~266_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\);
-
--- Location: MLABCELL_X28_Y32_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000101111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250_combout\);
-
--- Location: FF_X28_Y32_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~250_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\);
-
--- Location: FF_X28_Y32_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\);
-
--- Location: MLABCELL_X28_Y32_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a3\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000101111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246_combout\);
-
--- Location: FF_X28_Y32_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~246_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\);
-
--- Location: FF_X23_Y35_N22
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~262_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\);
-
--- Location: LABCELL_X32_Y31_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111001100110011001100000000111111110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\);
-
--- Location: FF_X23_Y35_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~263_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\);
-
--- Location: FF_X28_Y32_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\);
-
--- Location: MLABCELL_X28_Y32_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247_combout\);
-
--- Location: FF_X28_Y32_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~247_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y32_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111110111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251_combout\);
-
--- Location: FF_X28_Y32_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~251_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\);
-
--- Location: MLABCELL_X23_Y35_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a3\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001111101111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a3\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267_combout\);
-
--- Location: FF_X23_Y35_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~267_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\);
-
--- Location: LABCELL_X32_Y33_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000011110000111101010101010101010000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\);
-
--- Location: LABCELL_X29_Y33_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~0_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~2_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000101000101100010011100110100100011011001111010101111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\);
-
--- Location: LABCELL_X29_Y33_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~4_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110011001100110000110011001100111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~9_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\);
-
--- Location: LABCELL_X29_Y26_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111100000000000000000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1_combout\);
-
--- Location: LABCELL_X29_Y26_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100000000111111110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2_combout\);
-
--- Location: LABCELL_X29_Y26_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~8_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~1_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~8_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\);
-
--- Location: LABCELL_X24_Y26_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan17~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~5_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000011000000000000001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan17~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\);
-
--- Location: FF_X26_Y33_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~275_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\);
-
--- Location: FF_X26_Y33_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~274_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y33_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100000000000011110000000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\);
-
--- Location: FF_X28_Y33_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~256_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y33_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\);
-
--- Location: FF_X28_Y33_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~259_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y33_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\);
-
--- Location: FF_X26_Y33_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~273_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y33_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\);
-
--- Location: LABCELL_X29_Y28_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add22~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\,
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\);
-
--- Location: LABCELL_X29_Y28_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(2) ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(2),
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\);
-
--- Location: LABCELL_X29_Y28_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[3]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[3]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~18\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\);
-
--- Location: LABCELL_X29_Y28_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add22~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|pc[4]~DUPLICATE_q\ ) + ( GND ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[4]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add22~10\);
-
--- Location: MLABCELL_X28_Y37_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~18_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~17_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~8_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~7_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000011110000111100000000111111110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~18_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~8_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~17_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\);
-
--- Location: MLABCELL_X23_Y35_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\);
-
--- Location: MLABCELL_X28_Y32_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\);
-
--- Location: MLABCELL_X23_Y35_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\);
-
--- Location: FF_X28_Y32_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~249_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y32_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\);
-
--- Location: MLABCELL_X28_Y37_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~13_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~12_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~3_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~2_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111001100110011001100001111000011110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~13_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~12_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\);
-
--- Location: MLABCELL_X28_Y33_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\);
-
--- Location: FF_X26_Y33_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~270_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\);
-
--- Location: FF_X26_Y33_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~271_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y33_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111110000111111111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\);
-
--- Location: LABCELL_X26_Y33_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\);
-
--- Location: MLABCELL_X28_Y33_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\);
-
--- Location: MLABCELL_X28_Y37_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~16_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~15_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~6_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~5_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111010101010101010100001111000011110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~16_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~15_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~5_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\);
-
--- Location: MLABCELL_X23_Y35_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\);
-
--- Location: FF_X28_Y32_N5
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]_OTERM1839\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE_q\);
-
--- Location: MLABCELL_X28_Y32_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\);
-
--- Location: MLABCELL_X28_Y32_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\);
-
--- Location: MLABCELL_X28_Y37_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~11_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~10_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux250~0_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000000001111111101010101010101010000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~10_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~11_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux250~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\);
-
--- Location: MLABCELL_X28_Y37_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000010101010001001110010011101010101111111110010011100100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\);
-
--- Location: LABCELL_X31_Y33_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][3]~DUPLICATE_q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][3]~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000011110000111101010101010101010000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][3]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][3]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\);
-
--- Location: LABCELL_X31_Y33_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][3]~DUPLICATE_q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][3]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][3]~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000011110000111100000000111111110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][3]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][3]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\);
-
--- Location: LABCELL_X29_Y33_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][3]~q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][3]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][3]~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000110000001100001111110011111101000100011101110100010001110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][3]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][3]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][3]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\);
-
--- Location: MLABCELL_X28_Y33_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][3]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][3]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][3]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][3]~q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100000011111100111111001101010000010111110101000001011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][3]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][3]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][3]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\);
-
--- Location: LABCELL_X32_Y33_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~8_combout\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~7_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000011110101010111111111001100110000111101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~8_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~7_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\);
-
--- Location: LABCELL_X32_Y33_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][3]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][3]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][3]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000000001111111101010101010101010000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][3]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][3]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][3]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\);
-
--- Location: LABCELL_X32_Y33_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][3]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][3]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111001100110011001101010101010101010000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][3]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][3]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\);
-
--- Location: LABCELL_X32_Y31_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][3]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][3]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][3]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111001100110011001100000000111111110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][3]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][3]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][3]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\);
-
--- Location: LABCELL_X32_Y33_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][3]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][3]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][3]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][3]~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000000001111111101010101010101010011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][3]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][3]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][3]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][3]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\);
-
--- Location: LABCELL_X31_Y33_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~3_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001001000110100010101100111000010011010101111001101111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\);
-
--- Location: LABCELL_X31_Y33_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~9_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~9_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\);
-
--- Location: LABCELL_X26_Y29_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\
--- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111101100000000000001001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346_combout\);
-
--- Location: FF_X26_Y29_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\);
-
--- Location: FF_X26_Y29_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\);
-
--- Location: LABCELL_X26_Y29_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111101111111100000001000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350_combout\);
-
--- Location: FF_X26_Y29_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~350_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y29_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11_combout\);
-
--- Location: MLABCELL_X23_Y30_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\
--- & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111101100000000000001001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355_combout\);
-
--- Location: FF_X23_Y30_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\);
-
--- Location: MLABCELL_X23_Y30_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001000000001110111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354_combout\);
-
--- Location: FF_X23_Y30_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\);
-
--- Location: MLABCELL_X23_Y30_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9_combout\);
-
--- Location: FF_X31_Y30_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\);
-
--- Location: LABCELL_X31_Y30_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344_combout\);
-
--- Location: FF_X31_Y30_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~344_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X31_Y30_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111101111111100000001000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348_combout\);
-
--- Location: FF_X31_Y30_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~348_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\);
-
--- Location: LABCELL_X31_Y30_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10_combout\);
-
--- Location: LABCELL_X26_Y30_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360_combout\);
-
--- Location: FF_X26_Y30_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\);
-
--- Location: LABCELL_X26_Y30_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~4_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111101111111100000001000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~4_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361_combout\);
-
--- Location: FF_X26_Y30_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~361_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\);
-
--- Location: LABCELL_X26_Y30_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8_combout\);
-
--- Location: LABCELL_X29_Y28_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~11_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~10_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~9_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~8_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111001100110011001100001111000011110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~11_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~9_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~10_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~8_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\);
-
--- Location: FF_X26_Y31_N34
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\);
-
--- Location: LABCELL_X26_Y31_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349_combout\);
-
--- Location: FF_X26_Y31_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~349_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y31_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345_combout\);
-
--- Location: FF_X26_Y31_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\);
-
--- Location: LABCELL_X26_Y31_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18_combout\);
-
--- Location: FF_X26_Y30_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\);
-
--- Location: LABCELL_X26_Y30_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365_combout\);
-
--- Location: FF_X26_Y30_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~365_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y30_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111110100000000000000101111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364_combout\);
-
--- Location: FF_X26_Y30_N47
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\);
-
--- Location: LABCELL_X26_Y30_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~q\ )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16_combout\);
-
--- Location: LABCELL_X26_Y31_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ram_block1a7\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359_combout\);
-
--- Location: FF_X26_Y31_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\);
-
--- Location: FF_X23_Y30_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\);
-
--- Location: MLABCELL_X23_Y30_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001110111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358_combout\);
-
--- Location: FF_X23_Y30_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~358_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y31_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17_combout\);
-
--- Location: LABCELL_X26_Y31_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111101111111100000001000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM1_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347_combout\);
-
--- Location: FF_X26_Y31_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\);
-
--- Location: LABCELL_X26_Y31_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE_q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111111111111111111110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19_combout\);
-
--- Location: LABCELL_X29_Y28_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~19_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~18_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~17_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~16_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000011110000111101010101010101010000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~18_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~16_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~17_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~19_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\);
-
--- Location: MLABCELL_X9_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_NEW3159\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_OTERM3160\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(18) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_OTERM3160\);
-
--- Location: FF_X9_Y23_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[18]_OTERM3160\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(18));
-
--- Location: MLABCELL_X9_Y23_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_NEW3095\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_OTERM3096\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(18) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_OTERM3096\);
-
--- Location: FF_X9_Y23_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[18]_OTERM3096\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(18));
-
--- Location: MLABCELL_X9_Y23_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_NEW2967\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_OTERM2968\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001001100011100110111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_OTERM2968\);
-
--- Location: FF_X9_Y23_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[18]_OTERM2968\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18));
-
--- Location: MLABCELL_X9_Y23_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_NEW3031\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_OTERM3032\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_OTERM3032\);
-
--- Location: FF_X9_Y23_N56
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[18]_OTERM3032\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18));
-
--- Location: MLABCELL_X9_Y23_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(18)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(18)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(18) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(18))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(18)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101001101010011010100110101001100000000000011111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(18),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(18),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(18),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\);
-
--- Location: MLABCELL_X9_Y23_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_NEW2711\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_OTERM2712\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000011000100011100111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_OTERM2712\);
-
--- Location: FF_X9_Y23_N23
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[18]_OTERM2712\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18));
-
--- Location: MLABCELL_X9_Y23_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_NEW2839\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_OTERM2840\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(18) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_OTERM2840\);
-
--- Location: FF_X9_Y23_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[18]_OTERM2840\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(18));
-
--- Location: MLABCELL_X9_Y23_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_NEW2903\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_OTERM2904\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001001100011100110111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_OTERM2904\);
-
--- Location: FF_X9_Y23_N20
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[18]_OTERM2904\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18));
-
--- Location: MLABCELL_X9_Y23_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_NEW2775\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_OTERM2776\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(18) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100110101001101010011010100110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_OTERM2776\);
-
--- Location: FF_X9_Y23_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[18]_OTERM2776\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(18));
-
--- Location: MLABCELL_X9_Y23_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(18) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(18) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ &
--- ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(18) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(18) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111001100110011001101010101010101010000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(18),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(18),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(18),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(18),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\);
-
--- Location: MLABCELL_X9_Y23_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~1_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~0_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111000000000000111111111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\);
-
--- Location: LABCELL_X10_Y15_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[18]~30_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux24~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[18]~30_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000010001111111111101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux24~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~30_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(18),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23_combout\);
-
--- Location: FF_X10_Y15_N55
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[18]~23_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18));
-
--- Location: LABCELL_X7_Y16_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(18) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(2) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100001111000000110000111111001111000011111100111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(18),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[2]~3_combout\);
-
--- Location: LABCELL_X10_Y17_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[19]~33_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux23~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[19]~33_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000001001111111111100100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux23~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[19]~33_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(19),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22_combout\);
-
--- Location: FF_X10_Y17_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[19]~22_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19));
-
--- Location: LABCELL_X7_Y18_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(19) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(3) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001010100010101000101010001010111010101110101011101010111010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(3),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(19),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[3]~2_combout\);
-
--- Location: MLABCELL_X9_Y16_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[20]~16_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux22~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[20]~16_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001010001011010101111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[20]~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux22~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(20),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20_combout\);
-
--- Location: FF_X9_Y16_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[20]~20_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20));
-
--- Location: MLABCELL_X9_Y16_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(4) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(20) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111010101010101010101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(4),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(20),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[4]~0_combout\);
-
--- Location: LABCELL_X10_Y17_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & ( \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & (
--- \myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & ( !\myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & (
--- !\myVirtualToplevel|MEM_DATA_READ[21]~10_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux21~2_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000010111111111100111000000000000100111111111111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux21~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(21),
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[21]~10_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27_combout\);
-
--- Location: FF_X10_Y17_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[21]~27_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21));
-
--- Location: MLABCELL_X9_Y18_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(21) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(5) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001100001111000000110000111111001111000011111100111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(5),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(21),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[5]~7_combout\);
-
--- Location: LABCELL_X10_Y23_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_NEW2703\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_OTERM2704\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000001001100011100110111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data[22]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_OTERM2704\);
-
--- Location: FF_X10_Y23_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data[22]_OTERM2704\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22));
-
--- Location: LABCELL_X10_Y23_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_NEW2895\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_OTERM2896\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~6_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000011000100011100111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_OTERM2896\);
-
--- Location: FF_X10_Y23_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[22]_OTERM2896\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22));
-
--- Location: LABCELL_X10_Y23_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_NEW2831\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_OTERM2832\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(22) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_OTERM2832\);
-
--- Location: FF_X10_Y23_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data[22]_OTERM2832\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(22));
-
--- Location: LABCELL_X10_Y23_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_NEW2767\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_OTERM2768\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[0]~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data[0]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_OTERM2768\);
-
--- Location: FF_X10_Y23_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data[22]_OTERM2768\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22));
-
--- Location: LABCELL_X10_Y23_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(22)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22) & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[1].data\(22)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[3].data\(22) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data\(22)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[2].data\(22))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011010100110101000000001111000000110101001101010000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[2].data\(22),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data\(22),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[1].data\(22),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[3].data\(22),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\);
-
--- Location: LABCELL_X10_Y23_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_NEW3087\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_OTERM3088\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22)))))
--- # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[0]~3_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000111110001000000011111000100001101111111010000110111111101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data[0]~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_OTERM3088\);
-
--- Location: FF_X10_Y23_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data[22]_OTERM3088\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22));
-
--- Location: LABCELL_X10_Y23_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_NEW3023\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_OTERM3024\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[0]~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(22) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100100111001001110010011100100111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data[0]~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_OTERM3024\);
-
--- Location: FF_X10_Y23_N19
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data[22]_OTERM3024\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(22));
-
--- Location: LABCELL_X10_Y23_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_NEW3151\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_OTERM3152\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[0]~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(22) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100011101000111010001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data[0]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_OTERM3152\);
-
--- Location: FF_X10_Y23_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data[22]_OTERM3152\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(22));
-
--- Location: LABCELL_X10_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_NEW2959\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_OTERM2960\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[16]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[0].data[23]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[28]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000011000100011100111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[16]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[0].data[23]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data[28]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_OTERM2960\);
-
--- Location: FF_X10_Y23_N2
-\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data[22]_OTERM2960\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22));
-
--- Location: LABCELL_X10_Y23_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(22)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[6].data\(22) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(22)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[7].data\(22) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[4].data\(22)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifo[5].data\(22))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010111110101000001011111010100110000001100000011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[5].data\(22),
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[6].data\(22),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[4].data\(22),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifo[7].data\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\);
-
--- Location: LABCELL_X10_Y23_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxFifoReadIdx[2]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~1_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxFifoReadIdx[2]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\);
-
--- Location: LABCELL_X10_Y17_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[22]~13_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux20~2_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|MEM_DATA_READ[22]~13_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000011000100011100111111011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[22]~13_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux20~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(22),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26_combout\);
-
--- Location: FF_X10_Y17_N53
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[22]~26_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22));
-
--- Location: LABCELL_X7_Y18_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(22))) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(6)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010011100100111000011110000111100100111001001110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(22),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(6),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[6]~6_combout\);
-
--- Location: LABCELL_X17_Y12_N0
-\myVirtualToplevel|Mux88~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Mux88~0_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6)) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[4]~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(6)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010000101000001010000010100000101000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[4]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(6),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- combout => \myVirtualToplevel|Mux88~0_combout\);
-
--- Location: FF_X17_Y12_N2
-\myVirtualToplevel|IO_DATA_READ_SOCCFG[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Mux88~0_combout\,
- ena => \myVirtualToplevel|RESET_n~q\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SOCCFG\(23));
-
--- Location: LABCELL_X24_Y9_N24
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0_combout\ = ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(7) & ( \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.START_INIT~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datae => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(7),
- dataf => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_state_v.START_INIT~q\,
- combout => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0_combout\);
-
--- Location: FF_X24_Y9_N25
-\myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o[7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|Selector8~0_combout\,
- asdata => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|rx_v\(7),
- sload => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|state_v.REPORT_ERROR~q\,
- ena => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|mosi_o~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(7));
-
--- Location: LABCELL_X21_Y9_N0
-\myVirtualToplevel|IO_DATA_READ_SD[23]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ_SD[23]~feeder_combout\ = \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|error_o\(7)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|SDCARD0:SDCARDS:0:SDCARD|ALT_INV_error_o\(7),
- combout => \myVirtualToplevel|IO_DATA_READ_SD[23]~feeder_combout\);
-
--- Location: FF_X16_Y9_N4
-\myVirtualToplevel|SD_ADDR[0][23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\,
- sload => VCC,
- ena => \myVirtualToplevel|SD_ADDR[0][0]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|SD_ADDR[0][23]~q\);
-
--- Location: FF_X21_Y9_N2
-\myVirtualToplevel|IO_DATA_READ_SD[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ_SD[23]~feeder_combout\,
- asdata => \myVirtualToplevel|SD_ADDR[0][23]~q\,
- sclr => \myVirtualToplevel|TIMER:TIMER1|Mux2~0_combout\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- ena => \myVirtualToplevel|IO_DATA_READ_SD[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ_SD\(23));
-
--- Location: FF_X16_Y11_N17
-\myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1262\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|Equal3~0_combout\,
- sload => VCC,
- ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ[22]_OTERM1263\);
-
--- Location: LABCELL_X16_Y8_N9
-\myVirtualToplevel|UART1|Add10~40\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~40_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(7) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(7) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(7),
- datad => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(7),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add10~40_combout\);
-
--- Location: LABCELL_X16_Y8_N6
-\myVirtualToplevel|UART1|Add10~38\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~38_combout\ = ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) & ( (!\myVirtualToplevel|UART1_CS~combout\) # (\myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6)) ) ) # ( !\myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(6) & (
--- (\myVirtualToplevel|UART1_CS~combout\ & \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(6)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000001010000010110101111101011111010111110101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(6),
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(6),
- combout => \myVirtualToplevel|UART1|Add10~38_combout\);
-
--- Location: MLABCELL_X13_Y8_N54
-\myVirtualToplevel|UART1|Add10~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~37_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(5) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[5]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(5),
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[5]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add10~37_combout\);
-
--- Location: MLABCELL_X13_Y8_N57
-\myVirtualToplevel|UART1|Add10~39\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~39_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(4) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(4) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(4),
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(4),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add10~39_combout\);
-
--- Location: LABCELL_X16_Y8_N21
-\myVirtualToplevel|UART1|Add10~43\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~43_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(3) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(3) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(3),
- datac => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(3),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add10~43_combout\);
-
--- Location: LABCELL_X14_Y8_N54
-\myVirtualToplevel|UART1|Add10~42\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~42_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(2) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR[2]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(2),
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR[2]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add10~42_combout\);
-
--- Location: LABCELL_X16_Y8_N27
-\myVirtualToplevel|UART1|Add10~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~41_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(1) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(1) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(1),
- datab => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(1),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add10~41_combout\);
-
--- Location: LABCELL_X14_Y8_N39
-\myVirtualToplevel|UART1|Add10~32\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~32_combout\ = ( \myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART1|TX_FIFO_WR_ADDR\(0) ) ) # ( !\myVirtualToplevel|UART1_CS~combout\ & ( \myVirtualToplevel|UART0|TX_FIFO_WR_ADDR\(0) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100000000111111110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_WR_ADDR\(0),
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_WR_ADDR\(0),
- dataf => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- combout => \myVirtualToplevel|UART1|Add10~32_combout\);
-
--- Location: LABCELL_X16_Y8_N30
-\myVirtualToplevel|UART1|Add10~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~35_cout\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) ) + ( VCC ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- cin => GND,
- cout => \myVirtualToplevel|UART1|Add10~35_cout\);
-
--- Location: LABCELL_X16_Y8_N33
-\myVirtualToplevel|UART1|Add10~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~1_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~32_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0))))) ) + ( \myVirtualToplevel|UART1|Add10~35_cout\ ))
--- \myVirtualToplevel|UART1|Add10~2\ = CARRY(( \myVirtualToplevel|UART1|Add10~32_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(0)))) # (\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(0))))) ) + ( \myVirtualToplevel|UART1|Add10~35_cout\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000011111101100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(0),
- datac => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_Add10~32_combout\,
- dataf => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(0),
- cin => \myVirtualToplevel|UART1|Add10~35_cout\,
- sumout => \myVirtualToplevel|UART1|Add10~1_sumout\,
- cout => \myVirtualToplevel|UART1|Add10~2\);
-
--- Location: LABCELL_X16_Y8_N36
-\myVirtualToplevel|UART1|Add10~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~21_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~41_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1)))))) ) + ( \myVirtualToplevel|UART1|Add10~2\ ))
--- \myVirtualToplevel|UART1|Add10~22\ = CARRY(( \myVirtualToplevel|UART1|Add10~41_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(1))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(1)))))) ) + ( \myVirtualToplevel|UART1|Add10~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011100001111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(1),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add10~41_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(1),
- cin => \myVirtualToplevel|UART1|Add10~2\,
- sumout => \myVirtualToplevel|UART1|Add10~21_sumout\,
- cout => \myVirtualToplevel|UART1|Add10~22\);
-
--- Location: LABCELL_X16_Y8_N39
-\myVirtualToplevel|UART1|Add10~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~25_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~42_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2)))))) ) + ( \myVirtualToplevel|UART1|Add10~22\ ))
--- \myVirtualToplevel|UART1|Add10~26\ = CARRY(( \myVirtualToplevel|UART1|Add10~42_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(2))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(2)))))) ) + ( \myVirtualToplevel|UART1|Add10~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011100001111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(2),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add10~42_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(2),
- cin => \myVirtualToplevel|UART1|Add10~22\,
- sumout => \myVirtualToplevel|UART1|Add10~25_sumout\,
- cout => \myVirtualToplevel|UART1|Add10~26\);
-
--- Location: LABCELL_X16_Y8_N42
-\myVirtualToplevel|UART1|Add10~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~29_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~43_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3)))))) ) + ( \myVirtualToplevel|UART1|Add10~26\ ))
--- \myVirtualToplevel|UART1|Add10~30\ = CARRY(( \myVirtualToplevel|UART1|Add10~43_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(3))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(3)))))) ) + ( \myVirtualToplevel|UART1|Add10~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011100001111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(3),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add10~43_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(3),
- cin => \myVirtualToplevel|UART1|Add10~26\,
- sumout => \myVirtualToplevel|UART1|Add10~29_sumout\,
- cout => \myVirtualToplevel|UART1|Add10~30\);
-
--- Location: LABCELL_X16_Y8_N45
-\myVirtualToplevel|UART1|Add10~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~13_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~39_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4)))))) ) + ( \myVirtualToplevel|UART1|Add10~30\ ))
--- \myVirtualToplevel|UART1|Add10~14\ = CARRY(( \myVirtualToplevel|UART1|Add10~39_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(4))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(4)))))) ) + ( \myVirtualToplevel|UART1|Add10~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011100001111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(4),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add10~39_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(4),
- cin => \myVirtualToplevel|UART1|Add10~30\,
- sumout => \myVirtualToplevel|UART1|Add10~13_sumout\,
- cout => \myVirtualToplevel|UART1|Add10~14\);
-
--- Location: LABCELL_X16_Y8_N48
-\myVirtualToplevel|UART1|Add10~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~5_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~37_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5)))))) ) + ( \myVirtualToplevel|UART1|Add10~14\ ))
--- \myVirtualToplevel|UART1|Add10~6\ = CARRY(( \myVirtualToplevel|UART1|Add10~37_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(5))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(5)))))) ) + ( \myVirtualToplevel|UART1|Add10~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011100001111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(5),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add10~37_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(5),
- cin => \myVirtualToplevel|UART1|Add10~14\,
- sumout => \myVirtualToplevel|UART1|Add10~5_sumout\,
- cout => \myVirtualToplevel|UART1|Add10~6\);
-
--- Location: LABCELL_X16_Y8_N51
-\myVirtualToplevel|UART1|Add10~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~9_sumout\ = SUM(( \myVirtualToplevel|UART1|Add10~38_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6)))))) ) + ( \myVirtualToplevel|UART1|Add10~6\ ))
--- \myVirtualToplevel|UART1|Add10~10\ = CARRY(( \myVirtualToplevel|UART1|Add10~38_combout\ ) + ( (!\myVirtualToplevel|Equal4~0_combout\ & (((!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6))))) # (\myVirtualToplevel|Equal4~0_combout\ &
--- ((!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(6))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(6)))))) ) + ( \myVirtualToplevel|UART1|Add10~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011100001111100000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(6),
- datad => \myVirtualToplevel|UART1|ALT_INV_Add10~38_combout\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(6),
- cin => \myVirtualToplevel|UART1|Add10~6\,
- sumout => \myVirtualToplevel|UART1|Add10~9_sumout\,
- cout => \myVirtualToplevel|UART1|Add10~10\);
-
--- Location: LABCELL_X16_Y8_N54
-\myVirtualToplevel|UART1|Add10~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|UART1|Add10~17_sumout\ = SUM(( (!\myVirtualToplevel|IO_SELECT~combout\ & (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7))) # (\myVirtualToplevel|IO_SELECT~combout\ & ((!\myVirtualToplevel|Equal4~0_combout\ &
--- (!\myVirtualToplevel|UART0|TX_FIFO_RD_ADDR\(7))) # (\myVirtualToplevel|Equal4~0_combout\ & ((!\myVirtualToplevel|UART1|TX_FIFO_RD_ADDR\(7)))))) ) + ( \myVirtualToplevel|UART1|Add10~40_combout\ ) + ( \myVirtualToplevel|UART1|Add10~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111110000000000000000000000001010101110101000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART0|ALT_INV_TX_FIFO_RD_ADDR\(7),
- datab => \myVirtualToplevel|ALT_INV_IO_SELECT~combout\,
- datac => \myVirtualToplevel|ALT_INV_Equal4~0_combout\,
- datad => \myVirtualToplevel|UART1|ALT_INV_TX_FIFO_RD_ADDR\(7),
- dataf => \myVirtualToplevel|UART1|ALT_INV_Add10~40_combout\,
- cin => \myVirtualToplevel|UART1|Add10~10\,
- sumout => \myVirtualToplevel|UART1|Add10~17_sumout\);
-
--- Location: LABCELL_X14_Y9_N6
-\myVirtualToplevel|IO_DATA_READ~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~15_combout\ = ( \myVirtualToplevel|UART0|TX_ENABLE~q\ & ( \myVirtualToplevel|UART1|Add10~17_sumout\ & ( ((!\myVirtualToplevel|UART1|TX_ENABLE~q\ & (\myVirtualToplevel|UART1_CS~combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( !\myVirtualToplevel|UART0|TX_ENABLE~q\ & ( \myVirtualToplevel|UART1|Add10~17_sumout\ & ( ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) &
--- ((!\myVirtualToplevel|UART1|TX_ENABLE~q\) # (!\myVirtualToplevel|UART1_CS~combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)) ) ) ) # ( \myVirtualToplevel|UART0|TX_ENABLE~q\ & ( !\myVirtualToplevel|UART1|Add10~17_sumout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & (((!\myVirtualToplevel|UART1|TX_ENABLE~q\ & \myVirtualToplevel|UART1_CS~combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3)))) ) ) ) # ( !\myVirtualToplevel|UART0|TX_ENABLE~q\ & (
--- !\myVirtualToplevel|UART1|Add10~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ((!\myVirtualToplevel|UART1|TX_ENABLE~q\) # ((!\myVirtualToplevel|UART1_CS~combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111011000000000011101100110011111110110011001100111011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|UART1|ALT_INV_TX_ENABLE~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- datac => \myVirtualToplevel|ALT_INV_UART1_CS~combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- datae => \myVirtualToplevel|UART0|ALT_INV_TX_ENABLE~q\,
- dataf => \myVirtualToplevel|UART1|ALT_INV_Add10~17_sumout\,
- combout => \myVirtualToplevel|IO_DATA_READ~15_combout\);
-
--- Location: FF_X14_Y9_N7
-\myVirtualToplevel|IO_DATA_READ[23]_NEW_REG1304\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ~15_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\);
-
--- Location: FF_X16_Y11_N59
-\myVirtualToplevel|IO_DATA_READ[22]_NEW_REG1260\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[6]~DUPLICATE_q\,
- sload => VCC,
- ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\);
-
--- Location: FF_X13_Y11_N41
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~17_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y11_N24
-\myVirtualToplevel|Add13~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~25_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~22\ ))
--- \myVirtualToplevel|Add13~26\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[18]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add13~22\,
- sumout => \myVirtualToplevel|Add13~25_sumout\,
- cout => \myVirtualToplevel|Add13~26\);
-
--- Location: MLABCELL_X13_Y11_N27
-\myVirtualToplevel|Add13~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~29_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19) ) + ( VCC ) + ( \myVirtualToplevel|Add13~26\ ))
--- \myVirtualToplevel|Add13~30\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19) ) + ( VCC ) + ( \myVirtualToplevel|Add13~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(19),
- cin => \myVirtualToplevel|Add13~26\,
- sumout => \myVirtualToplevel|Add13~29_sumout\,
- cout => \myVirtualToplevel|Add13~30\);
-
--- Location: FF_X13_Y11_N29
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[19]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~29_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[19]~19_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(19));
-
--- Location: MLABCELL_X13_Y11_N30
-\myVirtualToplevel|Add13~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~13_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~30\ ))
--- \myVirtualToplevel|Add13~14\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add13~30\,
- sumout => \myVirtualToplevel|Add13~13_sumout\,
- cout => \myVirtualToplevel|Add13~14\);
-
--- Location: FF_X13_Y11_N32
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~13_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[20]~17_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[20]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y11_N33
-\myVirtualToplevel|Add13~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~5_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(21) ) + ( VCC ) + ( \myVirtualToplevel|Add13~14\ ))
--- \myVirtualToplevel|Add13~6\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(21) ) + ( VCC ) + ( \myVirtualToplevel|Add13~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(21),
- cin => \myVirtualToplevel|Add13~14\,
- sumout => \myVirtualToplevel|Add13~5_sumout\,
- cout => \myVirtualToplevel|Add13~6\);
-
--- Location: FF_X13_Y11_N35
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~5_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[21]~15_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(21));
-
--- Location: MLABCELL_X13_Y11_N36
-\myVirtualToplevel|Add13~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~9_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~6\ ))
--- \myVirtualToplevel|Add13~10\ = CARRY(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add13~6\,
- sumout => \myVirtualToplevel|Add13~9_sumout\,
- cout => \myVirtualToplevel|Add13~10\);
-
--- Location: FF_X13_Y11_N38
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~9_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[22]~16_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[22]~DUPLICATE_q\);
-
--- Location: MLABCELL_X13_Y11_N39
-\myVirtualToplevel|Add13~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|Add13~17_sumout\ = SUM(( \myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\ ) + ( VCC ) + ( \myVirtualToplevel|Add13~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER[23]~DUPLICATE_q\,
- cin => \myVirtualToplevel|Add13~10\,
- sumout => \myVirtualToplevel|Add13~17_sumout\);
-
--- Location: FF_X13_Y11_N40
-\myVirtualToplevel|MICROSEC_DOWN_COUNTER[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|Add13~17_sumout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|MICROSEC_DOWN_COUNTER~0_combout\,
- ena => \myVirtualToplevel|MICROSEC_DOWN_COUNTER[21]~2_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(23));
-
--- Location: LABCELL_X16_Y11_N39
-\myVirtualToplevel|IO_DATA_READ~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MILLISEC_UP_COUNTER\(23) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(3) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR\(2) & ( \myVirtualToplevel|MICROSEC_DOWN_COUNTER\(23) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101001100110011001100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MICROSEC_DOWN_COUNTER\(23),
- datab => \myVirtualToplevel|ALT_INV_MILLISEC_UP_COUNTER\(23),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(3),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR\(2),
- combout => \myVirtualToplevel|IO_DATA_READ~16_combout\);
-
--- Location: FF_X16_Y11_N41
-\myVirtualToplevel|IO_DATA_READ[23]_NEW_REG1306\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|IO_DATA_READ~16_combout\,
- ena => \myVirtualToplevel|IO_DATA_READ[0]~5_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|IO_DATA_READ[23]_OTERM1307\);
-
--- Location: LABCELL_X16_Y11_N54
-\myVirtualToplevel|IO_DATA_READ~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|IO_DATA_READ~17_combout\ = ( \myVirtualToplevel|IO_DATA_READ[23]_OTERM1307\ & ( (!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\ & (((\myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\)))) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\ &
--- ((!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\ & (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1263\)) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\ & ((\myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\))))) ) ) # (
--- !\myVirtualToplevel|IO_DATA_READ[23]_OTERM1307\ & ( (\myVirtualToplevel|IO_DATA_READ[23]_OTERM1305\ & ((!\myVirtualToplevel|IO_DATA_READ[22]_OTERM1265\) # (\myVirtualToplevel|IO_DATA_READ[22]_OTERM1261\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000001111000010100000111100011011000011110001101100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1265\,
- datab => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1263\,
- datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1305\,
- datad => \myVirtualToplevel|ALT_INV_IO_DATA_READ[22]_OTERM1261\,
- dataf => \myVirtualToplevel|ALT_INV_IO_DATA_READ[23]_OTERM1307\,
- combout => \myVirtualToplevel|IO_DATA_READ~17_combout\);
-
--- Location: LABCELL_X17_Y12_N18
-\myVirtualToplevel|MEM_DATA_READ[23]~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[23]~17_combout\ = ( \myVirtualToplevel|IO_DATA_READ~17_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|INTR0_CS~combout\) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\) ) ) ) # (
--- !\myVirtualToplevel|IO_DATA_READ~17_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & !\myVirtualToplevel|INTR0_CS~combout\) ) ) ) # ( \myVirtualToplevel|IO_DATA_READ~17_combout\ & (
--- !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ_SOCCFG\(23))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & ((\myVirtualToplevel|IO_DATA_READ_SD\(23)))) ) ) )
--- # ( !\myVirtualToplevel|IO_DATA_READ~17_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[18]~6_combout\ & ( (!\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\ & (\myVirtualToplevel|IO_DATA_READ_SOCCFG\(23))) # (\myVirtualToplevel|MEM_DATA_READ[18]~7_combout\
--- & ((\myVirtualToplevel|IO_DATA_READ_SD\(23)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0100011101000111010001110100011111001100000000001111111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SOCCFG\(23),
- datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~7_combout\,
- datac => \myVirtualToplevel|ALT_INV_IO_DATA_READ_SD\(23),
- datad => \myVirtualToplevel|ALT_INV_INTR0_CS~combout\,
- datae => \myVirtualToplevel|ALT_INV_IO_DATA_READ~17_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[18]~6_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[23]~17_combout\);
-
--- Location: FF_X19_Y12_N19
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_NEW_REG68\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll2_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\,
- sload => VCC,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\);
-
--- Location: LABCELL_X19_Y12_N9
-\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) # (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & (
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\ & !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[1]_OTERM1~DUPLICATE_q\) ) ) ) # (
--- \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\ ) ) ) # (
--- !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[7]_OTERM43\ & ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[24]_OTERM13\ & ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]_OTERM69\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011001100110011001100110000001100000011111100111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]_OTERM69\,
- datac => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[1]_OTERM1~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[7]_OTERM43\,
- dataf => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[24]_OTERM13\,
- combout => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\);
-
--- Location: LABCELL_X17_Y8_N30
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4_combout\ = (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT\(7))) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM3_WREN~0_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[23]~18_combout\)))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000111111001100000011111100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT\(7),
- datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|ALT_INV_RAM3_WREN~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[23]~18_combout\,
- combout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_DATA[7]~4_combout\);
-
--- Location: M10K_X30_Y8_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 7,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 7,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(1),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15_PORTBDATAOUT_bus\);
-
--- Location: M10K_X11_Y9_N0
-\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init3 => "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000022220000000000000000000E040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001FFFFFDA200010000000000000000000000000000000000000000000000000000000D7FFFED6A6F77090667FFFFFD4095FFFC1CB83FFE799D19E",
- mem_init2 => "E345FA0DF1A38C8004B3E01C84FD9E8081C820259F20721E4FD7C68E338BE35FE833DF82B3E6F0BC3FDA7AF45C9C2393DCE7198E6CD63A2B6EA7041E7065FC0A83223081CBF603F0E5FB01F873FF8C305A7394119C6326151AEE003DF1F11837840C40FFFFF9F3EA439943FFF26F17160C9C16580BD0048EE36C9DB550CEE1E8E15574653A2C0B601811010DB0091E70092B318342E083C16F0C8EC880826F8E521A00998A309116D1C083BC02CA339F497DC6313FC62BC069C17E3123A22B72882C81F9EA0DD60BA9A8845218A3320BFE8BA51D971CA47A7642608C618F7BA53CE037E09278418EB2142241470F84651FECB13E123F424189E0890DE8430C79",
- mem_init1 => "0C0C084841BCC4C8791000001978502800140080213B1C481EF23C0E6007E7A7873B046FE01E990050030D8C708002E22A6F6230494451C0BE0428001713D8445B23C09B8221F9982CE768DC23196848E14860639E705301EC03840001C5F89E69908A91F610B69E5403F22044EECFD575604A617CC631482A7FE3C7ABFA7C78004826AE4C3C143D2949A35278C803C8281B2906040504285020A9008B00CDC48601806080108008822C47A0D2BBCE39DC3E7C41D337EA5E84116491A819E386222CE1C9371B9C3568B30A3C00810CA904A6208887DDEF480B07914000801010D0E1020000000BC3400048F00839F727BCE721121C0A44848400198100400F02",
- mem_init0 => "85AD6B55811928ACD904E4E08C945661014E1C725CB4240C340006D580A200903057DCAA0010401A28024630F7EDE0A0204003422819011014120197998A88000084B68C28484FBE00CDC491FF41F73F06237FFFE3F8D1E23C58B162C58E24C51E465BBC25637784AC6EF09E73F9FCFE4C8DAB93522B24DD1434C628AA8AC0E040BB007016739CA76AAB4C9249E60902A21C0920A4162088402940124AFE2AAE1E45F71CD816BFAB3E67BF0833756567CCFD52FECAD0060001FFC3FFFFFFFFFFFFFFFFFFFFFFFFFFF87FF0FFE1FFC3FEFFFFFFFFFFFC924924924924924924FEF8000100010001042020202113000000000800020200000000040000AB130000",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram2_SinglePortBootBRAM_affed8c6.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|SinglePortBootBRAM:\ZPUBRAMEVO:ZPUBRAM|altsyncram:RAM2_rtl_0|altsyncram_f902:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "old",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 13,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 1,
- port_a_first_address => 0,
- port_a_first_bit_number => 7,
- port_a_last_address => 8191,
- port_a_logical_ram_depth => 16384,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock0",
- port_b_address_width => 13,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 1,
- port_b_first_address => 0,
- port_b_first_bit_number => 7,
- port_b_last_address => 8191,
- port_b_logical_ram_depth => 16384,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock0",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|decode2|eq_node\(0),
- portbre => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_WREN~1_combout\,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- portadatain => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7_PORTBDATAOUT_bus\);
-
--- Location: MLABCELL_X18_Y12_N39
-\myVirtualToplevel|MEM_DATA_READ[23]~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\ & (
--- \myVirtualToplevel|LessThan0~1_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\ & ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\ & (
--- (!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\) ) ) ) # ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a15~portbdataout\ & (
--- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ram_block1a7~portbdataout\ & ( (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|address_reg_b\(0) & \myVirtualToplevel|LessThan0~1_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000101010100000000101010100000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_address_reg_b\(0),
- datad => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\,
- datae => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a15~portbdataout\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7~portbdataout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\);
-
--- Location: MLABCELL_X18_Y12_N51
-\myVirtualToplevel|MEM_DATA_READ[23]~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\ = ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ & (
--- \myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ ) ) # ( \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ & ( ((\myVirtualToplevel|MEM_DATA_READ[23]~17_combout\ &
--- \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[23]~8_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[23]~18_combout\ & (
--- (\myVirtualToplevel|MEM_DATA_READ[23]~17_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011010101010111011111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\,
- datab => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~17_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\,
- datae => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[23]~8_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~18_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[23]~19_combout\);
-
--- Location: MLABCELL_X9_Y16_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[23]~19_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23) & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_ADDR[23]~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux19~2_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|MEM_DATA_OUT[16]~2_combout\ & ((\myVirtualToplevel|MEM_DATA_READ[23]~19_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23) & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[29]~2_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100010000000101011011101010111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_ADDR[23]~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux19~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_MEM_DATA_OUT[16]~2_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[23]~19_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(23),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData[29]~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25_combout\);
-
--- Location: FF_X9_Y16_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData[23]~25_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23));
-
--- Location: MLABCELL_X9_Y16_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteHword~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(7) & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteData\(23) & !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL2WriteByte~q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101000001010000000000000000000001011111010111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(23),
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteByte~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteHword~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL2WriteData\(7),
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_DATA[7]~5_combout\);
-
--- Location: M10K_X22_Y34_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0\ : cyclonev_ram_block
--- pragma translate_off
-GENERIC MAP (
- mem_init4 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init3 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init2 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init1 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- mem_init0 => "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000",
- clk0_core_clock_enable => "ena0",
- data_interleave_offset_in_bits => 1,
- data_interleave_width_in_bits => 1,
- init_file => "db/QMV_zpu.ram2_evo_L2cache_a612c956.hdl.mif",
- init_file_layout => "port_a",
- logical_ram_name => "zpu_soc:myVirtualToplevel|zpu_core_evo:\ZPUEVO:ZPU0|evo_L2cache:CACHEL2|altsyncram:RAM2_rtl_0|altsyncram_dnn1:auto_generated|ALTSYNCRAM",
- mixed_port_feed_through_mode => "dont_care",
- operation_mode => "dual_port",
- port_a_address_clear => "none",
- port_a_address_width => 10,
- port_a_byte_enable_clock => "none",
- port_a_data_out_clear => "none",
- port_a_data_out_clock => "none",
- port_a_data_width => 10,
- port_a_first_address => 0,
- port_a_first_bit_number => 0,
- port_a_last_address => 1023,
- port_a_logical_ram_depth => 1024,
- port_a_logical_ram_width => 8,
- port_a_read_during_write_mode => "new_data_no_nbe_read",
- port_b_address_clear => "none",
- port_b_address_clock => "clock1",
- port_b_address_width => 10,
- port_b_data_out_clear => "none",
- port_b_data_out_clock => "none",
- port_b_data_width => 10,
- port_b_first_address => 0,
- port_b_first_bit_number => 0,
- port_b_last_address => 1023,
- port_b_logical_ram_depth => 1024,
- port_b_logical_ram_width => 8,
- port_b_read_during_write_mode => "new_data_no_nbe_read",
- port_b_read_enable_clock => "clock1",
- ram_block_type => "M20K")
--- pragma translate_on
-PORT MAP (
- portawe => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0_combout\,
- portbre => VCC,
- clk0 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- clk1 => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- ena0 => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_WREN~0_combout\,
- portadatain => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTADATAIN_bus\,
- portaaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTAADDR_bus\,
- portbaddr => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBADDR_bus\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- portbdataout => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus\);
-
--- Location: LABCELL_X31_Y30_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111101111111100000001000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340_combout\);
-
--- Location: FF_X31_Y30_N8
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\);
-
--- Location: LABCELL_X31_Y30_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\
--- & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~0_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336_combout\);
-
--- Location: FF_X31_Y30_N41
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\);
-
--- Location: LABCELL_X31_Y30_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ & \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000000000011001111111111001100111111111100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6_combout\);
-
--- Location: LABCELL_X26_Y29_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_NEW1828\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_OTERM1829\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_OTERM1829\);
-
--- Location: FF_X26_Y29_N38
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_OTERM1829\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~q\);
-
--- Location: FF_X26_Y29_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_OTERM1827\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\);
-
--- Location: LABCELL_X26_Y29_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_NEW1826\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_OTERM1827\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][13]~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][13]~20_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_OTERM1827\);
-
--- Location: FF_X26_Y29_N32
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]_OTERM1827\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y29_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4_combout\);
-
--- Location: LABCELL_X26_Y29_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342_combout\);
-
--- Location: FF_X26_Y29_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\);
-
--- Location: LABCELL_X26_Y29_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~2_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111101100000000000001001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338_combout\);
-
--- Location: FF_X26_Y29_N11
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\);
-
--- Location: LABCELL_X26_Y29_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100110011001100110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7_combout\);
-
--- Location: FF_X23_Y30_N34
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\);
-
--- Location: MLABCELL_X23_Y30_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) #
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000100001111111110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353_combout\);
-
--- Location: FF_X23_Y30_N35
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~353_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE_q\);
-
--- Location: MLABCELL_X23_Y30_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~6_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111101100000000000001001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352_combout\);
-
--- Location: FF_X23_Y30_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\);
-
--- Location: MLABCELL_X23_Y30_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~DUPLICATE_q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5_combout\);
-
--- Location: LABCELL_X29_Y28_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~7_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~6_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~5_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~4_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100110011000000001111111101010101010101010000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~7_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~5_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\);
-
--- Location: LABCELL_X26_Y31_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000101111111111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339_combout\);
-
--- Location: FF_X26_Y31_N26
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\);
-
--- Location: LABCELL_X26_Y31_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343_combout\);
-
--- Location: FF_X26_Y31_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~343_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\);
-
--- Location: LABCELL_X26_Y28_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000001111000011111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15_combout\);
-
--- Location: LABCELL_X29_Y30_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~1_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341_combout\);
-
--- Location: FF_X29_Y30_N59
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\);
-
--- Location: LABCELL_X29_Y30_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14_combout\);
-
--- Location: FF_X26_Y31_N29
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\);
-
--- Location: LABCELL_X26_Y31_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000101111111111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356_combout\);
-
--- Location: FF_X26_Y31_N28
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~356_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y29_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ &
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~7_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111110111100000000000100001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~7_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357_combout\);
-
--- Location: FF_X26_Y29_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~357_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\);
-
--- Location: MLABCELL_X28_Y28_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~DUPLICATE_q\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13_combout\);
-
--- Location: FF_X26_Y30_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\);
-
--- Location: LABCELL_X26_Y30_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ram_block1a7\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111101111111100000001000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM2_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363_combout\);
-
--- Location: FF_X26_Y30_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~363_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\);
-
--- Location: FF_X26_Y30_N44
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\);
-
--- Location: LABCELL_X26_Y30_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ram_block1a7\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Decoder4~5_combout\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][8]~1_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|CACHE_LEVEL1~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan12~26_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111110100000000000000101111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan12~26_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Decoder4~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][8]~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_CACHE_LEVEL1~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|CACHEL2|RAM3_rtl_0|auto_generated|ALT_INV_ram_block1a7\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362_combout\);
-
--- Location: FF_X26_Y30_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~362_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X29_Y30_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12_combout\);
-
--- Location: LABCELL_X29_Y28_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~15_combout\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~14_combout\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~13_combout\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~5_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add22~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux182~12_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000011110000111100110011001100110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~15_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~14_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~13_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~12_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~5_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\);
-
--- Location: LABCELL_X29_Y28_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~0_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[1]~DUPLICATE_q\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~1_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add22~17_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~3_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000100001001100001010100110111000011001010111010011101101111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add22~17_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[1]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~3_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\);
-
--- Location: FF_X26_Y31_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~359_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X25_Y28_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011010100110101001101010011010100000000000011111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\);
-
--- Location: FF_X26_Y30_N46
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~364_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X25_Y28_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101111101011111010100110000001111110011000000111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\);
-
--- Location: FF_X26_Y29_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]_OTERM1829\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\);
-
--- Location: FF_X26_Y30_N31
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~360_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X26_Y30_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001101010101001100110101010100000000000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\);
-
--- Location: FF_X23_Y30_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~354_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\);
-
--- Location: FF_X23_Y30_N49
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~352_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\);
-
--- Location: FF_X23_Y30_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~355_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y30_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\))) ) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100001111001100110000111100000000010101011111111101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\);
-
--- Location: LABCELL_X25_Y28_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\) #
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~7_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~5_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~8_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~6_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000100100011100010011010101101000101011001111100110111101111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~6_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~8_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~7_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\);
-
--- Location: FF_X26_Y31_N13
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~351_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\);
-
--- Location: LABCELL_X25_Y28_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101001100110011001100001111000011110000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\);
-
--- Location: FF_X26_Y31_N52
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~345_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\);
-
--- Location: FF_X26_Y29_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~346_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X25_Y28_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111001100110011001101010101010101010000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\);
-
--- Location: FF_X26_Y29_N16
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~342_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X25_Y28_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101000000001111111100001111000011110011001100110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\);
-
--- Location: FF_X31_Y30_N40
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~336_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X25_Y28_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add37~5_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000011110000111100110011001100110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\);
-
--- Location: LABCELL_X25_Y28_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~1_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~17_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~3_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~2_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000001000111110011000100011100110011010001111111111101000111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~3_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~2_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~17_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~1_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\);
-
--- Location: LABCELL_X25_Y28_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011110000000000001111000000001111111111110000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~9_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\);
-
--- Location: MLABCELL_X28_Y25_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678_BDD12679\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~69_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~61_sumout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~61_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~69_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678_BDD12679\);
-
--- Location: MLABCELL_X28_Y27_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_RESYN12678_BDD12679\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~65_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~49_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~53_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~57_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000100000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~65_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~49_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~53_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~57_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_RESYN12678_BDD12679\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\);
-
--- Location: MLABCELL_X28_Y25_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670_BDD12671\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~9_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~25_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~45_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~21_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~17_sumout\))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1000000000000000100000000000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~25_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~45_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~21_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~17_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670_BDD12671\);
-
--- Location: MLABCELL_X28_Y25_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~29_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_RESYN12670_BDD12671\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~41_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~33_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~13_sumout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~37_sumout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~41_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~33_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~13_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~37_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~29_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_RESYN12670_BDD12671\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\);
-
--- Location: LABCELL_X25_Y27_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~4_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Add17~89_sumout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000000000000110000001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~89_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~4_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\);
-
--- Location: LABCELL_X24_Y27_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan19~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux183~10_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000011000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~10_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan19~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\);
-
--- Location: LABCELL_X25_Y28_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux184~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|Mux182~0_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~9_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add37~1_sumout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux183~4_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000110110000000000011011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add37~1_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~4_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux183~9_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux182~0_Duplicate_33\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux184~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\);
-
--- Location: LABCELL_X25_Y29_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[7][7]~q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[6][7]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[5][7]~DUPLICATE_q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[4][7]~DUPLICATE_q\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101001101010011010100110101001100000000111100000000111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[5][7]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[4][7]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[7][7]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[6][7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\);
-
--- Location: LABCELL_X24_Y30_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[10][7]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[11][7]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[9][7]~q\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[8][7]~DUPLICATE_q\))) ) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000111111001100000011111100000101000001011111010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[10][7]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[9][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[8][7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[11][7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\);
-
--- Location: LABCELL_X26_Y30_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[2][7]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[3][7]~q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[1][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc\(0) & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[0][7]~DUPLICATE_q\)) ) )
--- )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011010100110101001101010011010100000000000011111111000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[0][7]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[1][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc\(0),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[2][7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[3][7]~q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\);
-
--- Location: LABCELL_X25_Y28_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[14][7]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[15][7]~DUPLICATE_q\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[13][7]~q\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[12][7]~q\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001101010101001100110101010100000000000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[12][7]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[13][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[14][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[15][7]~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\);
-
--- Location: LABCELL_X24_Y26_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~8_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~7_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000110100110001001111010000000111001101111100011111110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~7_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~8_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\);
-
--- Location: FF_X26_Y31_N25
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~339_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE_q\);
-
--- Location: FF_X26_Y29_N10
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~338_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X29_Y31_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[28][7]~DUPLICATE_q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[24][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[20][7]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[16][7]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000000001111111100110011001100110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[28][7]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[24][7]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[16][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[20][7]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\);
-
--- Location: FF_X29_Y30_N58
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~341_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\);
-
--- Location: FF_X31_Y30_N7
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~340_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X29_Y31_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[29][7]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[25][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[21][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[17][7]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111001100110011001100001111000011110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[29][7]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[21][7]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[25][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[17][7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\);
-
--- Location: LABCELL_X24_Y27_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[31][7]~q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[27][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[23][7]~q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[19][7]~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101001100110011001100000000111111110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[19][7]~q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[23][7]~q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[31][7]~q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[27][7]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\);
-
--- Location: FF_X26_Y31_N43
-\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~347_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE_q\);
-
--- Location: LABCELL_X24_Y26_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[30][7]~DUPLICATE_q\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[22][7]~DUPLICATE_q\ ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[26][7]~DUPLICATE_q\ ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~13_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add23~9_sumout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1[18][7]~q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000011110000111100110011001100110101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[30][7]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[22][7]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[26][7]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1[18][7]~q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~13_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~9_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\);
-
--- Location: LABCELL_X24_Y26_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~3_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~2_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~21_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~1_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[0]~DUPLICATE_q\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~0_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000001010001010010001101100111000010011100110110101011111011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~21_sumout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[0]~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~1_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~3_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~2_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\);
-
--- Location: LABCELL_X29_Y26_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add17~5_sumout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan13~0_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add17~1_sumout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100001111111111110000111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~1_sumout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan13~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add17~5_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\);
-
--- Location: LABCELL_X25_Y26_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~2_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_RESYN12672_BDD12673\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan25~1_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~9_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Add23~5_sumout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux181~4_combout\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101011110000101010101111000010001000110000001010101011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~9_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux181~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add23~5_sumout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_RESYN12672_BDD12673\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan25~1_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\);
-
--- Location: LABCELL_X24_Y26_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~4_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~3_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~6_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000010101010000000001010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~3_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~6_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~4_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\);
-
--- Location: LABCELL_X19_Y26_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\))))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux161~4_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) #
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux154~10_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~9_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|Selector386~7_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~21_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|Mux168~10_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111001100101110111000100011110000110000001011000010000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux154~10_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~21_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux161~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux168~10_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~9_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Selector386~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1002~1_combout\);
-
--- Location: LABCELL_X20_Y14_N12
-\myVirtualToplevel|MEM_DATA_READ[2]~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ = ( \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ &
--- ((!\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\) # (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\))) ) ) # (
--- !\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a2~portbdataout\ & ( (\myVirtualToplevel|LessThan0~1_combout\ & (\myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|address_reg_b[0]~DUPLICATE_q\ &
--- \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ram_block1a10~portbdataout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000011000000000000001100110000001100110011000000110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ALT_INV_LessThan0~1_combout\,
- datac => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_address_reg_b[0]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a10~portbdataout\,
- dataf => \myVirtualToplevel|ZPUBRAMEVO:ZPUBRAM|RAM0_rtl_0|auto_generated|ALT_INV_ram_block1a2~portbdataout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\);
-
--- Location: MLABCELL_X18_Y15_N36
-\myVirtualToplevel|MEM_DATA_READ[2]~38\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|MEM_DATA_READ[2]~38_combout\ = ( \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & (
--- \myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ ) ) # ( \myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ & ( ((\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ &
--- \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\)) # (\myVirtualToplevel|MEM_DATA_READ[2]~36_combout\) ) ) ) # ( !\myVirtualToplevel|MEM_DATA_READ[2]~4_combout\ & ( !\myVirtualToplevel|MEM_DATA_READ[2]~37_combout\ & (
--- (\myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|DATA_OUT[2]~25_combout\ & \myVirtualToplevel|MEM_DATA_READ[2]~5_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000011110011111111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUSDRAMEVO:ZPUSDRAM|ALT_INV_DATA_OUT[2]~25_combout\,
- datac => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~36_combout\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~5_combout\,
- datae => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~4_combout\,
- dataf => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[2]~37_combout\,
- combout => \myVirtualToplevel|MEM_DATA_READ[2]~38_combout\);
-
--- Location: FF_X18_Y15_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|MEM_DATA_READ[2]~38_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(2));
-
--- Location: FF_X19_Y18_N17
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[2]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[21]~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(2));
-
--- Location: LABCELL_X19_Y18_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(2) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.valid~q\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word\(2) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.word\(2),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_NOS.word\(2),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxNOS.valid~q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\);
-
--- Location: DSP_X8_Y23_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8\ : cyclonev_mac
--- pragma translate_off
-GENERIC MAP (
- accumulate_clock => "none",
- ax_clock => "none",
- ax_width => 18,
- ay_scan_in_clock => "none",
- ay_scan_in_width => 18,
- ay_use_scan_in => "false",
- az_clock => "none",
- bx_clock => "none",
- by_clock => "none",
- by_use_scan_in => "false",
- bz_clock => "none",
- coef_a_0 => 0,
- coef_a_1 => 0,
- coef_a_2 => 0,
- coef_a_3 => 0,
- coef_a_4 => 0,
- coef_a_5 => 0,
- coef_a_6 => 0,
- coef_a_7 => 0,
- coef_b_0 => 0,
- coef_b_1 => 0,
- coef_b_2 => 0,
- coef_b_3 => 0,
- coef_b_4 => 0,
- coef_b_5 => 0,
- coef_b_6 => 0,
- coef_b_7 => 0,
- coef_sel_a_clock => "none",
- coef_sel_b_clock => "none",
- delay_scan_out_ay => "false",
- delay_scan_out_by => "false",
- enable_double_accum => "false",
- load_const_clock => "none",
- load_const_value => 0,
- mode_sub_location => 0,
- negate_clock => "none",
- operand_source_max => "input",
- operand_source_may => "input",
- operand_source_mbx => "input",
- operand_source_mby => "input",
- operation_mode => "m18x18_full",
- output_clock => "0",
- preadder_subtract_a => "false",
- preadder_subtract_b => "false",
- result_a_width => 64,
- signed_max => "false",
- signed_may => "false",
- signed_mbx => "false",
- signed_mby => "false",
- sub_clock => "none",
- use_chainadder => "false")
--- pragma translate_on
-PORT MAP (
- sub => GND,
- negate => GND,
- aclr => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ACLR_bus\,
- clk => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_CLK_bus\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_ENA_bus\,
- ax => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AX_bus\,
- ay => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_AY_bus\,
- resulta => \myVirtualToplevel|ZPUEVO:ZPU0|Mult0~8_RESULTA_bus\);
-
--- Location: LABCELL_X1_Y33_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt[0]~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|bitCnt\(1) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt\(1),
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_bitCnt[0]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Decoder11~10_combout\);
-
--- Location: MLABCELL_X18_Y17_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[28]~feeder_combout\);
-
--- Location: LABCELL_X14_Y24_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux253~20_Duplicate_22\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux253~20_Duplicate_22\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\);
-
--- Location: LABCELL_X14_Y24_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778_BDD12779\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111100111111111111110010101010101010001010101010101000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778_BDD12779\);
-
--- Location: LABCELL_X14_Y24_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_RESYN12778_BDD12779\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~1_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~5_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~21_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux147~10_Duplicate_12\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010000000100010001000000010001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~5_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~21_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux147~10_Duplicate_12\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_RESYN12778_BDD12779\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\);
-
--- Location: LABCELL_X19_Y24_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ $
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111110000111111111111000010011001100100001001100110010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\);
-
--- Location: LABCELL_X19_Y24_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~119\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_RESYN8671_BDD8672\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001010101000000000000000001100000010001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_RESYN8671_BDD8672\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_combout\);
-
--- Location: LABCELL_X19_Y24_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~120\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~119_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\)))) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000010101111101011101010111110101110",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~119_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~120_combout\);
-
--- Location: MLABCELL_X23_Y24_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000000000000000011110000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~20_combout\);
-
--- Location: LABCELL_X19_Y24_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669_BDD8670\ = (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\)
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111100001111111111110000111111111111000011111111111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~116_RESYN8669_BDD8670\);
-
--- Location: FF_X18_Y17_N50
-\myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[29]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- asdata => \myVirtualToplevel|MEM_DATA_READ[29]~44_combout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => VCC,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word[31]~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxNOS.word\(29));
-
--- Location: MLABCELL_X18_Y17_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0101010101010101010101010101010101010101010101010101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[29]~feeder_combout\);
-
--- Location: MLABCELL_X18_Y20_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~29_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~27\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~27\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010000000000000000000000001010101001010101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~26\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~27\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\);
-
--- Location: MLABCELL_X18_Y19_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001100110000000000000000001100110000110011",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~30\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~31\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\);
-
--- Location: MLABCELL_X18_Y19_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~5_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~14\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~15\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\);
-
--- Location: MLABCELL_X18_Y19_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~6\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~7\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\);
-
--- Location: MLABCELL_X18_Y19_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010000000000000000000000001010101001010101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~10\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~11\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~17_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\);
-
--- Location: MLABCELL_X18_Y19_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~109\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~18\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~19\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~109_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\);
-
--- Location: MLABCELL_X18_Y19_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~105\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~105_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~110\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~111\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~105_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\);
-
--- Location: MLABCELL_X18_Y19_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~101\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~101_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011000000110000000000000000001100001111000011",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~106\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~107\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~101_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\);
-
--- Location: MLABCELL_X18_Y19_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~97\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010100000101000000000000000000001010010110100101",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~102\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~103\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~97_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\);
-
--- Location: MLABCELL_X18_Y19_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~113\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~98\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~99\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~113_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\);
-
--- Location: MLABCELL_X18_Y19_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~117\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~117_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\ = SHARE((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000001111000000000000000000001111000000001111",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~114\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~115\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~117_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\);
-
--- Location: LABCELL_X12_Y24_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~160\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Mux252~20_Duplicate_22\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011110000111111111111111111110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux252~20_Duplicate_22\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\);
-
--- Location: MLABCELL_X13_Y24_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~155\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~160_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010100000001000000000101000101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~160_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\);
-
--- Location: MLABCELL_X13_Y24_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~156\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~13_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~155_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111111110011001011110000111100000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~13_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~155_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~156_combout\);
-
--- Location: LABCELL_X16_Y24_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~37_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~35_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111110000111111111111000000110011001100000011001100110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~35_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~37_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\);
-
--- Location: LABCELL_X16_Y24_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\)))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~29_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|pc[12]~16_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101011111010111110101111101011001000001100101100100000110010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_pc[12]~16_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~29_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\);
-
--- Location: LABCELL_X17_Y25_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~5_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~10_combout\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010101010101010101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\);
-
--- Location: LABCELL_X16_Y24_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8673_BDD8674\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~7_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_RESYN8675_BDD8676\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\) # ((\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~1_combout\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~32_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000011010000110000000000000000000000111100001100",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~1_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8675_BDD8676\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~32_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~127_RESYN8673_BDD8674\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~7_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~127_combout\);
-
--- Location: LABCELL_X14_Y24_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~30_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|Equal145~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011111111111100001111111111110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Equal145~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~30_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~17_combout\);
-
--- Location: LABCELL_X19_Y19_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\
--- & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000110011000111010001110111001100111111110001110100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\);
-
--- Location: LABCELL_X14_Y24_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000000000000111100000000000011110000111100001111000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\);
-
--- Location: MLABCELL_X13_Y18_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011001100000000000011110101010100110011111111110000111101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\);
-
--- Location: LABCELL_X14_Y18_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000011111111000000001111111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\);
-
--- Location: LABCELL_X17_Y18_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111000011110000111100001111000000000000111100000000000011110000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\);
-
--- Location: LABCELL_X17_Y18_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\);
-
--- Location: MLABCELL_X18_Y18_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000011011010101010001101110101010000110111111111100011011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\);
-
--- Location: LABCELL_X14_Y18_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~128\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\)) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~19_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~5_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ & \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~18_combout\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101000000111111001111110101111101010000001111110011",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~18_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~19_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~5_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\);
-
--- Location: LABCELL_X19_Y19_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000011010000101010001111110110000101110101011010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\);
-
--- Location: MLABCELL_X18_Y19_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & (
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ &
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ &
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000001110000001010100111101000100101011101010010111101111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\);
-
--- Location: MLABCELL_X18_Y19_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\))) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000101000000000000010100000000001011111000000000101111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\);
-
--- Location: LABCELL_X16_Y18_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001101100011011000110110001101100000000010101011010101011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\);
-
--- Location: LABCELL_X17_Y19_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\) ) ) )
--- # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\))))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ &
--- (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~10_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~11_combout\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~6_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~8_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010000000101010001001010010111101110000011110100111010101111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~6_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~8_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~10_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~11_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\);
-
--- Location: LABCELL_X14_Y24_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~129\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\)))) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~128_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~35_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~21_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~45_combout\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~20_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~7_combout\)))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000011101001100110001110111001100000111011111111100011101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~7_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~20_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~45_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~21_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~128_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~35_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\);
-
--- Location: LABCELL_X14_Y24_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677_BDD8678\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~23_combout\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~129_combout\ )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111111111111111111111111111111111111111000000001111111100000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~23_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~129_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~134_RESYN8677_BDD8678\);
-
--- Location: FF_X18_Y22_N37
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector1346~4_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|DEBUG:DEBUGUART|ALT_INV_READY~0_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\);
-
--- Location: LABCELL_X19_Y16_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add7~93\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~93_sumout\ = SUM(( \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add7~94\ = CARRY(( \myVirtualToplevel|MEM_DATA_READ[1]~65_Duplicate_152\ ) + ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & (\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]~DUPLICATE_q\)) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111110100101000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[1]~DUPLICATE_q\,
- datad => \myVirtualToplevel|ALT_INV_MEM_DATA_READ[1]~65_Duplicate_152\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[1]~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~90\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~93_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~94\);
-
--- Location: FF_X17_Y16_N14
-\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[1]\ : dffeas
--- pragma translate_off
-GENERIC MAP (
- is_wysiwyg => "true",
- power_up => "low")
--- pragma translate_on
-PORT MAP (
- clk => \mypll|altpll_component|auto_generated|wire_generic_pll1_outclk~CLKENA0_outclk\,
- d => \myVirtualToplevel|ZPUEVO:ZPU0|Selector357~1_combout\,
- asdata => \myVirtualToplevel|ZPUEVO:ZPU0|Add7~93_sumout\,
- clrn => \myVirtualToplevel|RESET_n~q\,
- sload => \myVirtualToplevel|ZPUEVO:ZPU0|mxState.MemXact_ReadAddToTOS~q\,
- ena => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS~1_combout\,
- devclrn => ww_devclrn,
- devpor => ww_devpor,
- q => \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(1));
-
--- Location: LABCELL_X17_Y16_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(1) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word\(1) &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.word[0]~DUPLICATE_q\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[1]~DUPLICATE_q\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[0]~DUPLICATE_q\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1010101010101010110011000000000000000000000000001100110000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[0]~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word\(1),
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.word[0]~DUPLICATE_q\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[1]~DUPLICATE_q\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\);
-
--- Location: LABCELL_X16_Y20_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ = ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\) # (!\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight1~5_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "1111101011111010111110101111101000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight1~5_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\);
-
--- Location: LABCELL_X14_Y20_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~3_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\) # (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000000000000011110101111101011111010111110101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~3_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|Selector978~2_combout\);
-
--- Location: MLABCELL_X23_Y18_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]~feeder\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]~feeder_combout\ = \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100001111000011110000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|NOS.word[30]~feeder_combout\);
-
--- Location: LABCELL_X20_Y24_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466_BDD13467\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\) # (\myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|LessThan16~0_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|cacheL1Invalid~5_combout\ & \myVirtualToplevel|ZPUEVO:ZPU0|Mux251~20_Duplicate_22\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000001111111100001111111100000000000000001111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_cacheL1Invalid~5_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux251~20_Duplicate_22\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan16~0_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466_BDD13467\);
-
--- Location: LABCELL_X19_Y21_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~89\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ ) + ( !VCC ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- cin => GND,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\);
-
--- Location: LABCELL_X19_Y21_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~93\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~93_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010101000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~90\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~93_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\);
-
--- Location: LABCELL_X19_Y21_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~85\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~94\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~85_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\);
-
--- Location: LABCELL_X19_Y21_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~81\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~86\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~81_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\);
-
--- Location: LABCELL_X19_Y21_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~49\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~49_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~82\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~49_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\);
-
--- Location: LABCELL_X19_Y21_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~53\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~53_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[5]~13_Duplicate_44\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[5]~13_Duplicate_44\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~50\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~53_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\);
-
--- Location: LABCELL_X19_Y21_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~69\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~69_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[6]~17_Duplicate_46\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110011001100110000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[6]~17_Duplicate_46\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~54\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~69_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\);
-
--- Location: LABCELL_X19_Y21_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~73\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[7]~18_Duplicate_42\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010101000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[7]~18_Duplicate_42\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~70\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~73_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\);
-
--- Location: LABCELL_X19_Y21_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~77\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[8]~19_Duplicate_48\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110011001100110000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[8]~19_Duplicate_48\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~74\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~77_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\);
-
--- Location: LABCELL_X19_Y21_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~57\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[9]~14_Duplicate_45\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[9]~14_Duplicate_45\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~78\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~57_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\);
-
--- Location: LABCELL_X19_Y21_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~61\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~61_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[10]~15_Duplicate_47\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000110011001100110000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[10]~15_Duplicate_47\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~58\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~61_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\);
-
--- Location: LABCELL_X19_Y21_N33
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~65\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~65_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[11]~16_Duplicate_43\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010101000000000000000000000111100001111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[11]~16_Duplicate_43\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~62\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~65_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\);
-
--- Location: LABCELL_X19_Y21_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~33\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~33_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[12]~8_Duplicate_49\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[12]~8_Duplicate_49\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~66\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~33_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\);
-
--- Location: LABCELL_X19_Y21_N39
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~37\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[13]~9_Duplicate_52\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[13]~9_Duplicate_52\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~34\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~37_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\);
-
--- Location: LABCELL_X19_Y21_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~41\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[14]~10_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[14]~10_Duplicate_54\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~38\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~41_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\);
-
--- Location: LABCELL_X19_Y21_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~45\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~45_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[15]~11_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[15]~10_Duplicate_37\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000101010101010101000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[15]~10_Duplicate_37\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[15]~11_Duplicate_50\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~42\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~45_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\);
-
--- Location: LABCELL_X19_Y21_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~1\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[16]~0_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[16]~1_Duplicate_52\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[16]~1_Duplicate_52\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[16]~0_Duplicate_56\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~46\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~1_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\);
-
--- Location: LABCELL_X19_Y21_N51
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~21\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[17]~4_Duplicate_50\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[17]~5_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[17]~5_Duplicate_53\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[17]~4_Duplicate_50\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~2\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~21_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\);
-
--- Location: LABCELL_X19_Y21_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~25\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~25_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[18]~3_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[18]~6_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[18]~6_Duplicate_55\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[18]~3_Duplicate_51\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~22\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~25_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\);
-
--- Location: LABCELL_X19_Y21_N57
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~29\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[19]~7_Duplicate_51\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[19]~8_Duplicate_49\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[19]~7_Duplicate_51\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~26\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~29_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\);
-
--- Location: LABCELL_X19_Y20_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[20]~3_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[20]~3_Duplicate_57\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[20]~7_Duplicate_53\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~30\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~13_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\);
-
--- Location: LABCELL_X19_Y20_N3
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~5\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~5_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[21]~1_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[21]~1_Duplicate_61\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[21]~30_Duplicate_57\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~14\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~5_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\);
-
--- Location: LABCELL_X19_Y20_N6
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~9\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[22]~2_Duplicate_63\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[22]~2_Duplicate_63\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[22]~29_Duplicate_59\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~6\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~9_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\);
-
--- Location: LABCELL_X19_Y20_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~17\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[23]~21_Duplicate_55\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[23]~21_Duplicate_55\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~10\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~17_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\);
-
--- Location: LABCELL_X19_Y20_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~109\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[24]~24_Duplicate_60\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[24]~24_Duplicate_60\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~18\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~109_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\);
-
--- Location: LABCELL_X19_Y20_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~105\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[25]~19_Duplicate_56\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[25]~19_Duplicate_56\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~110\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~105_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\);
-
--- Location: LABCELL_X19_Y20_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~101\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[26]~18_Duplicate_58\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[26]~18_Duplicate_58\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~106\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~101_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\);
-
--- Location: LABCELL_X19_Y20_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~97\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[27]~20_Duplicate_54\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000101010101010101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[27]~20_Duplicate_54\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~102\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~97_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\);
-
--- Location: LABCELL_X19_Y20_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~113\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[28]~17_Duplicate_61\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[28]~17_Duplicate_61\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~98\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~113_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\);
-
--- Location: LABCELL_X19_Y20_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~117\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~117_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[29]~23_Duplicate_65\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[29]~23_Duplicate_65\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~114\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~117_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\);
-
--- Location: LABCELL_X19_Y20_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add33~121\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\ = SUM(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~122\ = CARRY(( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111100001111000000000000000000000000000011111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~118\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add33~122\);
-
--- Location: MLABCELL_X18_Y19_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add34~121\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~122\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ $ (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\) ) + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\ ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add34~123\ = SHARE((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100000011000000000000000000001100001111000011",
- shared_arith => "on")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~118\,
- sharein => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~119\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~122\,
- shareout => \myVirtualToplevel|ZPUEVO:ZPU0|Add34~123\);
-
--- Location: LABCELL_X20_Y24_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~28_combout\ ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add33~121_sumout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|Add34~121_sumout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS.word[29]~2_combout\ ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000010101010101010100001111000011110101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.word[29]~2_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~28_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add33~121_sumout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Add34~121_sumout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\);
-
--- Location: LABCELL_X20_Y24_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_BDD9276\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\ ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\ ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~2_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13464_BDD13465\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|PROCESSOR~6_combout\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|Mux149~20_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|LessThan10~4_combout\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_RESYN13466_BDD13467\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000001100100011011111111111111111111111111111111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_PROCESSOR~6_combout\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_Mux149~20_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_LessThan10~4_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13466_BDD13467\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~2_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~148_RESYN9275_RESYN13464_BDD13465\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~148_RESYN9275_BDD9276\);
-
--- Location: LABCELL_X20_Y24_N45
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~137\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~137_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|RotateRight0~31_combout\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\)) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|TOS~90_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[30]~22_Duplicate_66\ ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000111100001111000011110000111100000000000001010000000000000101",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_RotateRight0~31_combout\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[30]~22_Duplicate_66\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS~90_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~137_combout\);
-
--- Location: LABCELL_X19_Y22_N9
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~18_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) +
--- ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[23]~4_Duplicate_59\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000110011010101010",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[23]~4_Duplicate_59\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~11\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~18_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\);
-
--- Location: LABCELL_X19_Y22_N12
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~120\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[24]~27_Duplicate_64\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[24]~27_Duplicate_64\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~19\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~120_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\);
-
--- Location: LABCELL_X19_Y22_N15
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~116\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~116_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[25]~26_Duplicate_60\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111011110001000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[25]~26_Duplicate_60\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~121\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~116_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\);
-
--- Location: LABCELL_X19_Y22_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~112\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[26]~25_Duplicate_62\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011111111000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[26]~25_Duplicate_62\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~117\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~112_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\);
-
--- Location: LABCELL_X19_Y22_N21
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~108\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[27]~24_Duplicate_58\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[27]~24_Duplicate_58\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~113\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~108_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\);
-
--- Location: LABCELL_X19_Y22_N24
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~124\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~124_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[28]~28_Duplicate_65\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000011111111000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[28]~28_Duplicate_65\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~109\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~124_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\);
-
--- Location: LABCELL_X19_Y22_N27
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~128\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~128_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[29]~29_Duplicate_69\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000101111110100000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[29]~29_Duplicate_69\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~125\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~128_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\);
-
--- Location: LABCELL_X19_Y22_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|Add36~132\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\ = SUM(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND )
--- + ( \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\ ))
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~133\ = CARRY(( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[30]~30_Duplicate_70\ $ (((!\myVirtualToplevel|ZPUEVO:ZPU0|mxTOS.valid~DUPLICATE_q\ & !\myVirtualToplevel|ZPUEVO:ZPU0|TOS.valid~DUPLICATE_q\))) ) + ( GND ) + (
--- \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\ ))
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000111111111111111100000000000000000111100001111000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_mxTOS.valid~DUPLICATE_q\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_TOS.valid~DUPLICATE_q\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[30]~30_Duplicate_70\,
- cin => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~129\,
- sumout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~132_sumout\,
- cout => \myVirtualToplevel|ZPUEVO:ZPU0|Add36~133\);
-
--- Location: LABCELL_X14_Y20_N18
-\myVirtualToplevel|ZPUEVO:ZPU0|TOS~144\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[31]~31_Duplicate_62\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[4]~12_Duplicate_41\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftRight0~0_combout\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000000000000000000000110000000000000000000000000000000000000000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftRight0~0_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[31]~31_Duplicate_62\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[4]~12_Duplicate_41\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|TOS~144_combout\);
-
--- Location: LABCELL_X16_Y17_N30
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[8]~25_Duplicate_33\) ) ) ) # (
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[7]~14_Duplicate_46\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[10]~26_Duplicate_35\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[9]~28_Duplicate_36\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0010001001110111001000100111011100001010000010100101111101011111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[10]~26_Duplicate_35\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[8]~25_Duplicate_33\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[9]~28_Duplicate_36\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[7]~14_Duplicate_46\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\);
-
--- Location: LABCELL_X16_Y18_N42
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\
--- & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[0]~0_Duplicate_44\ & !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[1]~12_Duplicate_42\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[2]~2_Duplicate_43\ &
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0011000000110000001111110011111101010000010100000101000001010000",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[0]~0_Duplicate_44\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[2]~2_Duplicate_43\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[1]~12_Duplicate_42\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\);
-
--- Location: LABCELL_X16_Y18_N36
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[12]~6_Duplicate_40\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- ((\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[11]~27_Duplicate_34\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[14]~9_Duplicate_38\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & ( (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[13]~5_Duplicate_39\) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010100000101101011111010111100100010011101110010001001110111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[12]~6_Duplicate_40\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[13]~5_Duplicate_39\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[11]~27_Duplicate_34\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[14]~9_Duplicate_38\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\);
-
--- Location: LABCELL_X19_Y19_N48
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[3]~11_Duplicate_41\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[6]~13_Duplicate_48\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ & \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[4]~16_Duplicate_45\)))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[5]~15_Duplicate_47\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0001000000011010000101010001111110110000101110101011010110111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[0]~22_Duplicate_38\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[5]~15_Duplicate_47\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[1]~23_Duplicate_34\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[4]~16_Duplicate_45\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[3]~11_Duplicate_41\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxNOS.word[6]~13_Duplicate_48\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\);
-
--- Location: MLABCELL_X13_Y18_N54
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\) #
--- ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\)))) )
--- ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\))))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\))))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~14_combout\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~19_combout\ & (
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[2]~21_Duplicate_37\ & ((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & (\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~16_combout\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[3]~20_Duplicate_33\ & ((\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~18_combout\))))) ) ) )
-
--- pragma translate_off
-GENERIC MAP (
- extended_lut => "off",
- lut_mask => "0000010000010101100011001001110100100110001101111010111010111111",
- shared_arith => "off")
--- pragma translate_on
-PORT MAP (
- dataa => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[2]~21_Duplicate_37\,
- datab => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_muxTOS.word[3]~20_Duplicate_33\,
- datac => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~16_combout\,
- datad => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~18_combout\,
- datae => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~14_combout\,
- dataf => \myVirtualToplevel|ZPUEVO:ZPU0|ALT_INV_ShiftLeft0~19_combout\,
- combout => \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~36_combout\);
-
--- Location: MLABCELL_X13_Y18_N0
-\myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13\ : cyclonev_lcell_comb
--- Equation(s):
--- \myVirtualToplevel|ZPUEVO:ZPU0|ShiftLeft0~13_combout\ = ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) ) ) ) # (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ &
--- (((!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) ) ) ) # ( \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & (
--- !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & ( (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\)) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\))) # (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ &
--- \myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[19]~8_Duplicate_49\)))) ) ) ) # ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[20]~7_Duplicate_53\ & ( !\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[21]~30_Duplicate_57\ & (
--- (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (\myVirtualToplevel|ZPUEVO:ZPU0|muxNOS.word[22]~29_Duplicate_59\ & (!\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\))) #
--- (\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[0]~22_Duplicate_38\ & (((\myVirtualToplevel|ZPUEVO:ZPU0|muxTOS.word[1]~23_Duplicate_34\ &